arch/parisc/kernel/unaligned.c

   1 /*
   2  *    Unaligned memory access handler
   3  *
   4  *    Copyright (C) 2001 Randolph Chung <tausq@debian.org>
   5  *    Significantly tweaked by LaMont Jones <lamont@debian.org>
   6  *
   7  *    This program is free software; you can redistribute it and/or modify
   8  *    it under the terms of the GNU General Public License as published by
   9  *    the Free Software Foundation; either version 2, or (at your option)
  10  *    any later version.
  11  *
  12  *    This program is distributed in the hope that it will be useful,
  13  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *    GNU General Public License for more details.
  16  *
  17  *    You should have received a copy of the GNU General Public License
  18  *    along with this program; if not, write to the Free Software
  19  *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  *
  21  */
  22
  23 #include <linux/jiffies.h>
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/sched.h>
  27 #include <linux/signal.h>
  28 #include <asm/uaccess.h>
  29
  30 /* #define DEBUG_UNALIGNED 1 */
  31
  32 #ifdef DEBUG_UNALIGNED
  33 #define DPRINTF(fmt, args...) do { printk(KERN_DEBUG "%s:%d:%s ", __FILE__, __LINE__, __FUNCTION__ ); printk(KERN_DEBUG fmt, ##args ); } while (0)
  34 #else
  35 #define DPRINTF(fmt, args...)
  36 #endif
  37
  38 #ifdef __LP64__
  39 #define RFMT "%016lx"
  40 #else
  41 #define RFMT "%08lx"
  42 #endif
  43
  44 #define FIXUP_BRANCH(lbl) \
  45         "\tldil L%%" #lbl ", %%r1\n"                    \
  46         "\tldo R%%" #lbl "(%%r1), %%r1\n"               \
  47         "\tbv,n %%r0(%%r1)\n"
  48 /* If you use FIXUP_BRANCH, then you must list this clobber */
  49 #define FIXUP_BRANCH_CLOBBER "r1"
  50
  51 /* 1111 1100 0000 0000 0001 0011 1100 0000 */
  52 #define OPCODE1(a,b,c)  ((a)<<26|(b)<<12|(c)<<6)
  53 #define OPCODE2(a,b)    ((a)<<26|(b)<<1)
  54 #define OPCODE3(a,b)    ((a)<<26|(b)<<2)
  55 #define OPCODE4(a)      ((a)<<26)
  56 #define OPCODE1_MASK    OPCODE1(0x3f,1,0xf)
  57 #define OPCODE2_MASK    OPCODE2(0x3f,1)
  58 #define OPCODE3_MASK    OPCODE3(0x3f,1)
  59 #define OPCODE4_MASK    OPCODE4(0x3f)
  60
  61 /* skip LDB - never unaligned (index) */
  62 #define OPCODE_LDH_I    OPCODE1(0x03,0,0x1)
  63 #define OPCODE_LDW_I    OPCODE1(0x03,0,0x2)
  64 #define OPCODE_LDD_I    OPCODE1(0x03,0,0x3)
  65 #define OPCODE_LDDA_I   OPCODE1(0x03,0,0x4)
  66 #define OPCODE_LDCD_I   OPCODE1(0x03,0,0x5)
  67 #define OPCODE_LDWA_I   OPCODE1(0x03,0,0x6)
  68 #define OPCODE_LDCW_I   OPCODE1(0x03,0,0x7)
  69 /* skip LDB - never unaligned (short) */
  70 #define OPCODE_LDH_S    OPCODE1(0x03,1,0x1)
  71 #define OPCODE_LDW_S    OPCODE1(0x03,1,0x2)
  72 #define OPCODE_LDD_S    OPCODE1(0x03,1,0x3)
  73 #define OPCODE_LDDA_S   OPCODE1(0x03,1,0x4)
  74 #define OPCODE_LDCD_S   OPCODE1(0x03,1,0x5)
  75 #define OPCODE_LDWA_S   OPCODE1(0x03,1,0x6)
  76 #define OPCODE_LDCW_S   OPCODE1(0x03,1,0x7)
  77 /* skip STB - never unaligned */
  78 #define OPCODE_STH      OPCODE1(0x03,1,0x9)
  79 #define OPCODE_STW      OPCODE1(0x03,1,0xa)
  80 #define OPCODE_STD      OPCODE1(0x03,1,0xb)
  81 /* skip STBY - never unaligned */
  82 /* skip STDBY - never unaligned */
  83 #define OPCODE_STWA     OPCODE1(0x03,1,0xe)
  84 #define OPCODE_STDA     OPCODE1(0x03,1,0xf)
  85
  86 #define OPCODE_FLDWX    OPCODE1(0x09,0,0x0)
  87 #define OPCODE_FLDWXR   OPCODE1(0x09,0,0x1)
  88 #define OPCODE_FSTWX    OPCODE1(0x09,0,0x8)
  89 #define OPCODE_FSTWXR   OPCODE1(0x09,0,0x9)
  90 #define OPCODE_FLDWS    OPCODE1(0x09,1,0x0)
  91 #define OPCODE_FLDWSR   OPCODE1(0x09,1,0x1)
  92 #define OPCODE_FSTWS    OPCODE1(0x09,1,0x8)
  93 #define OPCODE_FSTWSR   OPCODE1(0x09,1,0x9)
  94 #define OPCODE_FLDDX    OPCODE1(0x0b,0,0x0)
  95 #define OPCODE_FSTDX    OPCODE1(0x0b,0,0x8)
  96 #define OPCODE_FLDDS    OPCODE1(0x0b,1,0x0)
  97 #define OPCODE_FSTDS    OPCODE1(0x0b,1,0x8)
  98
  99 #define OPCODE_LDD_L    OPCODE2(0x14,0)
 100 #define OPCODE_FLDD_L   OPCODE2(0x14,1)
 101 #define OPCODE_STD_L    OPCODE2(0x1c,0)
 102 #define OPCODE_FSTD_L   OPCODE2(0x1c,1)
 103
 104 #define OPCODE_LDW_M    OPCODE3(0x17,1)
 105 #define OPCODE_FLDW_L   OPCODE3(0x17,0)
 106 #define OPCODE_FSTW_L   OPCODE3(0x1f,0)
 107 #define OPCODE_STW_M    OPCODE3(0x1f,1)
 108
 109 #define OPCODE_LDH_L    OPCODE4(0x11)
 110 #define OPCODE_LDW_L    OPCODE4(0x12)
 111 #define OPCODE_LDWM     OPCODE4(0x13)
 112 #define OPCODE_STH_L    OPCODE4(0x19)
 113 #define OPCODE_STW_L    OPCODE4(0x1A)
 114 #define OPCODE_STWM     OPCODE4(0x1B)
 115
 116 #define MAJOR_OP(i) (((i)>>26)&0x3f)
 117 #define R1(i) (((i)>>21)&0x1f)
 118 #define R2(i) (((i)>>16)&0x1f)
 119 #define R3(i) ((i)&0x1f)
 120 #define FR3(i) ((((i)<<1)&0x1f)|(((i)>>6)&1))
 121 #define IM(i,n) (((i)>>1&((1<<(n-1))-1))|((i)&1?((0-1L)<<(n-1)):0))
 122 #define IM5_2(i) IM((i)>>16,5)
 123 #define IM5_3(i) IM((i),5)
 124 #define IM14(i) IM((i),14)
 125
 126 #define ERR_NOTHANDLED  -1
 127 #define ERR_PAGEFAULT   -2
 128
 129 int unaligned_enabled __read_mostly = 1;
 130
 131 void die_if_kernel (char *str, struct pt_regs *regs, long err);
 132
 133 static int emulate_ldh(struct pt_regs *regs, int toreg)
 134 {
 135         unsigned long saddr = regs->ior;
 136         unsigned long val = 0;
 137         int ret;
 138
 139         DPRINTF("load " RFMT ":" RFMT " to r%d for 2 bytes\n",
 140                 regs->isr, regs->ior, toreg);
 141
 142         __asm__ __volatile__  (
 143 "       mtsp    %4, %%sr1\n"
 144 "1:     ldbs    0(%%sr1,%3), %%r20\n"
 145 "2:     ldbs    1(%%sr1,%3), %0\n"
 146 "       depw    %%r20, 23, 24, %0\n"
 147 "       copy    %%r0, %1\n"
 148 "3:     \n"
 149 "       .section .fixup,\"ax\"\n"
 150 "4:     ldi     -2, %1\n"
 151         FIXUP_BRANCH(3b)
 152 "       .previous\n"
 153 "       .section __ex_table,\"aw\"\n"
 154 #ifdef __LP64__
 155 "       .dword  1b,4b\n"
 156 "       .dword  2b,4b\n"
 157 #else
 158 "       .word   1b,4b\n"
 159 "       .word   2b,4b\n"
 160 #endif
 161 "       .previous\n"
 162         : "=r" (val), "=r" (ret)
 163         : "0" (val), "r" (saddr), "r" (regs->isr)
 164         : "r20", FIXUP_BRANCH_CLOBBER );
 165
 166         DPRINTF("val = 0x" RFMT "\n", val);
 167
 168         if (toreg)
 169                 regs->gr[toreg] = val;
 170
 171         return ret;
 172 }
 173
 174 static int emulate_ldw(struct pt_regs *regs, int toreg, int flop)
 175 {
 176         unsigned long saddr = regs->ior;
 177         unsigned long val = 0;
 178         int ret;
 179
 180         DPRINTF("load " RFMT ":" RFMT " to r%d for 4 bytes\n",
 181                 regs->isr, regs->ior, toreg);
 182
 183         __asm__ __volatile__  (
 184 "       zdep    %3,28,2,%%r19\n"                /* r19=(ofs&3)*8 */
 185 "       mtsp    %4, %%sr1\n"
 186 "       depw    %%r0,31,2,%3\n"
 187 "1:     ldw     0(%%sr1,%3),%0\n"
 188 "2:     ldw     4(%%sr1,%3),%%r20\n"
 189 "       subi    32,%%r19,%%r19\n"
 190 "       mtctl   %%r19,11\n"
 191 "       vshd    %0,%%r20,%0\n"
 192 "       copy    %%r0, %1\n"
 193 "3:     \n"
 194 "       .section .fixup,\"ax\"\n"
 195 "4:     ldi     -2, %1\n"
 196         FIXUP_BRANCH(3b)
 197 "       .previous\n"
 198 "       .section __ex_table,\"aw\"\n"
 199 #ifdef __LP64__
 200 "       .dword  1b,4b\n"
 201 "       .dword  2b,4b\n"
 202 #else
 203 "       .word   1b,4b\n"
 204 "       .word   2b,4b\n"
 205 #endif
 206 "       .previous\n"
 207         : "=r" (val), "=r" (ret)
 208         : "0" (val), "r" (saddr), "r" (regs->isr)
 209         : "r19", "r20", FIXUP_BRANCH_CLOBBER );
 210
 211         DPRINTF("val = 0x" RFMT "\n", val);
 212
 213         if (flop)
 214                 ((__u32*)(regs->fr))[toreg] = val;
 215         else if (toreg)
 216                 regs->gr[toreg] = val;
 217
 218         return ret;
 219 }
 220 static int emulate_ldd(struct pt_regs *regs, int toreg, int flop)
 221 {
 222         unsigned long saddr = regs->ior;
 223         __u64 val = 0;
 224         int ret;
 225
 226         DPRINTF("load " RFMT ":" RFMT " to r%d for 8 bytes\n",
 227                 regs->isr, regs->ior, toreg);
 228 #ifdef CONFIG_PA20
 229
 230 #ifndef __LP64__
 231         if (!flop)
 232                 return -1;
 233 #endif
 234         __asm__ __volatile__  (
 235 "       depd,z  %3,60,3,%%r19\n"                /* r19=(ofs&7)*8 */
 236 "       mtsp    %4, %%sr1\n"
 237 "       depd    %%r0,63,3,%3\n"
 238 "1:     ldd     0(%%sr1,%3),%0\n"
 239 "2:     ldd     8(%%sr1,%3),%%r20\n"
 240 "       subi    64,%%r19,%%r19\n"
 241 "       mtsar   %%r19\n"
 242 "       shrpd   %0,%%r20,%%sar,%0\n"
 243 "       copy    %%r0, %1\n"
 244 "3:     \n"
 245 "       .section .fixup,\"ax\"\n"
 246 "4:     ldi     -2, %1\n"
 247         FIXUP_BRANCH(3b)
 248 "       .previous\n"
 249 "       .section __ex_table,\"aw\"\n"
 250 #ifdef __LP64__
 251 "       .dword  1b,4b\n"
 252 "       .dword  2b,4b\n"
 253 #else
 254 "       .word   1b,4b\n"
 255 "       .word   2b,4b\n"
 256 #endif
 257 "       .previous\n"
 258         : "=r" (val), "=r" (ret)
 259         : "0" (val), "r" (saddr), "r" (regs->isr)
 260         : "r19", "r20", FIXUP_BRANCH_CLOBBER );
 261 #else
 262     {
 263         unsigned long valh=0,vall=0;
 264         __asm__ __volatile__  (
 265 "       zdep    %5,29,2,%%r19\n"                /* r19=(ofs&3)*8 */
 266 "       mtsp    %6, %%sr1\n"
 267 "       dep     %%r0,31,2,%5\n"
 268 "1:     ldw     0(%%sr1,%5),%0\n"
 269 "2:     ldw     4(%%sr1,%5),%1\n"
 270 "3:     ldw     8(%%sr1,%5),%%r20\n"
 271 "       subi    32,%%r19,%%r19\n"
 272 "       mtsar   %%r19\n"
 273 "       vshd    %0,%1,%0\n"
 274 "       vshd    %1,%%r20,%1\n"
 275 "       copy    %%r0, %2\n"
 276 "4:     \n"
 277 "       .section .fixup,\"ax\"\n"
 278 "5:     ldi     -2, %2\n"
 279         FIXUP_BRANCH(4b)
 280 "       .previous\n"
 281 "       .section __ex_table,\"aw\"\n"
 282 #ifdef __LP64__
 283 "       .dword  1b,5b\n"
 284 "       .dword  2b,5b\n"
 285 "       .dword  3b,5b\n"
 286 #else
 287 "       .word   1b,5b\n"
 288 "       .word   2b,5b\n"
 289 "       .word   3b,5b\n"
 290 #endif
 291 "       .previous\n"
 292         : "=r" (valh), "=r" (vall), "=r" (ret)
 293         : "0" (valh), "1" (vall), "r" (saddr), "r" (regs->isr)
 294         : "r19", "r20", FIXUP_BRANCH_CLOBBER );
 295         val=((__u64)valh<<32)|(__u64)vall;
 296     }
 297 #endif
 298
 299         DPRINTF("val = 0x%llx\n", val);
 300
 301         if (flop)
 302                 regs->fr[toreg] = val;
 303         else if (toreg)
 304                 regs->gr[toreg] = val;
 305
 306         return ret;
 307 }
 308
 309 static int emulate_sth(struct pt_regs *regs, int frreg)
 310 {
 311         unsigned long val = regs->gr[frreg];
 312         int ret;
 313
 314         if (!frreg)
 315                 val = 0;
 316
 317         DPRINTF("store r%d (0x" RFMT ") to " RFMT ":" RFMT " for 2 bytes\n", frreg,
 318                 val, regs->isr, regs->ior);
 319
 320         __asm__ __volatile__ (
 321 "       mtsp %3, %%sr1\n"
 322 "       extrw,u %1, 23, 8, %%r19\n"
 323 "1:     stb %1, 1(%%sr1, %2)\n"
 324 "2:     stb %%r19, 0(%%sr1, %2)\n"
 325 "       copy    %%r0, %0\n"
 326 "3:     \n"
 327 "       .section .fixup,\"ax\"\n"
 328 "4:     ldi     -2, %0\n"
 329         FIXUP_BRANCH(3b)
 330 "       .previous\n"
 331 "       .section __ex_table,\"aw\"\n"
 332 #ifdef __LP64__
 333 "       .dword  1b,4b\n"
 334 "       .dword  2b,4b\n"
 335 #else
 336 "       .word   1b,4b\n"
 337 "       .word   2b,4b\n"
 338 #endif
 339 "       .previous\n"
 340         : "=r" (ret)
 341         : "r" (val), "r" (regs->ior), "r" (regs->isr)
 342         : "r19", FIXUP_BRANCH_CLOBBER );
 343
 344         return ret;
 345 }
 346
 347 static int emulate_stw(struct pt_regs *regs, int frreg, int flop)
 348 {
 349         unsigned long val;
 350         int ret;
 351
 352         if (flop)
 353                 val = ((__u32*)(regs->fr))[frreg];
 354         else if (frreg)
 355                 val = regs->gr[frreg];
 356         else
 357                 val = 0;
 358
 359         DPRINTF("store r%d (0x" RFMT ") to " RFMT ":" RFMT " for 4 bytes\n", frreg,
 360                 val, regs->isr, regs->ior);
 361
 362
 363         __asm__ __volatile__ (
 364 "       mtsp %3, %%sr1\n"
 365 "       zdep    %2, 28, 2, %%r19\n"
 366 "       dep     %%r0, 31, 2, %2\n"
 367 "       mtsar   %%r19\n"
 368 "       depwi,z -2, %%sar, 32, %%r19\n"
 369 "1:     ldw     0(%%sr1,%2),%%r20\n"
 370 "2:     ldw     4(%%sr1,%2),%%r21\n"
 371 "       vshd    %%r0, %1, %%r22\n"
 372 "       vshd    %1, %%r0, %%r1\n"
 373 "       and     %%r20, %%r19, %%r20\n"
 374 "       andcm   %%r21, %%r19, %%r21\n"
 375 "       or      %%r22, %%r20, %%r20\n"
 376 "       or      %%r1, %%r21, %%r21\n"
 377 "       stw     %%r20,0(%%sr1,%2)\n"
 378 "       stw     %%r21,4(%%sr1,%2)\n"
 379 "       copy    %%r0, %0\n"
 380 "3:     \n"
 381 "       .section .fixup,\"ax\"\n"
 382 "4:     ldi     -2, %0\n"
 383         FIXUP_BRANCH(3b)
 384 "       .previous\n"
 385 "       .section __ex_table,\"aw\"\n"
 386 #ifdef __LP64__
 387 "       .dword  1b,4b\n"
 388 "       .dword  2b,4b\n"
 389 #else
 390 "       .word   1b,4b\n"
 391 "       .word   2b,4b\n"
 392 #endif
 393 "       .previous\n"
 394         : "=r" (ret)
 395         : "r" (val), "r" (regs->ior), "r" (regs->isr)
 396         : "r19", "r20", "r21", "r22", "r1", FIXUP_BRANCH_CLOBBER );
 397
 398         return 0;
 399 }
 400 static int emulate_std(struct pt_regs *regs, int frreg, int flop)
 401 {
 402         __u64 val;
 403         int ret;
 404
 405         if (flop)
 406                 val = regs->fr[frreg];
 407         else if (frreg)
 408                 val = regs->gr[frreg];
 409         else
 410                 val = 0;
 411
 412         DPRINTF("store r%d (0x%016llx) to " RFMT ":" RFMT " for 8 bytes\n", frreg,
 413                 val,  regs->isr, regs->ior);
 414
 415 #ifdef CONFIG_PA20
 416 #ifndef __LP64__
 417         if (!flop)
 418                 return -1;
 419 #endif
 420         __asm__ __volatile__ (
 421 "       mtsp %3, %%sr1\n"
 422 "       depd,z  %2, 60, 3, %%r19\n"
 423 "       depd    %%r0, 63, 3, %2\n"
 424 "       mtsar   %%r19\n"
 425 "       depdi,z -2, %%sar, 64, %%r19\n"
 426 "1:     ldd     0(%%sr1,%2),%%r20\n"
 427 "2:     ldd     8(%%sr1,%2),%%r21\n"
 428 "       shrpd   %%r0, %1, %%sar, %%r22\n"
 429 "       shrpd   %1, %%r0, %%sar, %%r1\n"
 430 "       and     %%r20, %%r19, %%r20\n"
 431 "       andcm   %%r21, %%r19, %%r21\n"
 432 "       or      %%r22, %%r20, %%r20\n"
 433 "       or      %%r1, %%r21, %%r21\n"
 434 "3:     std     %%r20,0(%%sr1,%2)\n"
 435 "4:     std     %%r21,8(%%sr1,%2)\n"
 436 "       copy    %%r0, %0\n"
 437 "5:     \n"
 438 "       .section .fixup,\"ax\"\n"
 439 "6:     ldi     -2, %0\n"
 440         FIXUP_BRANCH(5b)
 441 "       .previous\n"
 442 "       .section __ex_table,\"aw\"\n"
 443 #ifdef __LP64__
 444 "       .dword  1b,6b\n"
 445 "       .dword  2b,6b\n"
 446 "       .dword  3b,6b\n"
 447 "       .dword  4b,6b\n"
 448 #else
 449 "       .word   1b,6b\n"
 450 "       .word   2b,6b\n"
 451 "       .word   3b,6b\n"
 452 "       .word   4b,6b\n"
 453 #endif
 454 "       .previous\n"
 455         : "=r" (ret)
 456         : "r" (val), "r" (regs->ior), "r" (regs->isr)
 457         : "r19", "r20", "r21", "r22", "r1", FIXUP_BRANCH_CLOBBER );
 458 #else
 459     {
 460         unsigned long valh=(val>>32),vall=(val&0xffffffffl);
 461         __asm__ __volatile__ (
 462 "       mtsp    %4, %%sr1\n"
 463 "       zdep    %2, 29, 2, %%r19\n"
 464 "       dep     %%r0, 31, 2, %2\n"
 465 "       mtsar   %%r19\n"
 466 "       zvdepi  -2, 32, %%r19\n"
 467 "1:     ldw     0(%%sr1,%3),%%r20\n"
 468 "2:     ldw     8(%%sr1,%3),%%r21\n"
 469 "       vshd    %1, %2, %%r1\n"
 470 "       vshd    %%r0, %1, %1\n"
 471 "       vshd    %2, %%r0, %2\n"
 472 "       and     %%r20, %%r19, %%r20\n"
 473 "       andcm   %%r21, %%r19, %%r21\n"
 474 "       or      %1, %%r20, %1\n"
 475 "       or      %2, %%r21, %2\n"
 476 "3:     stw     %1,0(%%sr1,%1)\n"
 477 "4:     stw     %%r1,4(%%sr1,%3)\n"
 478 "5:     stw     %2,8(%%sr1,%3)\n"
 479 "       copy    %%r0, %0\n"
 480 "6:     \n"
 481 "       .section .fixup,\"ax\"\n"
 482 "7:     ldi     -2, %0\n"
 483         FIXUP_BRANCH(6b)
 484 "       .previous\n"
 485 "       .section __ex_table,\"aw\"\n"
 486 #ifdef __LP64__
 487 "       .dword  1b,7b\n"
 488 "       .dword  2b,7b\n"
 489 "       .dword  3b,7b\n"
 490 "       .dword  4b,7b\n"
 491 "       .dword  5b,7b\n"
 492 #else
 493 "       .word   1b,7b\n"
 494 "       .word   2b,7b\n"
 495 "       .word   3b,7b\n"
 496 "       .word   4b,7b\n"
 497 "       .word   5b,7b\n"
 498 #endif
 499 "       .previous\n"
 500         : "=r" (ret)
 501         : "r" (valh), "r" (vall), "r" (regs->ior), "r" (regs->isr)
 502         : "r19", "r20", "r21", "r1", FIXUP_BRANCH_CLOBBER );
 503     }
 504 #endif
 505
 506         return ret;
 507 }
 508
 509 void handle_unaligned(struct pt_regs *regs)
 510 {
 511         static unsigned long unaligned_count = 0;
 512         static unsigned long last_time = 0;
 513         unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0;
 514         int modify = 0;
 515         int ret = ERR_NOTHANDLED;
 516         struct siginfo si;
 517         register int flop=0;    /* true if this is a flop */
 518
 519         /* log a message with pacing */
 520         if (user_mode(regs)) {
 521                 if (current->thread.flags & PARISC_UAC_SIGBUS) {
 522                         goto force_sigbus;
 523                 }
 524
 525                 if (unaligned_count > 5 && jiffies - last_time > 5*HZ) {
 526                         unaligned_count = 0;
 527                         last_time = jiffies;
 528                 }
 529
 530                 if (!(current->thread.flags & PARISC_UAC_NOPRINT)
 531                     && ++unaligned_count < 5) {
 532                         char buf[256];
 533                         sprintf(buf, "%s(%d): unaligned access to 0x" RFMT " at ip=0x" RFMT "\n",
 534                                 current->comm, current->pid, regs->ior, regs->iaoq[0]);
 535                         printk(KERN_WARNING "%s", buf);
 536 #ifdef DEBUG_UNALIGNED
 537                         show_regs(regs);
 538 #endif
 539                 }
 540
 541                 if (!unaligned_enabled)
 542                         goto force_sigbus;
 543         }
 544
 545         /* handle modification - OK, it's ugly, see the instruction manual */
 546         switch (MAJOR_OP(regs->iir))
 547         {
 548         case 0x03:
 549         case 0x09:
 550         case 0x0b:
 551                 if (regs->iir&0x20)
 552                 {
 553                         modify = 1;
 554                         if (regs->iir&0x1000)           /* short loads */
 555                                 if (regs->iir&0x200)
 556                                         newbase += IM5_3(regs->iir);
 557                                 else
 558                                         newbase += IM5_2(regs->iir);
 559                         else if (regs->iir&0x2000)      /* scaled indexed */
 560                         {
 561                                 int shift=0;
 562                                 switch (regs->iir & OPCODE1_MASK)
 563                                 {
 564                                 case OPCODE_LDH_I:
 565                                         shift= 1; break;
 566                                 case OPCODE_LDW_I:
 567                                         shift= 2; break;
 568                                 case OPCODE_LDD_I:
 569                                 case OPCODE_LDDA_I:
 570                                         shift= 3; break;
 571                                 }
 572                                 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0)<<shift;
 573                         } else                          /* simple indexed */
 574                                 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0);
 575                 }
 576                 break;
 577         case 0x13:
 578         case 0x1b:
 579                 modify = 1;
 580                 newbase += IM14(regs->iir);
 581                 break;
 582         case 0x14:
 583         case 0x1c:
 584                 if (regs->iir&8)
 585                 {
 586                         modify = 1;
 587                         newbase += IM14(regs->iir&~0xe);
 588                 }
 589                 break;
 590         case 0x16:
 591         case 0x1e:
 592                 modify = 1;
 593                 newbase += IM14(regs->iir&6);
 594                 break;
 595         case 0x17:
 596         case 0x1f:
 597                 if (regs->iir&4)
 598                 {
 599                         modify = 1;
 600                         newbase += IM14(regs->iir&~4);
 601                 }
 602                 break;
 603         }
 604
 605         /* TODO: make this cleaner... */
 606         switch (regs->iir & OPCODE1_MASK)
 607         {
 608         case OPCODE_LDH_I:
 609         case OPCODE_LDH_S:
 610                 ret = emulate_ldh(regs, R3(regs->iir));
 611                 break;
 612
 613         case OPCODE_LDW_I:
 614         case OPCODE_LDWA_I:
 615         case OPCODE_LDW_S:
 616         case OPCODE_LDWA_S:
 617                 ret = emulate_ldw(regs, R3(regs->iir),0);
 618                 break;
 619
 620         case OPCODE_STH:
 621                 ret = emulate_sth(regs, R2(regs->iir));
 622                 break;
 623
 624         case OPCODE_STW:
 625         case OPCODE_STWA:
 626                 ret = emulate_stw(regs, R2(regs->iir),0);
 627                 break;
 628
 629 #ifdef CONFIG_PA20
 630         case OPCODE_LDD_I:
 631         case OPCODE_LDDA_I:
 632         case OPCODE_LDD_S:
 633         case OPCODE_LDDA_S:
 634                 ret = emulate_ldd(regs, R3(regs->iir),0);
 635                 break;
 636
 637         case OPCODE_STD:
 638         case OPCODE_STDA:
 639                 ret = emulate_std(regs, R2(regs->iir),0);
 640                 break;
 641 #endif
 642
 643         case OPCODE_FLDWX:
 644         case OPCODE_FLDWS:
 645         case OPCODE_FLDWXR:
 646         case OPCODE_FLDWSR:
 647                 flop=1;
 648                 ret = emulate_ldw(regs,FR3(regs->iir),1);
 649                 break;
 650
 651         case OPCODE_FLDDX:
 652         case OPCODE_FLDDS:
 653                 flop=1;
 654                 ret = emulate_ldd(regs,R3(regs->iir),1);
 655                 break;
 656
 657         case OPCODE_FSTWX:
 658         case OPCODE_FSTWS:
 659         case OPCODE_FSTWXR:
 660         case OPCODE_FSTWSR:
 661                 flop=1;
 662                 ret = emulate_stw(regs,FR3(regs->iir),1);
 663                 break;
 664
 665         case OPCODE_FSTDX:
 666         case OPCODE_FSTDS:
 667                 flop=1;
 668                 ret = emulate_std(regs,R3(regs->iir),1);
 669                 break;
 670
 671         case OPCODE_LDCD_I:
 672         case OPCODE_LDCW_I:
 673         case OPCODE_LDCD_S:
 674         case OPCODE_LDCW_S:
 675                 ret = ERR_NOTHANDLED;   /* "undefined", but lets kill them. */
 676                 break;
 677         }
 678 #ifdef CONFIG_PA20
 679         switch (regs->iir & OPCODE2_MASK)
 680         {
 681         case OPCODE_FLDD_L:
 682                 flop=1;
 683                 ret = emulate_ldd(regs,R2(regs->iir),1);
 684                 break;
 685         case OPCODE_FSTD_L:
 686                 flop=1;
 687                 ret = emulate_std(regs, R2(regs->iir),1);
 688                 break;
 689
 690 #ifdef CONFIG_PA20
 691         case OPCODE_LDD_L:
 692                 ret = emulate_ldd(regs, R2(regs->iir),0);
 693                 break;
 694         case OPCODE_STD_L:
 695                 ret = emulate_std(regs, R2(regs->iir),0);
 696                 break;
 697 #endif
 698         }
 699 #endif
 700         switch (regs->iir & OPCODE3_MASK)
 701         {
 702         case OPCODE_FLDW_L:
 703                 flop=1;
 704                 ret = emulate_ldw(regs, R2(regs->iir),0);
 705                 break;
 706         case OPCODE_LDW_M:
 707                 ret = emulate_ldw(regs, R2(regs->iir),1);
 708                 break;
 709
 710         case OPCODE_FSTW_L:
 711                 flop=1;
 712                 ret = emulate_stw(regs, R2(regs->iir),1);
 713                 break;
 714         case OPCODE_STW_M:
 715                 ret = emulate_stw(regs, R2(regs->iir),0);
 716                 break;
 717         }
 718         switch (regs->iir & OPCODE4_MASK)
 719         {
 720         case OPCODE_LDH_L:
 721                 ret = emulate_ldh(regs, R2(regs->iir));
 722                 break;
 723         case OPCODE_LDW_L:
 724         case OPCODE_LDWM:
 725                 ret = emulate_ldw(regs, R2(regs->iir),0);
 726                 break;
 727         case OPCODE_STH_L:
 728                 ret = emulate_sth(regs, R2(regs->iir));
 729                 break;
 730         case OPCODE_STW_L:
 731         case OPCODE_STWM:
 732                 ret = emulate_stw(regs, R2(regs->iir),0);
 733                 break;
 734         }
 735
 736         if (modify && R1(regs->iir))
 737                 regs->gr[R1(regs->iir)] = newbase;
 738
 739
 740         if (ret == ERR_NOTHANDLED)
 741                 printk(KERN_CRIT "Not-handled unaligned insn 0x%08lx\n", regs->iir);
 742
 743         DPRINTF("ret = %d\n", ret);
 744
 745         if (ret)
 746         {
 747                 printk(KERN_CRIT "Unaligned handler failed, ret = %d\n", ret);
 748                 die_if_kernel("Unaligned data reference", regs, 28);
 749
 750                 if (ret == ERR_PAGEFAULT)
 751                 {
 752                         si.si_signo = SIGSEGV;
 753                         si.si_errno = 0;
 754                         si.si_code = SEGV_MAPERR;
 755                         si.si_addr = (void __user *)regs->ior;
 756                         force_sig_info(SIGSEGV, &si, current);
 757                 }
 758                 else
 759                 {
 760 force_sigbus:
 761                         /* couldn't handle it ... */
 762                         si.si_signo = SIGBUS;
 763                         si.si_errno = 0;
 764                         si.si_code = BUS_ADRALN;
 765                         si.si_addr = (void __user *)regs->ior;
 766                         force_sig_info(SIGBUS, &si, current);
 767                 }
 768
 769                 return;
 770         }
 771
 772         /* else we handled it, let life go on. */
 773         regs->gr[0]|=PSW_N;
 774 }
 775
 776 /*
 777  * NB: check_unaligned() is only used for PCXS processors right
 778  * now, so we only check for PA1.1 encodings at this point.
 779  */
 780
 781 int
 782 check_unaligned(struct pt_regs *regs)
 783 {
 784         unsigned long align_mask;
 785
 786         /* Get alignment mask */
 787
 788         align_mask = 0UL;
 789         switch (regs->iir & OPCODE1_MASK) {
 790
 791         case OPCODE_LDH_I:
 792         case OPCODE_LDH_S:
 793         case OPCODE_STH:
 794                 align_mask = 1UL;
 795                 break;
 796
 797         case OPCODE_LDW_I:
 798         case OPCODE_LDWA_I:
 799         case OPCODE_LDW_S:
 800         case OPCODE_LDWA_S:
 801         case OPCODE_STW:
 802         case OPCODE_STWA:
 803                 align_mask = 3UL;
 804                 break;
 805
 806         default:
 807                 switch (regs->iir & OPCODE4_MASK) {
 808                 case OPCODE_LDH_L:
 809                 case OPCODE_STH_L:
 810                         align_mask = 1UL;
 811                         break;
 812                 case OPCODE_LDW_L:
 813                 case OPCODE_LDWM:
 814                 case OPCODE_STW_L:
 815                 case OPCODE_STWM:
 816                         align_mask = 3UL;
 817                         break;
 818                 }
 819                 break;
 820         }
 821
 822         return (int)(regs->ior & align_mask);
 823 }
 824