2 * MPC8379E MDS Device Tree Source
4 * Copyright 2007 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
15 model = "fsl,mpc8379emds";
16 compatible = "fsl,mpc8379emds","fsl,mpc837xmds";
35 d-cache-line-size = <32>;
36 i-cache-line-size = <32>;
37 d-cache-size = <32768>;
38 i-cache-size = <32768>;
39 timebase-frequency = <0>;
41 clock-frequency = <0>;
46 device_type = "memory";
47 reg = <0x00000000 0x20000000>; // 512MB at 0
53 compatible = "fsl,mpc8379-elbc", "fsl,elbc", "simple-bus";
54 reg = <0xe0005000 0x1000>;
55 interrupts = <77 0x8>;
56 interrupt-parent = <&ipic>;
58 // booting from NOR flash
59 ranges = <0 0x0 0xfe000000 0x02000000
60 1 0x0 0xf8000000 0x00008000
61 3 0x0 0xe0600000 0x00008000>;
66 compatible = "cfi-flash";
67 reg = <0 0x0 0x2000000>;
77 reg = <0x100000 0x800000>;
81 reg = <0x1d00000 0x200000>;
85 reg = <0x1f00000 0x100000>;
91 compatible = "fsl,mpc837xmds-bcsr";
97 compatible = "fsl,mpc8379-fcm-nand",
102 reg = <0x0 0x100000>;
107 reg = <0x100000 0x300000>;
111 reg = <0x400000 0x1c00000>;
117 #address-cells = <1>;
120 compatible = "simple-bus";
121 ranges = <0x0 0xe0000000 0x00100000>;
122 reg = <0xe0000000 0x00000200>;
126 compatible = "mpc83xx_wdt";
131 #address-cells = <1>;
133 compatible = "simple-bus";
134 sleep = <&pmc 0x0c000000>;
138 #address-cells = <1>;
141 compatible = "fsl-i2c";
142 reg = <0x3000 0x100>;
143 interrupts = <14 0x8>;
144 interrupt-parent = <&ipic>;
148 compatible = "dallas,ds1374";
150 interrupts = <19 0x8>;
151 interrupt-parent = <&ipic>;
156 compatible = "fsl,mpc8379-esdhc";
157 reg = <0x2e000 0x1000>;
158 interrupts = <42 0x8>;
159 interrupt-parent = <&ipic>;
160 /* Filled in by U-Boot */
161 clock-frequency = <0>;
166 #address-cells = <1>;
169 compatible = "fsl-i2c";
170 reg = <0x3100 0x100>;
171 interrupts = <15 0x8>;
172 interrupt-parent = <&ipic>;
178 compatible = "fsl,spi";
179 reg = <0x7000 0x1000>;
180 interrupts = <16 0x8>;
181 interrupt-parent = <&ipic>;
186 #address-cells = <1>;
188 compatible = "fsl,mpc8379-dma", "fsl,elo-dma";
190 ranges = <0 0x8100 0x1a8>;
191 interrupt-parent = <&ipic>;
195 compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
198 interrupt-parent = <&ipic>;
202 compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
205 interrupt-parent = <&ipic>;
209 compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
212 interrupt-parent = <&ipic>;
216 compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
219 interrupt-parent = <&ipic>;
225 compatible = "fsl-usb2-dr";
226 reg = <0x23000 0x1000>;
227 #address-cells = <1>;
229 interrupt-parent = <&ipic>;
230 interrupts = <38 0x8>;
233 sleep = <&pmc 0x00c00000>;
237 #address-cells = <1>;
239 compatible = "fsl,gianfar-mdio";
240 reg = <0x24520 0x20>;
241 phy2: ethernet-phy@2 {
242 interrupt-parent = <&ipic>;
243 interrupts = <17 0x8>;
245 device_type = "ethernet-phy";
247 phy3: ethernet-phy@3 {
248 interrupt-parent = <&ipic>;
249 interrupts = <18 0x8>;
251 device_type = "ethernet-phy";
255 device_type = "tbi-phy";
260 #address-cells = <1>;
262 compatible = "fsl,gianfar-tbi";
263 reg = <0x25520 0x20>;
267 device_type = "tbi-phy";
271 enet0: ethernet@24000 {
273 device_type = "network";
275 compatible = "gianfar";
276 reg = <0x24000 0x1000>;
277 local-mac-address = [ 00 00 00 00 00 00 ];
278 interrupts = <32 0x8 33 0x8 34 0x8>;
279 phy-connection-type = "mii";
280 interrupt-parent = <&ipic>;
281 tbi-handle = <&tbi0>;
282 phy-handle = <&phy2>;
283 sleep = <&pmc 0xc0000000>;
287 enet1: ethernet@25000 {
289 device_type = "network";
291 compatible = "gianfar";
292 reg = <0x25000 0x1000>;
293 local-mac-address = [ 00 00 00 00 00 00 ];
294 interrupts = <35 0x8 36 0x8 37 0x8>;
295 phy-connection-type = "mii";
296 interrupt-parent = <&ipic>;
297 tbi-handle = <&tbi1>;
298 phy-handle = <&phy3>;
299 sleep = <&pmc 0x30000000>;
303 serial0: serial@4500 {
305 device_type = "serial";
306 compatible = "ns16550";
307 reg = <0x4500 0x100>;
308 clock-frequency = <0>;
309 interrupts = <9 0x8>;
310 interrupt-parent = <&ipic>;
313 serial1: serial@4600 {
315 device_type = "serial";
316 compatible = "ns16550";
317 reg = <0x4600 0x100>;
318 clock-frequency = <0>;
319 interrupts = <10 0x8>;
320 interrupt-parent = <&ipic>;
324 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
325 "fsl,sec2.1", "fsl,sec2.0";
326 reg = <0x30000 0x10000>;
327 interrupts = <11 0x8>;
328 interrupt-parent = <&ipic>;
329 fsl,num-channels = <4>;
330 fsl,channel-fifo-len = <24>;
331 fsl,exec-units-mask = <0x9fe>;
332 fsl,descriptor-types-mask = <0x3ab0ebf>;
333 sleep = <&pmc 0x03000000>;
337 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
338 reg = <0x18000 0x1000>;
339 interrupts = <44 0x8>;
340 interrupt-parent = <&ipic>;
341 sleep = <&pmc 0x000000c0>;
345 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
346 reg = <0x19000 0x1000>;
347 interrupts = <45 0x8>;
348 interrupt-parent = <&ipic>;
349 sleep = <&pmc 0x00000030>;
353 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
354 reg = <0x1a000 0x1000>;
355 interrupts = <46 0x8>;
356 interrupt-parent = <&ipic>;
357 sleep = <&pmc 0x0000000c>;
361 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
362 reg = <0x1b000 0x1000>;
363 interrupts = <47 0x8>;
364 interrupt-parent = <&ipic>;
365 sleep = <&pmc 0x00000003>;
369 * interrupts cell = <intr #, sense>
370 * sense values match linux IORESOURCE_IRQ_* defines:
371 * sense == 8: Level, low assertion
372 * sense == 2: Edge, high-to-low change
375 compatible = "fsl,ipic";
376 interrupt-controller;
377 #address-cells = <0>;
378 #interrupt-cells = <2>;
383 compatible = "fsl,mpc8379-pmc", "fsl,mpc8349-pmc";
384 reg = <0xb00 0x100 0xa00 0x100>;
385 interrupts = <80 0x8>;
386 interrupt-parent = <&ipic>;
392 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
396 0x8800 0x0 0x0 0x1 &ipic 20 0x8
397 0x8800 0x0 0x0 0x2 &ipic 21 0x8
398 0x8800 0x0 0x0 0x3 &ipic 22 0x8
399 0x8800 0x0 0x0 0x4 &ipic 23 0x8
402 0x9000 0x0 0x0 0x1 &ipic 22 0x8
403 0x9000 0x0 0x0 0x2 &ipic 23 0x8
404 0x9000 0x0 0x0 0x3 &ipic 20 0x8
405 0x9000 0x0 0x0 0x4 &ipic 21 0x8
408 0x9800 0x0 0x0 0x1 &ipic 23 0x8
409 0x9800 0x0 0x0 0x2 &ipic 20 0x8
410 0x9800 0x0 0x0 0x3 &ipic 21 0x8
411 0x9800 0x0 0x0 0x4 &ipic 22 0x8
414 0xa800 0x0 0x0 0x1 &ipic 20 0x8
415 0xa800 0x0 0x0 0x2 &ipic 21 0x8
416 0xa800 0x0 0x0 0x3 &ipic 22 0x8
417 0xa800 0x0 0x0 0x4 &ipic 23 0x8
420 0xb000 0x0 0x0 0x1 &ipic 23 0x8
421 0xb000 0x0 0x0 0x2 &ipic 20 0x8
422 0xb000 0x0 0x0 0x3 &ipic 21 0x8
423 0xb000 0x0 0x0 0x4 &ipic 22 0x8
426 0xb800 0x0 0x0 0x1 &ipic 22 0x8
427 0xb800 0x0 0x0 0x2 &ipic 23 0x8
428 0xb800 0x0 0x0 0x3 &ipic 20 0x8
429 0xb800 0x0 0x0 0x4 &ipic 21 0x8
432 0xc000 0x0 0x0 0x1 &ipic 21 0x8
433 0xc000 0x0 0x0 0x2 &ipic 22 0x8
434 0xc000 0x0 0x0 0x3 &ipic 23 0x8
435 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
436 interrupt-parent = <&ipic>;
437 interrupts = <66 0x8>;
438 bus-range = <0x0 0x0>;
439 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
440 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
441 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
442 sleep = <&pmc 0x00010000>;
443 clock-frequency = <0>;
444 #interrupt-cells = <1>;
446 #address-cells = <3>;
447 reg = <0xe0008500 0x100 /* internal registers */
448 0xe0008300 0x8>; /* config space access registers */
449 compatible = "fsl,mpc8349-pci";