arch/powerpc/boot/dts/mpc8544ds.dts

   1 /*
   2  * MPC8544 DS Device Tree Source
   3  *
   4  * Copyright 2007 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 / {
  13         model = "MPC8544DS";
  14         compatible = "MPC8544DS", "MPC85xxDS";
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17
  18         cpus {
  19                 #cpus = <1>;
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 PowerPC,8544@0 {
  24                         device_type = "cpu";
  25                         reg = <0>;
  26                         d-cache-line-size = <20>;       // 32 bytes
  27                         i-cache-line-size = <20>;       // 32 bytes
  28                         d-cache-size = <8000>;          // L1, 32K
  29                         i-cache-size = <8000>;          // L1, 32K
  30                         timebase-frequency = <0>;
  31                         bus-frequency = <0>;
  32                         clock-frequency = <0>;
  33                         32-bit;
  34                 };
  35         };
  36
  37         memory {
  38                 device_type = "memory";
  39                 reg = <00000000 00000000>;      // Filled by U-Boot
  40         };
  41
  42         soc8544@e0000000 {
  43                 #address-cells = <1>;
  44                 #size-cells = <1>;
  45                 #interrupt-cells = <2>;
  46                 device_type = "soc";
  47                 ranges = <0 e0000000 00100000>;
  48                 reg = <e0000000 00100000>;      // CCSRBAR 1M
  49                 bus-frequency = <0>;            // Filled out by uboot.
  50
  51                 memory-controller@2000 {
  52                         compatible = "fsl,8544-memory-controller";
  53                         reg = <2000 1000>;
  54                         interrupt-parent = <&mpic>;
  55                         interrupts = <12 2>;
  56                 };
  57
  58                 l2-cache-controller@20000 {
  59                         compatible = "fsl,8544-l2-cache-controller";
  60                         reg = <20000 1000>;
  61                         cache-line-size = <20>; // 32 bytes
  62                         cache-size = <40000>;   // L2, 256K
  63                         interrupt-parent = <&mpic>;
  64                         interrupts = <10 2>;
  65                 };
  66
  67                 i2c@3000 {
  68                         device_type = "i2c";
  69                         compatible = "fsl-i2c";
  70                         reg = <3000 100>;
  71                         interrupts = <2b 2>;
  72                         interrupt-parent = <&mpic>;
  73                         dfsrr;
  74                 };
  75
  76                 mdio@24520 {
  77                         #address-cells = <1>;
  78                         #size-cells = <0>;
  79                         device_type = "mdio";
  80                         compatible = "gianfar";
  81                         reg = <24520 20>;
  82                         phy0: ethernet-phy@0 {
  83                                 interrupt-parent = <&mpic>;
  84                                 interrupts = <a 1>;
  85                                 reg = <0>;
  86                                 device_type = "ethernet-phy";
  87                         };
  88                         phy1: ethernet-phy@1 {
  89                                 interrupt-parent = <&mpic>;
  90                                 interrupts = <a 1>;
  91                                 reg = <1>;
  92                                 device_type = "ethernet-phy";
  93                         };
  94                 };
  95
  96                 ethernet@24000 {
  97                         #address-cells = <1>;
  98                         #size-cells = <0>;
  99                         device_type = "network";
 100                         model = "TSEC";
 101                         compatible = "gianfar";
 102                         reg = <24000 1000>;
 103                         local-mac-address = [ 00 00 00 00 00 00 ];
 104                         interrupts = <1d 2 1e 2 22 2>;
 105                         interrupt-parent = <&mpic>;
 106                         phy-handle = <&phy0>;
 107                 };
 108
 109                 ethernet@26000 {
 110                         #address-cells = <1>;
 111                         #size-cells = <0>;
 112                         device_type = "network";
 113                         model = "TSEC";
 114                         compatible = "gianfar";
 115                         reg = <26000 1000>;
 116                         local-mac-address = [ 00 00 00 00 00 00 ];
 117                         interrupts = <1f 2 20 2 21 2>;
 118                         interrupt-parent = <&mpic>;
 119                         phy-handle = <&phy1>;
 120                 };
 121
 122                 serial@4500 {
 123                         device_type = "serial";
 124                         compatible = "ns16550";
 125                         reg = <4500 100>;
 126                         clock-frequency = <0>;
 127                         interrupts = <2a 2>;
 128                         interrupt-parent = <&mpic>;
 129                 };
 130
 131                 serial@4600 {
 132                         device_type = "serial";
 133                         compatible = "ns16550";
 134                         reg = <4600 100>;
 135                         clock-frequency = <0>;
 136                         interrupts = <2a 2>;
 137                         interrupt-parent = <&mpic>;
 138                 };
 139
 140                 pci@8000 {
 141                         compatible = "fsl,mpc8540-pci";
 142                         device_type = "pci";
 143                         interrupt-map-mask = <f800 0 0 7>;
 144                         interrupt-map = <
 145
 146                                 /* IDSEL 0x11 J17 Slot 1 */
 147                                 8800 0 0 1 &mpic 2 1
 148                                 8800 0 0 2 &mpic 3 1
 149                                 8800 0 0 3 &mpic 4 1
 150                                 8800 0 0 4 &mpic 1 1
 151
 152                                 /* IDSEL 0x12 J16 Slot 2 */
 153
 154                                 9000 0 0 1 &mpic 3 1
 155                                 9000 0 0 2 &mpic 4 1
 156                                 9000 0 0 3 &mpic 2 1
 157                                 9000 0 0 4 &mpic 1 1>;
 158
 159                         interrupt-parent = <&mpic>;
 160                         interrupts = <18 2>;
 161                         bus-range = <0 ff>;
 162                         ranges = <02000000 0 80000000 80000000 0 10000000
 163                                   01000000 0 00000000 e2000000 0 00800000>;
 164                         clock-frequency = <3f940aa>;
 165                         #interrupt-cells = <1>;
 166                         #size-cells = <2>;
 167                         #address-cells = <3>;
 168                         reg = <8000 1000>;
 169                 };
 170
 171                 pcie@9000 {
 172                         compatible = "fsl,mpc8548-pcie";
 173                         device_type = "pci";
 174                         #interrupt-cells = <1>;
 175                         #size-cells = <2>;
 176                         #address-cells = <3>;
 177                         reg = <9000 1000>;
 178                         bus-range = <0 ff>;
 179                         ranges = <02000000 0 90000000 90000000 0 10000000
 180                                   01000000 0 00000000 e3000000 0 00800000>;
 181                         clock-frequency = <1fca055>;
 182                         interrupt-parent = <&mpic>;
 183                         interrupts = <1a 2>;
 184                         interrupt-map-mask = <f800 0 0 7>;
 185                         interrupt-map = <
 186                                 /* IDSEL 0x0 */
 187                                 0000 0 0 1 &mpic 4 1
 188                                 0000 0 0 2 &mpic 5 1
 189                                 0000 0 0 3 &mpic 6 1
 190                                 0000 0 0 4 &mpic 7 1
 191                                 >;
 192                 };
 193
 194                 pcie@a000 {
 195                         compatible = "fsl,mpc8548-pcie";
 196                         device_type = "pci";
 197                         #interrupt-cells = <1>;
 198                         #size-cells = <2>;
 199                         #address-cells = <3>;
 200                         reg = <a000 1000>;
 201                         bus-range = <0 ff>;
 202                         ranges = <02000000 0 a0000000 a0000000 0 10000000
 203                                   01000000 0 00000000 e2800000 0 00800000>;
 204                         clock-frequency = <1fca055>;
 205                         interrupt-parent = <&mpic>;
 206                         interrupts = <19 2>;
 207                         interrupt-map-mask = <f800 0 0 7>;
 208                         interrupt-map = <
 209                                 /* IDSEL 0x0 */
 210                                 0000 0 0 1 &mpic 0 1
 211                                 0000 0 0 2 &mpic 1 1
 212                                 0000 0 0 3 &mpic 2 1
 213                                 0000 0 0 4 &mpic 3 1
 214                                 >;
 215                 };
 216
 217                 pcie@b000 {
 218                         compatible = "fsl,mpc8548-pcie";
 219                         device_type = "pci";
 220                         #interrupt-cells = <1>;
 221                         #size-cells = <2>;
 222                         #address-cells = <3>;
 223                         reg = <b000 1000>;
 224                         bus-range = <0 ff>;
 225                         ranges = <02000000 0 b0000000 b0000000 0 10000000
 226                                   01000000 0 00000000 e3800000 0 00800000>;
 227                         clock-frequency = <1fca055>;
 228                         interrupt-parent = <&mpic>;
 229                         interrupts = <1b 2>;
 230                         interrupt-map-mask = <f800 0 0 7>;
 231                         interrupt-map = <
 232
 233                                 // IDSEL 0x1a
 234                                 d000 0 0 1 &i8259 6 2
 235                                 d000 0 0 2 &i8259 3 2
 236                                 d000 0 0 3 &i8259 4 2
 237                                 d000 0 0 4 &i8259 5 2
 238
 239                                 // IDSEL 0x1b
 240                                 d800 0 0 1 &i8259 5 2
 241                                 d800 0 0 2 &i8259 0 0
 242                                 d800 0 0 3 &i8259 0 0
 243                                 d800 0 0 4 &i8259 0 0
 244
 245                                 // IDSEL 0x1c  USB
 246                                 e000 0 0 1 &i8259 9 2
 247                                 e000 0 0 2 &i8259 a 2
 248                                 e000 0 0 3 &i8259 c 2
 249                                 e000 0 0 4 &i8259 7 2
 250
 251                                 // IDSEL 0x1d  Audio
 252                                 e800 0 0 1 &i8259 9 2
 253                                 e800 0 0 2 &i8259 a 2
 254                                 e800 0 0 3 &i8259 b 2
 255                                 e800 0 0 4 &i8259 0 0
 256
 257                                 // IDSEL 0x1e Legacy
 258                                 f000 0 0 1 &i8259 c 2
 259                                 f000 0 0 2 &i8259 0 0
 260                                 f000 0 0 3 &i8259 0 0
 261                                 f000 0 0 4 &i8259 0 0
 262
 263                                 // IDSEL 0x1f IDE/SATA
 264                                 f800 0 0 1 &i8259 6 2
 265                                 f800 0 0 2 &i8259 0 0
 266                                 f800 0 0 3 &i8259 0 0
 267                                 f800 0 0 4 &i8259 0 0
 268                         >;
 269                         uli1575@0 {
 270                                 reg = <0 0 0 0 0>;
 271                                 #size-cells = <2>;
 272                                 #address-cells = <3>;
 273                                 ranges = <02000000 0 b0000000
 274                                           02000000 0 b0000000
 275                                           0 10000000
 276                                           01000000 0 00000000
 277                                           01000000 0 00000000
 278                                           0 00080000>;
 279
 280                                 pci_bridge@0 {
 281                                         reg = <0 0 0 0 0>;
 282                                         #size-cells = <2>;
 283                                         #address-cells = <3>;
 284                                         ranges = <02000000 0 b0000000
 285                                                   02000000 0 b0000000
 286                                                   0 20000000
 287                                                   01000000 0 00000000
 288                                                   01000000 0 00000000
 289                                                   0 00100000>;
 290
 291                                         isa@1e {
 292                                                 device_type = "isa";
 293                                                 #interrupt-cells = <2>;
 294                                                 #size-cells = <1>;
 295                                                 #address-cells = <2>;
 296                                                 reg = <f000 0 0 0 0>;
 297                                                 ranges = <1 0 01000000 0 0
 298                                                           00001000>;
 299                                                 interrupt-parent = <&i8259>;
 300
 301                                                 i8259: interrupt-controller@20 {
 302                                                         reg = <1 20 2
 303                                                                1 a0 2
 304                                                                1 4d0 2>;
 305                                                         clock-frequency = <0>;
 306                                                         interrupt-controller;
 307                                                         device_type = "interrupt-controller";
 308                                                         #address-cells = <0>;
 309                                                         #interrupt-cells = <2>;
 310                                                         built-in;
 311                                                         compatible = "chrp,iic";
 312                                                         interrupts = <9 2>;
 313                                                         interrupt-parent =
 314                                                                 <&mpic>;
 315                                                 };
 316
 317                                                 i8042@60 {
 318                                                         #size-cells = <0>;
 319                                                         #address-cells = <1>;
 320                                                         reg = <1 60 1 1 64 1>;
 321                                                         interrupts = <1 3 c 3>;
 322                                                         interrupt-parent =
 323                                                                 <&i8259>;
 324
 325                                                         keyboard@0 {
 326                                                                 reg = <0>;
 327                                                                 compatible = "pnpPNP,303";
 328                                                         };
 329
 330                                                         mouse@1 {
 331                                                                 reg = <1>;
 332                                                                 compatible = "pnpPNP,f03";
 333                                                         };
 334                                                 };
 335
 336                                                 rtc@70 {
 337                                                         compatible =
 338                                                                 "pnpPNP,b00";
 339                                                         reg = <1 70 2>;
 340                                                 };
 341
 342                                                 gpio@400 {
 343                                                         reg = <1 400 80>;
 344                                                 };
 345                                         };
 346                                 };
 347                         };
 348
 349                 };
 350
 351                 mpic: pic@40000 {
 352                         clock-frequency = <0>;
 353                         interrupt-controller;
 354                         #address-cells = <0>;
 355                         #interrupt-cells = <2>;
 356                         reg = <40000 40000>;
 357                         built-in;
 358                         compatible = "chrp,open-pic";
 359                         device_type = "open-pic";
 360                         big-endian;
 361                 };
 362         };
 363 };