arch/powerpc/boot/dts/mpc8610_hpcd.dts

   1 /*
   2  * MPC8610 HPCD Device Tree Source
   3  *
   4  * Copyright 2007 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under the terms of the GNU General Public License Version 2 as published
   8  * by the Free Software Foundation.
   9  */
  10
  11
  12 / {
  13         model = "MPC8610HPCD";
  14         compatible = "fsl,MPC8610HPCD";
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17
  18         aliases {
  19                 serial0 = &serial0;
  20                 serial1 = &serial1;
  21                 pci0 = &pci0;
  22                 pci1 = &pci1;
  23         };
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 PowerPC,8610@0 {
  30                         device_type = "cpu";
  31                         reg = <0>;
  32                         d-cache-line-size = <d# 32>;    // bytes
  33                         i-cache-line-size = <d# 32>;    // bytes
  34                         d-cache-size = <8000>;          // L1, 32K
  35                         i-cache-size = <8000>;          // L1, 32K
  36                         timebase-frequency = <0>;       // 33 MHz, from uboot
  37                         bus-frequency = <0>;            // From uboot
  38                         clock-frequency = <0>;          // From uboot
  39                 };
  40         };
  41
  42         memory {
  43                 device_type = "memory";
  44                 reg = <00000000 20000000>;      // 512M at 0x0
  45         };
  46
  47         soc@e0000000 {
  48                 #address-cells = <1>;
  49                 #size-cells = <1>;
  50                 #interrupt-cells = <2>;
  51                 device_type = "soc";
  52                 ranges = <0 e0000000 00100000>;
  53                 reg = <e0000000 1000>;
  54                 bus-frequency = <0>;
  55
  56                 i2c@3000 {
  57                         #address-cells = <1>;
  58                         #size-cells = <0>;
  59                         cell-index = <0>;
  60                         compatible = "fsl-i2c";
  61                         reg = <3000 100>;
  62                         interrupts = <2b 2>;
  63                         interrupt-parent = <&mpic>;
  64                         dfsrr;
  65                 };
  66
  67                 i2c@3100 {
  68                         #address-cells = <1>;
  69                         #size-cells = <0>;
  70                         cell-index = <1>;
  71                         compatible = "fsl-i2c";
  72                         reg = <3100 100>;
  73                         interrupts = <2b 2>;
  74                         interrupt-parent = <&mpic>;
  75                         dfsrr;
  76                 };
  77
  78                 serial0: serial@4500 {
  79                         cell-index = <0>;
  80                         device_type = "serial";
  81                         compatible = "ns16550";
  82                         reg = <4500 100>;
  83                         clock-frequency = <0>;
  84                         interrupts = <2a 2>;
  85                         interrupt-parent = <&mpic>;
  86                 };
  87
  88                 serial1: serial@4600 {
  89                         cell-index = <1>;
  90                         device_type = "serial";
  91                         compatible = "ns16550";
  92                         reg = <4600 100>;
  93                         clock-frequency = <0>;
  94                         interrupts = <1c 2>;
  95                         interrupt-parent = <&mpic>;
  96                 };
  97
  98                 mpic: interrupt-controller@40000 {
  99                         clock-frequency = <0>;
 100                         interrupt-controller;
 101                         #address-cells = <0>;
 102                         #interrupt-cells = <2>;
 103                         reg = <40000 40000>;
 104                         compatible = "chrp,open-pic";
 105                         device_type = "open-pic";
 106                         big-endian;
 107                 };
 108
 109                 global-utilities@e0000 {
 110                         compatible = "fsl,mpc8610-guts";
 111                         reg = <e0000 1000>;
 112                         fsl,has-rstcr;
 113                 };
 114         };
 115
 116         pci0: pci@e0008000 {
 117                 cell-index = <0>;
 118                 compatible = "fsl,mpc8610-pci";
 119                 device_type = "pci";
 120                 #interrupt-cells = <1>;
 121                 #size-cells = <2>;
 122                 #address-cells = <3>;
 123                 reg = <e0008000 1000>;
 124                 bus-range = <0 0>;
 125                 ranges = <02000000 0 80000000 80000000 0 10000000
 126                           01000000 0 00000000 e1000000 0 00100000>;
 127                 clock-frequency = <1fca055>;
 128                 interrupt-parent = <&mpic>;
 129                 interrupts = <18 2>;
 130                 interrupt-map-mask = <f800 0 0 7>;
 131                 interrupt-map = <
 132                         /* IDSEL 0x11 */
 133                         8800 0 0 1 &mpic 4 1
 134                         8800 0 0 2 &mpic 5 1
 135                         8800 0 0 3 &mpic 6 1
 136                         8800 0 0 4 &mpic 7 1
 137
 138                         /* IDSEL 0x12 */
 139                         9000 0 0 1 &mpic 5 1
 140                         9000 0 0 2 &mpic 6 1
 141                         9000 0 0 3 &mpic 7 1
 142                         9000 0 0 4 &mpic 4 1
 143                         >;
 144         };
 145
 146         pci1: pcie@e000a000 {
 147                 cell-index = <1>;
 148                 compatible = "fsl,mpc8641-pcie";
 149                 device_type = "pci";
 150                 #interrupt-cells = <1>;
 151                 #size-cells = <2>;
 152                 #address-cells = <3>;
 153                 reg = <e000a000 1000>;
 154                 bus-range = <1 3>;
 155                 ranges = <02000000 0 a0000000 a0000000 0 10000000
 156                           01000000 0 00000000 e3000000 0 00100000>;
 157                 clock-frequency = <1fca055>;
 158                 interrupt-parent = <&mpic>;
 159                 interrupts = <1a 2>;
 160                 interrupt-map-mask = <f800 0 0 7>;
 161
 162                 interrupt-map = <
 163                         /* IDSEL 0x1b */
 164                         d800 0 0 1 &mpic 2 1
 165
 166                         /* IDSEL 0x1c*/
 167                         e000 0 0 1 &mpic 1 1
 168                         e000 0 0 2 &mpic 1 1
 169                         e000 0 0 3 &mpic 1 1
 170                         e000 0 0 4 &mpic 1 1
 171
 172                         /* IDSEL 0x1f */
 173                         f800 0 0 1 &mpic 3 0
 174                         f800 0 0 2 &mpic 0 1
 175                 >;
 176
 177                 pcie@0 {
 178                         reg = <0 0 0 0 0>;
 179                         #size-cells = <2>;
 180                         #address-cells = <3>;
 181                         device_type = "pci";
 182                         ranges = <02000000 0 a0000000
 183                                   02000000 0 a0000000
 184                                   0 10000000
 185                                   01000000 0 00000000
 186                                   01000000 0 00000000
 187                                   0 00100000>;
 188                         uli1575@0 {
 189                                 reg = <0 0 0 0 0>;
 190                                 #size-cells = <2>;
 191                                 #address-cells = <3>;
 192                                 ranges = <02000000 0 a0000000
 193                                           02000000 0 a0000000
 194                                           0 10000000
 195                                           01000000 0 00000000
 196                                           01000000 0 00000000
 197                                           0 00100000>;
 198                         };
 199                 };
 200         };
 201 };