2 * P1020 RDB Device Tree Source
4 * Copyright 2009 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
15 compatible = "fsl,P1020RDB";
36 next-level-cache = <&L2>;
42 next-level-cache = <&L2>;
47 device_type = "memory";
53 compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
54 reg = <0 0xffe05000 0 0x1000>;
56 interrupt-parent = <&mpic>;
58 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
59 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
60 0x1 0x0 0x0 0xffa00000 0x00040000
61 0x2 0x0 0x0 0xffb00000 0x00020000>;
66 compatible = "cfi-flash";
67 reg = <0x0 0x0 0x1000000>;
72 /* This location must not be altered */
73 /* 256KB for Vitesse 7385 Switch firmware */
74 reg = <0x0 0x00040000>;
75 label = "NOR (RO) Vitesse-7385 Firmware";
80 /* 256KB for DTB Image */
81 reg = <0x00040000 0x00040000>;
82 label = "NOR (RO) DTB Image";
87 /* 3.5 MB for Linux Kernel Image */
88 reg = <0x00080000 0x00380000>;
89 label = "NOR (RO) Linux Kernel Image";
94 /* 11MB for JFFS2 based Root file System */
95 reg = <0x00400000 0x00b00000>;
96 label = "NOR (RW) JFFS2 Root File System";
100 /* This location must not be altered */
101 /* 512KB for u-boot Bootloader Image */
102 /* 512KB for u-boot Environment Variables */
103 reg = <0x00f00000 0x00100000>;
104 label = "NOR (RO) U-Boot Image";
110 #address-cells = <1>;
112 compatible = "fsl,p1020-fcm-nand",
114 reg = <0x1 0x0 0x40000>;
117 /* This location must not be altered */
118 /* 1MB for u-boot Bootloader Image */
119 reg = <0x0 0x00100000>;
120 label = "NAND (RO) U-Boot Image";
125 /* 1MB for DTB Image */
126 reg = <0x00100000 0x00100000>;
127 label = "NAND (RO) DTB Image";
132 /* 4MB for Linux Kernel Image */
133 reg = <0x00200000 0x00400000>;
134 label = "NAND (RO) Linux Kernel Image";
139 /* 4MB for Compressed Root file System Image */
140 reg = <0x00600000 0x00400000>;
141 label = "NAND (RO) Compressed RFS Image";
146 /* 7MB for JFFS2 based Root file System */
147 reg = <0x00a00000 0x00700000>;
148 label = "NAND (RW) JFFS2 Root File System";
152 /* 15MB for JFFS2 based Root file System */
153 reg = <0x01100000 0x00f00000>;
154 label = "NAND (RW) Writable User area";
159 #address-cells = <1>;
161 compatible = "vitesse-7385";
162 reg = <0x2 0x0 0x20000>;
168 #address-cells = <1>;
171 compatible = "fsl,p1020-immr", "simple-bus";
172 ranges = <0x0 0x0 0xffe00000 0x100000>;
173 bus-frequency = <0>; // Filled out by uboot.
176 compatible = "fsl,ecm-law";
182 compatible = "fsl,p1020-ecm", "fsl,ecm";
183 reg = <0x1000 0x1000>;
185 interrupt-parent = <&mpic>;
188 memory-controller@2000 {
189 compatible = "fsl,p1020-memory-controller";
190 reg = <0x2000 0x1000>;
191 interrupt-parent = <&mpic>;
196 #address-cells = <1>;
199 compatible = "fsl-i2c";
200 reg = <0x3000 0x100>;
202 interrupt-parent = <&mpic>;
205 compatible = "dallas,ds1339";
211 #address-cells = <1>;
214 compatible = "fsl-i2c";
215 reg = <0x3100 0x100>;
217 interrupt-parent = <&mpic>;
221 serial0: serial@4500 {
223 device_type = "serial";
224 compatible = "ns16550";
225 reg = <0x4500 0x100>;
226 clock-frequency = <0>;
228 interrupt-parent = <&mpic>;
231 serial1: serial@4600 {
233 device_type = "serial";
234 compatible = "ns16550";
235 reg = <0x4600 0x100>;
236 clock-frequency = <0>;
238 interrupt-parent = <&mpic>;
243 #address-cells = <1>;
245 compatible = "fsl,espi";
246 reg = <0x7000 0x1000>;
247 interrupts = <59 0x2>;
248 interrupt-parent = <&mpic>;
252 #address-cells = <1>;
254 compatible = "fsl,espi-flash";
256 linux,modalias = "fsl_m25p80";
258 spi-max-frequency = <50000000>;
262 /* 512KB for u-boot Bootloader Image */
263 reg = <0x0 0x00080000>;
264 label = "SPI (RO) U-Boot Image";
269 /* 512KB for DTB Image */
270 reg = <0x00080000 0x00080000>;
271 label = "SPI (RO) DTB Image";
276 /* 4MB for Linux Kernel Image */
277 reg = <0x00100000 0x00400000>;
278 label = "SPI (RO) Linux Kernel Image";
283 /* 4MB for Compressed RFS Image */
284 reg = <0x00500000 0x00400000>;
285 label = "SPI (RO) Compressed RFS Image";
290 /* 7MB for JFFS2 based RFS */
291 reg = <0x00900000 0x00700000>;
292 label = "SPI (RW) JFFS2 RFS";
297 gpio: gpio-controller@f000 {
299 compatible = "fsl,mpc8572-gpio";
300 reg = <0xf000 0x100>;
301 interrupts = <47 0x2>;
302 interrupt-parent = <&mpic>;
306 L2: l2-cache-controller@20000 {
307 compatible = "fsl,p1020-l2-cache-controller";
308 reg = <0x20000 0x1000>;
309 cache-line-size = <32>; // 32 bytes
310 cache-size = <0x40000>; // L2,256K
311 interrupt-parent = <&mpic>;
316 #address-cells = <1>;
318 compatible = "fsl,eloplus-dma";
320 ranges = <0x0 0x21100 0x200>;
323 compatible = "fsl,eloplus-dma-channel";
326 interrupt-parent = <&mpic>;
330 compatible = "fsl,eloplus-dma-channel";
333 interrupt-parent = <&mpic>;
337 compatible = "fsl,eloplus-dma-channel";
340 interrupt-parent = <&mpic>;
344 compatible = "fsl,eloplus-dma-channel";
347 interrupt-parent = <&mpic>;
353 #address-cells = <1>;
355 compatible = "fsl,etsec2-mdio";
356 reg = <0x24000 0x1000 0xb0030 0x4>;
358 phy0: ethernet-phy@0 {
359 interrupt-parent = <&mpic>;
364 phy1: ethernet-phy@1 {
365 interrupt-parent = <&mpic>;
372 #address-cells = <1>;
374 compatible = "fsl,etsec2-tbi";
375 reg = <0x25000 0x1000 0xb1030 0x4>;
379 device_type = "tbi-phy";
383 enet0: ethernet@b0000 {
384 #address-cells = <1>;
386 device_type = "network";
388 compatible = "fsl,etsec2";
389 fsl,num_rx_queues = <0x8>;
390 fsl,num_tx_queues = <0x8>;
391 local-mac-address = [ 00 00 00 00 00 00 ];
392 interrupt-parent = <&mpic>;
393 fixed-link = <1 1 1000 0 0>;
394 phy-connection-type = "rgmii-id";
397 #address-cells = <1>;
399 reg = <0xb0000 0x1000>;
400 interrupts = <29 2 30 2 34 2>;
404 #address-cells = <1>;
406 reg = <0xb4000 0x1000>;
407 interrupts = <17 2 18 2 24 2>;
411 enet1: ethernet@b1000 {
412 #address-cells = <1>;
414 device_type = "network";
416 compatible = "fsl,etsec2";
417 fsl,num_rx_queues = <0x8>;
418 fsl,num_tx_queues = <0x8>;
419 local-mac-address = [ 00 00 00 00 00 00 ];
420 interrupt-parent = <&mpic>;
421 phy-handle = <&phy0>;
422 tbi-handle = <&tbi0>;
423 phy-connection-type = "sgmii";
426 #address-cells = <1>;
428 reg = <0xb1000 0x1000>;
429 interrupts = <35 2 36 2 40 2>;
433 #address-cells = <1>;
435 reg = <0xb5000 0x1000>;
436 interrupts = <51 2 52 2 67 2>;
440 enet2: ethernet@b2000 {
441 #address-cells = <1>;
443 device_type = "network";
445 compatible = "fsl,etsec2";
446 fsl,num_rx_queues = <0x8>;
447 fsl,num_tx_queues = <0x8>;
448 local-mac-address = [ 00 00 00 00 00 00 ];
449 interrupt-parent = <&mpic>;
450 phy-handle = <&phy1>;
451 phy-connection-type = "rgmii-id";
454 #address-cells = <1>;
456 reg = <0xb2000 0x1000>;
457 interrupts = <31 2 32 2 33 2>;
461 #address-cells = <1>;
463 reg = <0xb6000 0x1000>;
464 interrupts = <25 2 26 2 27 2>;
469 #address-cells = <1>;
471 compatible = "fsl-usb2-dr";
472 reg = <0x22000 0x1000>;
473 interrupt-parent = <&mpic>;
474 interrupts = <28 0x2>;
478 /* USB2 is shared with localbus, so it must be disabled
479 by default. We can't put 'status = "disabled";' here
480 since U-Boot doesn't clear the status property when
481 it enables USB2. OTOH, U-Boot does create a new node
482 when there isn't any. So, just comment it out.
484 #address-cells = <1>;
486 compatible = "fsl-usb2-dr";
487 reg = <0x23000 0x1000>;
488 interrupt-parent = <&mpic>;
489 interrupts = <46 0x2>;
495 compatible = "fsl,p1020-esdhc", "fsl,esdhc";
496 reg = <0x2e000 0x1000>;
497 interrupts = <72 0x2>;
498 interrupt-parent = <&mpic>;
499 /* Filled in by U-Boot */
500 clock-frequency = <0>;
504 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
505 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
506 reg = <0x30000 0x10000>;
507 interrupts = <45 2 58 2>;
508 interrupt-parent = <&mpic>;
509 fsl,num-channels = <4>;
510 fsl,channel-fifo-len = <24>;
511 fsl,exec-units-mask = <0xbfe>;
512 fsl,descriptor-types-mask = <0x3ab0ebf>;
516 interrupt-controller;
517 #address-cells = <0>;
518 #interrupt-cells = <2>;
519 reg = <0x40000 0x40000>;
520 compatible = "chrp,open-pic";
521 device_type = "open-pic";
525 compatible = "fsl,p1020-msi", "fsl,mpic-msi";
526 reg = <0x41600 0x80>;
527 msi-available-ranges = <0 0x100>;
537 interrupt-parent = <&mpic>;
540 global-utilities@e0000 { //global utilities block
541 compatible = "fsl,p1020-guts";
542 reg = <0xe0000 0x1000>;
547 pci0: pcie@ffe09000 {
548 compatible = "fsl,mpc8548-pcie";
550 #interrupt-cells = <1>;
552 #address-cells = <3>;
553 reg = <0 0xffe09000 0 0x1000>;
555 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
556 0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>;
557 clock-frequency = <33333333>;
558 interrupt-parent = <&mpic>;
561 reg = <0x0 0x0 0x0 0x0 0x0>;
563 #address-cells = <3>;
565 ranges = <0x2000000 0x0 0xa0000000
566 0x2000000 0x0 0xa0000000
575 pci1: pcie@ffe0a000 {
576 compatible = "fsl,mpc8548-pcie";
578 #interrupt-cells = <1>;
580 #address-cells = <3>;
581 reg = <0 0xffe0a000 0 0x1000>;
583 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
584 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
585 clock-frequency = <33333333>;
586 interrupt-parent = <&mpic>;
589 reg = <0x0 0x0 0x0 0x0 0x0>;
591 #address-cells = <3>;
593 ranges = <0x2000000 0x0 0xc0000000
594 0x2000000 0x0 0xc0000000