2 * Manroland uc101 board Device Tree Source
4 * Copyright (C) 2009 DENX Software Engineering GmbH
5 * Heiko Schocher <hs@denx.de>
6 * Copyright 2006-2007 Secret Lab Technologies Ltd.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
17 model = "manroland,uc101";
18 compatible = "manroland,uc101";
21 interrupt-parent = <&mpc5200_pic>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <0x4000>; // L1, 16K
33 i-cache-size = <0x4000>; // L1, 16K
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
41 device_type = "memory";
42 reg = <0x00000000 0x04000000>; // 64MB
48 compatible = "fsl,mpc5200b-immr";
49 ranges = <0 0xf0000000 0x0000c000>;
50 reg = <0xf0000000 0x00000100>;
51 bus-frequency = <0>; // from bootloader
52 system-frequency = <0>; // from bootloader
55 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
59 mpc5200_pic: interrupt-controller@500 {
60 // 5200 interrupts are encoded into two levels;
62 #interrupt-cells = <3>;
63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
67 gpt0: timer@600 { // General Purpose Timer in GPIO mode
68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
75 gpt1: timer@610 { // General Purpose Timer in GPIO mode
76 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
78 interrupts = <1 10 0>;
83 gpt2: timer@620 { // General Purpose Timer in GPIO mode
84 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
86 interrupts = <1 11 0>;
91 gpt3: timer@630 { // General Purpose Timer in GPIO mode
92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
94 interrupts = <1 12 0>;
99 gpt4: timer@640 { // General Purpose Timer in GPIO mode
100 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
102 interrupts = <1 13 0>;
107 gpt5: timer@650 { // General Purpose Timer in GPIO mode
108 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
110 interrupts = <1 14 0>;
115 gpt6: timer@660 { // General Purpose Timer in GPIO mode
116 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
118 interrupts = <1 15 0>;
123 gpt7: timer@670 { // General Purpose Timer in GPIO mode
124 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
126 interrupts = <1 16 0>;
131 gpio_simple: gpio@b00 {
132 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
134 interrupts = <1 7 0>;
139 gpio_wkup: gpio@c00 {
140 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
142 interrupts = <1 8 0 0 3 0>;
147 dma-controller@1200 {
148 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
150 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
151 3 4 0 3 5 0 3 6 0 3 7 0
152 3 8 0 3 9 0 3 10 0 3 11 0
153 3 12 0 3 13 0 3 14 0 3 15 0>;
157 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
158 reg = <0x1f00 0x100>;
161 serial@2000 { /* PSC1 in UART mode */
162 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
163 reg = <0x2000 0x100>;
164 interrupts = <2 1 0>;
167 serial@2200 { /* PSC2 in UART mode */
168 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
169 reg = <0x2200 0x100>;
170 interrupts = <2 2 0>;
173 serial@2c00 { /* PSC6 in UART mode */
174 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
175 reg = <0x2c00 0x100>;
176 interrupts = <2 4 0>;
180 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
181 reg = <0x3000 0x400>;
182 local-mac-address = [ 00 00 00 00 00 00 ];
183 interrupts = <2 5 0>;
184 phy-handle = <&phy0>;
188 #address-cells = <1>;
190 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
191 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
192 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
194 phy0: ethernet-phy@0 {
195 compatible = "intel,lxt971";
201 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
202 reg = <0x3a00 0x100>;
203 interrupts = <2 7 0>;
207 #address-cells = <1>;
209 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
211 interrupts = <2 16 0>;
212 fsl,preserve-clocking;
213 clock-frequency = <400000>;
216 compatible = "ad,adm9240";
220 compatible = "nxp,pcf8563";
226 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
227 reg = <0x8000 0x4000>;
232 compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
234 #address-cells = <2>;
237 ranges = <0 0 0xff800000 0x00800000
238 1 0 0x80000000 0x00800000
239 3 0 0x80000000 0x00800000>;
242 compatible = "cfi-flash";
243 reg = <0 0 0x00800000>;
247 #address-cells = <1>;
251 reg = <0x0 0x00100000>;
255 reg = <0x100000 0x00200000>;
259 reg = <0x00300000 0x00200000>;
263 reg = <0x00500000 0x00200000>;
267 reg = <0x00700000 0x00040000>;
271 reg = <0x00740000 0x00010000>;
275 reg = <0x00750000 0x00010000>;
279 reg = <0x00760000 0x000a0000>;