2 * Copyright 2007 David Gibson, IBM Corporation.
4 * Based on earlier code:
5 * Copyright (C) Paul Mackerras 1997.
7 * Matt Porter <mporter@kernel.crashing.org>
8 * Copyright 2002-2005 MontaVista Software Inc.
10 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
11 * Copyright (c) 2003, 2004 Zultys Technologies
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
31 extern char _dtb_start[];
32 extern char _dtb_end[];
34 static u8 *ebony_mac0, *ebony_mac1;
36 /* Calculate 440GP clocks */
37 void ibm440gp_fixup_clocks(unsigned int sysclk, unsigned int ser_clk)
39 u32 sys0 = mfdcr(DCRN_CPC0_SYS0);
40 u32 cr0 = mfdcr(DCRN_CPC0_CR0);
41 u32 cpu, plb, opb, ebc, tb, uart0, uart1, m;
42 u32 opdv = CPC0_SYS0_OPDV(sys0);
43 u32 epdv = CPC0_SYS0_EPDV(sys0);
45 if (sys0 & CPC0_SYS0_BYPASS) {
46 /* Bypass system PLL */
49 if (sys0 & CPC0_SYS0_EXTSL)
51 m = CPC0_SYS0_FWDVB(sys0) * opdv * epdv;
54 m = CPC0_SYS0_FBDV(sys0) * CPC0_SYS0_FWDVA(sys0);
55 cpu = sysclk * m / CPC0_SYS0_FWDVA(sys0);
56 plb = sysclk * m / CPC0_SYS0_FWDVB(sys0);
62 /* FIXME: Check if this is for all 440GP, or just Ebony */
63 if ((mfpvr() & 0xf0000fff) == 0x40000440)
64 /* Rev. B 440GP, use external system clock */
67 /* Rev. C 440GP, errata force us to use internal clock */
70 if (cr0 & CPC0_CR0_U0EC)
71 /* External UART clock */
74 /* Internal UART clock */
75 uart0 = plb / CPC0_CR0_UDIV(cr0);
77 if (cr0 & CPC0_CR0_U1EC)
78 /* External UART clock */
81 /* Internal UART clock */
82 uart1 = plb / CPC0_CR0_UDIV(cr0);
84 printf("PPC440GP: SysClk = %dMHz (%x)\n\r",
85 (sysclk + 500000) / 1000000, sysclk);
87 dt_fixup_cpu_clocks(cpu, tb, 0);
89 dt_fixup_clock("/plb", plb);
90 dt_fixup_clock("/plb/opb", opb);
91 dt_fixup_clock("/plb/opb/ebc", ebc);
92 dt_fixup_clock("/plb/opb/serial@40000200", uart0);
93 dt_fixup_clock("/plb/opb/serial@40000300", uart1);
96 #define EBONY_FPGA_PATH "/plb/opb/ebc/fpga"
97 #define EBONY_FPGA_FLASH_SEL 0x01
98 #define EBONY_SMALL_FLASH_PATH "/plb/opb/ebc/small-flash"
100 static void ebony_flashsel_fixup(void)
103 u32 reg[3] = {0x0, 0x0, 0x80000};
107 devp = finddevice(EBONY_FPGA_PATH);
109 fatal("Couldn't locate FPGA node %s\n\r", EBONY_FPGA_PATH);
111 if (getprop(devp, "virtual-reg", &fpga, sizeof(fpga)) != sizeof(fpga))
112 fatal("%s has missing or invalid virtual-reg property\n\r",
115 fpga_reg0 = in_8(fpga);
117 devp = finddevice(EBONY_SMALL_FLASH_PATH);
119 fatal("Couldn't locate small flash node %s\n\r",
120 EBONY_SMALL_FLASH_PATH);
122 if (getprop(devp, "reg", reg, sizeof(reg)) != sizeof(reg))
123 fatal("%s has reg property of unexpected size\n\r",
124 EBONY_SMALL_FLASH_PATH);
126 /* Invert address bit 14 (IBM-endian) if FLASH_SEL fpga bit is set */
127 if (fpga_reg0 & EBONY_FPGA_FLASH_SEL)
130 setprop(devp, "reg", reg, sizeof(reg));
133 static void ebony_fixups(void)
135 // FIXME: sysclk should be derived by reading the FPGA registers
136 unsigned long sysclk = 33000000;
138 ibm440gp_fixup_clocks(sysclk, 6 * 1843200);
139 ibm44x_fixup_memsize();
140 dt_fixup_mac_addresses(ebony_mac0, ebony_mac1);
141 ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
142 ebony_flashsel_fixup();
145 void ebony_init(void *mac0, void *mac1)
147 platform_ops.fixups = ebony_fixups;
148 platform_ops.exit = ibm44x_dbcr_reset;
151 ft_init(_dtb_start, _dtb_end - _dtb_start, 32);
152 serial_console_init();