2 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
3 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <fsl_esdhc.h>
33 #include <asm/cache.h>
36 #include <asm/fsl_ifc.h>
37 #include <asm/fsl_law.h>
38 #include <asm/fsl_lbc.h>
40 #include <asm/processor.h>
41 #include <asm/fsl_ddr_sdram.h>
43 DECLARE_GLOBAL_DATA_PTR;
46 * Default board reset function
53 void board_reset(void) __attribute__((weak, alias("__board_reset")));
62 char buf1[32], buf2[32];
63 #if (defined(CONFIG_DDR_CLK_FREQ) || \
64 defined(CONFIG_FSL_CORENET)) && !defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
65 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
66 #endif /* CONFIG_FSL_CORENET */
69 * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
70 * mode. Previous platform use ddr ratio to do the same. This
71 * information is only for display here.
73 #ifdef CONFIG_FSL_CORENET
74 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
75 u32 ddr_sync = 0; /* only async mode is supported */
77 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
78 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
79 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
80 #else /* CONFIG_FSL_CORENET */
81 #ifdef CONFIG_DDR_CLK_FREQ
82 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
83 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
86 #endif /* CONFIG_DDR_CLK_FREQ */
87 #endif /* CONFIG_FSL_CORENET */
89 unsigned int i, core, nr_cores = cpu_numcores();
90 u32 mask = cpu_mask();
96 if (cpu_numcores() > 1) {
98 puts("Unicore software on multiprocessor system!!\n"
99 "To enable mutlticore build define CONFIG_MP\n");
101 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
102 printf("CPU%d: ", pic->whoami);
110 if (IS_E_PROCESSOR(svr))
113 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
117 major = PVR_MAJ(pvr);
118 minor = PVR_MIN(pvr);
122 case PVR_VER_E500_V1:
123 case PVR_VER_E500_V2:
140 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
142 if (nr_cores > CONFIG_MAX_CPUS) {
143 panic("\nUnexpected number of cores: %d, max is %d\n",
144 nr_cores, CONFIG_MAX_CPUS);
147 get_sys_info(&sysinfo);
149 puts("Clock Configuration:");
150 for_each_cpu(i, core, nr_cores, mask) {
153 printf("CPU%d:%-4s MHz, ", core,
154 strmhz(buf1, sysinfo.freqProcessor[core]));
156 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
158 #ifdef CONFIG_FSL_CORENET
160 printf(" DDR:%-4s MHz (%s MT/s data rate) "
162 strmhz(buf1, sysinfo.freqDDRBus/2),
163 strmhz(buf2, sysinfo.freqDDRBus));
165 printf(" DDR:%-4s MHz (%s MT/s data rate) "
167 strmhz(buf1, sysinfo.freqDDRBus/2),
168 strmhz(buf2, sysinfo.freqDDRBus));
173 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
174 strmhz(buf1, sysinfo.freqDDRBus/2),
175 strmhz(buf2, sysinfo.freqDDRBus));
178 printf(" DDR:%-4s MHz (%s MT/s data rate) "
180 strmhz(buf1, sysinfo.freqDDRBus/2),
181 strmhz(buf2, sysinfo.freqDDRBus));
184 printf(" DDR:%-4s MHz (%s MT/s data rate) "
186 strmhz(buf1, sysinfo.freqDDRBus/2),
187 strmhz(buf2, sysinfo.freqDDRBus));
192 #if defined(CONFIG_FSL_LBC)
193 if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
194 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
196 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
197 sysinfo.freqLocalBus);
201 #if defined(CONFIG_FSL_IFC)
202 printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
206 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
210 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
213 #ifdef CONFIG_SYS_DPAA_FMAN
214 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
215 printf(" FMAN%d: %s MHz\n", i + 1,
216 strmhz(buf1, sysinfo.freqFMan[i]));
220 #ifdef CONFIG_SYS_DPAA_PME
221 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME));
224 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
230 /* ------------------------------------------------------------------------- */
232 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
234 /* Everything after the first generation of PQ3 parts has RSTCR */
235 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
236 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
237 unsigned long val, msr;
240 * Initiate hard reset in debug control register DBCR0
241 * Make sure MSR[DE] = 1. This only resets the core.
251 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
253 /* Attempt board-specific reset */
256 /* Next try asserting HRESET_REQ */
257 out_be32(&gur->rstcr, 0x2);
266 * Get timebase clock frequency
268 #ifndef CONFIG_SYS_FSL_TBCLK_DIV
269 #define CONFIG_SYS_FSL_TBCLK_DIV 8
271 unsigned long get_tbclk (void)
273 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
275 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
279 #if defined(CONFIG_WATCHDOG)
283 int re_enable = disable_interrupts();
284 reset_85xx_watchdog();
285 if (re_enable) enable_interrupts();
289 reset_85xx_watchdog(void)
292 * Clear TSR(WIS) bit by writing 1
294 mtspr(SPRN_TSR, TSR_WIS);
296 #endif /* CONFIG_WATCHDOG */
299 * Initializes on-chip MMC controllers.
300 * to override, implement board_mmc_init()
302 int cpu_mmc_init(bd_t *bis)
304 #ifdef CONFIG_FSL_ESDHC
305 return fsl_esdhc_mmc_init(bis);
312 * Print out the state of various machine registers.
313 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
314 * parameters for IFC and TLBs
316 void mpc85xx_reginfo(void)
320 #if defined(CONFIG_FSL_LBC)
323 #ifdef CONFIG_FSL_IFC
329 /* Common ddr init for non-corenet fsl 85xx platforms */
330 #ifndef CONFIG_FSL_CORENET
331 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_INIT_L2_ADDR)
332 phys_size_t initdram(int board_type)
334 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
335 return fsl_ddr_sdram_size();
337 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
340 #else /* CONFIG_SYS_RAMBOOT */
341 phys_size_t initdram(int board_type)
343 phys_size_t dram_size = 0;
345 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
347 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
352 * Work around to stabilize DDR DLL
354 out_be32(&gur->ddrdllcr, 0x81000000);
355 asm("sync;isync;msync");
357 while (in_be32(&gur->ddrdllcr) != 0x81000100) {
358 setbits_be32(&gur->devdisr, 0x00010000);
359 for (i = 0; i < x; i++)
361 clrbits_be32(&gur->devdisr, 0x00010000);
367 #if defined(CONFIG_SPD_EEPROM) || \
368 defined(CONFIG_DDR_SPD) || \
369 defined(CONFIG_SYS_DDR_RAW_TIMING)
370 dram_size = fsl_ddr_sdram();
372 dram_size = fixed_sdram();
374 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
375 dram_size *= 0x100000;
377 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
379 * Initialize and enable DDR ECC.
381 ddr_enable_ecc(dram_size);
384 #if defined(CONFIG_FSL_LBC)
385 /* Some boards also have sdram on the lbc */
392 #endif /* CONFIG_SYS_RAMBOOT */
395 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY
397 /* Board-specific functions defined in each board's ddr.c */
398 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
399 unsigned int ctrl_num);
400 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
403 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
405 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
407 static void dump_spd_ddr_reg(void)
412 ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS];
414 spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
416 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
417 fsl_ddr_get_spd(spd[i], i);
419 puts("SPD data of all dimms (zero vaule is omitted)...\n");
422 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
423 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
424 printf("Dimm%d ", k++);
427 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
429 printf("%3d (0x%02x) ", k, k);
430 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
431 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
432 p_8 = (u8 *) &spd[i][j];
434 printf("0x%02x ", p_8[k]);
446 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
449 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
451 #if defined(CONFIG_SYS_MPC85xx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
453 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
456 #if defined(CONFIG_SYS_MPC85xx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
458 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR3_ADDR;
461 #if defined(CONFIG_SYS_MPC85xx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
463 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR4_ADDR;
467 printf("%s unexpected controller number = %u\n",
472 printf("DDR registers dump for all controllers "
473 "(zero vaule is omitted)...\n");
474 puts("Offset (hex) ");
475 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
476 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
478 for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) {
480 printf("%6d (0x%04x)", k * 4, k * 4);
481 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
482 p_32 = (u32 *) ddr[i];
484 printf(" 0x%08x", p_32[k]);
497 /* invalid the TLBs for DDR and setup new ones to cover p_addr */
498 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
500 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
502 u32 tsize, valid, ptr;
505 clear_ddr_tlbs_phys(p_addr, size>>20);
507 /* Setup new tlb to cover the physical address */
508 setup_ddr_tlbs_phys(p_addr, size>>20);
511 ddr_esel = find_tlb_idx((void *)ptr, 1);
512 if (ddr_esel != -1) {
513 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
515 printf("TLB error in function %s\n", __func__);
523 * slide the testing window up to test another area
524 * for 32_bit system, the maximum testable memory is limited to
525 * CONFIG_MAX_MEM_MAPPED
527 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
529 phys_addr_t test_cap, p_addr;
530 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
532 #if !defined(CONFIG_PHYS_64BIT) || \
533 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
534 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
537 test_cap = gd->ram_size;
539 p_addr = (*vstart) + (*size) + (*phys_offset);
540 if (p_addr < test_cap - 1) {
541 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
542 if (reset_tlb(p_addr, p_size, phys_offset) == -1)
544 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
545 *size = (u32) p_size;
546 printf("Testing 0x%08llx - 0x%08llx\n",
547 (u64)(*vstart) + (*phys_offset),
548 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
555 /* initialization for testing area */
556 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
558 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
560 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
561 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */
564 #if !defined(CONFIG_PHYS_64BIT) || \
565 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
566 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
567 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
568 puts("Cannot test more than ");
569 print_size(CONFIG_MAX_MEM_MAPPED,
570 " without proper 36BIT support.\n");
573 printf("Testing 0x%08llx - 0x%08llx\n",
574 (u64)(*vstart) + (*phys_offset),
575 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
580 /* invalid TLBs for DDR and remap as normal after testing */
581 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
584 u32 tsize, valid, ptr;
588 /* disable the TLBs for this testing */
591 while (ptr < (*vstart) + (*size)) {
592 ddr_esel = find_tlb_idx((void *)ptr, 1);
593 if (ddr_esel != -1) {
594 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
595 disable_tlb(ddr_esel);
597 ptr += TSIZE_TO_BYTES(tsize);
601 setup_ddr_tlbs(gd->ram_size>>20);
607 void arch_memory_failure_handle(void)