2 * Copyright 2007-2011 Freescale Semiconductor, Inc.
4 * (C) Copyright 2003 Motorola Inc.
5 * Modified by Xianghua Xiao, X.Xiao@motorola.com
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/processor.h>
36 #include <asm/cache.h>
38 #include <asm/fsl_law.h>
39 #include <asm/fsl_serdes.h>
40 #include <asm/fsl_srio.h>
42 #include <linux/compiler.h>
44 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
49 #include "../../../../drivers/block/fsl_sata.h"
51 #define HWCONFIG_BUFFER_SIZE 128
53 DECLARE_GLOBAL_DATA_PTR;
56 extern qe_iop_conf_t qe_iop_conf_tab[];
57 extern void qe_config_iopin(u8 port, u8 pin, int dir,
58 int open_drain, int assign);
59 extern void qe_init(uint qe_base);
60 extern void qe_reset(void);
62 static void config_qe_ioports(void)
65 int dir, open_drain, assign;
68 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
69 port = qe_iop_conf_tab[i].port;
70 pin = qe_iop_conf_tab[i].pin;
71 dir = qe_iop_conf_tab[i].dir;
72 open_drain = qe_iop_conf_tab[i].open_drain;
73 assign = qe_iop_conf_tab[i].assign;
74 qe_config_iopin(port, pin, dir, open_drain, assign);
80 void config_8560_ioports (volatile ccsr_cpm_t * cpm)
84 for (portnum = 0; portnum < 4; portnum++) {
91 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
92 iop_conf_t *eiopc = iopc + 32;
97 * index 0 refers to pin 31,
98 * index 31 refers to pin 0
100 while (iopc < eiopc) {
120 volatile ioport_t *iop = ioport_addr (cpm, portnum);
124 * the (somewhat confused) paragraph at the
125 * bottom of page 35-5 warns that there might
126 * be "unknown behaviour" when programming
127 * PSORx and PDIRx, if PPARx = 1, so I
128 * decided this meant I had to disable the
129 * dedicated function first, and enable it
133 iop->psor = (iop->psor & tpmsk) | psor;
134 iop->podr = (iop->podr & tpmsk) | podr;
135 iop->pdat = (iop->pdat & tpmsk) | pdat;
136 iop->pdir = (iop->pdir & tpmsk) | pdir;
143 #ifdef CONFIG_SYS_FSL_CPC
144 static void enable_cpc(void)
149 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
151 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
152 u32 cpccfg0 = in_be32(&cpc->cpccfg0);
153 size += CPC_CFG0_SZ_K(cpccfg0);
154 #ifdef CONFIG_RAMBOOT_PBL
155 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
156 /* find and disable LAW of SRAM */
157 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
159 if (law.index == -1) {
160 printf("\nFatal error happened\n");
163 disable_law(law.index);
165 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
166 out_be32(&cpc->cpccsr0, 0);
167 out_be32(&cpc->cpcsrcr0, 0);
171 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
172 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
174 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
175 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
178 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
179 /* Read back to sync write */
180 in_be32(&cpc->cpccsr0);
184 printf("Corenet Platform Cache: %d KB enabled\n", size);
187 void invalidate_cpc(void)
190 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
192 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
193 /* skip CPC when it used as all SRAM */
194 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
196 /* Flash invalidate the CPC and clear all the locks */
197 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
198 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
204 #define invalidate_cpc()
205 #endif /* CONFIG_SYS_FSL_CPC */
208 * Breathe some life into the CPU...
210 * Set up the memory map
211 * initialize a bunch of registers
214 #ifdef CONFIG_FSL_CORENET
215 static void corenet_tb_init(void)
217 volatile ccsr_rcpm_t *rcpm =
218 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
219 volatile ccsr_pic_t *pic =
220 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
221 u32 whoami = in_be32(&pic->whoami);
223 /* Enable the timebase register for this core */
224 out_be32(&rcpm->ctbenrl, (1 << whoami));
228 void cpu_init_f (void)
230 extern void m8560_cpm_reset (void);
231 #ifdef CONFIG_SYS_DCSRBAR_PHYS
232 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
234 #if defined(CONFIG_SECURE_BOOT)
235 struct law_entry law;
237 #ifdef CONFIG_MPC8548
238 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
239 uint svr = get_svr();
242 * CPU2 errata workaround: A core hang possible while executing
243 * a msync instruction and a snoopable transaction from an I/O
244 * master tagged to make quick forward progress is present.
245 * Fixed in silicon rev 2.1.
247 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
248 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
254 #if defined(CONFIG_SECURE_BOOT)
255 /* Disable the LAW created for NOR flash by the PBI commands */
256 law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
258 disable_law(law.index);
262 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
265 init_early_memctl_regs();
267 #if defined(CONFIG_CPM2)
271 /* Config QE ioports */
274 #if defined(CONFIG_FSL_DMA)
277 #ifdef CONFIG_FSL_CORENET
280 init_used_tlb_cams();
282 /* Invalidate the CPC before DDR gets enabled */
285 #ifdef CONFIG_SYS_DCSRBAR_PHYS
286 /* set DCSRCR so that DCSR space is 1G */
287 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
288 in_be32(&gur->dcsrcr);
293 /* Implement a dummy function for those platforms w/o SERDES */
294 static void __fsl_serdes__init(void)
298 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
301 * Initialize L2 as cache.
303 * The newer 8548, etc, parts have twice as much cache, but
304 * use the same bit-encoding as the older 8555, etc, parts.
309 __maybe_unused u32 svr = get_svr();
310 #ifdef CONFIG_SYS_LBC_LCRR
311 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
314 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
315 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
317 * CPU22 and NMG_CPU_A011 share the same workaround.
318 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
319 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
320 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
321 * fixed in 2.0. NMG_CPU_A011 is activated by default and can
322 * be disabled by hwconfig with syntax:
324 * fsl_cpu_a011:disable
326 extern int enable_cpu_a011_workaround;
327 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
328 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
330 char buffer[HWCONFIG_BUFFER_SIZE];
334 n = getenv_f("hwconfig", buffer, sizeof(buffer));
338 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
340 enable_cpu_a011_workaround = 0;
342 if (n >= HWCONFIG_BUFFER_SIZE) {
343 printf("fsl_cpu_a011 was not found. hwconfig variable "
344 "may be too long\n");
346 enable_cpu_a011_workaround =
347 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
348 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
351 if (enable_cpu_a011_workaround) {
353 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
360 #if defined(CONFIG_L2_CACHE)
361 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
362 volatile uint cache_ctl;
366 ver = SVR_SOC_VER(svr);
369 cache_ctl = l2cache->l2ctl;
371 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
372 if (cache_ctl & MPC85xx_L2CTL_L2E) {
373 /* Clear L2 SRAM memory-mapped base address */
374 out_be32(&l2cache->l2srbar0, 0x0);
375 out_be32(&l2cache->l2srbar1, 0x0);
377 /* set MBECCDIS=0, SBECCDIS=0 */
378 clrbits_be32(&l2cache->l2errdis,
379 (MPC85xx_L2ERRDIS_MBECC |
380 MPC85xx_L2ERRDIS_SBECC));
382 /* set L2E=0, L2SRAM=0 */
383 clrbits_be32(&l2cache->l2ctl,
385 MPC85xx_L2CTL_L2SRAM_ENTIRE));
389 l2siz_field = (cache_ctl >> 28) & 0x3;
391 switch (l2siz_field) {
393 printf(" unknown size (0x%08x)\n", cache_ctl);
397 if (ver == SVR_8540 || ver == SVR_8560 ||
398 ver == SVR_8541 || ver == SVR_8555) {
400 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
401 cache_ctl = 0xc4000000;
404 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
408 if (ver == SVR_8540 || ver == SVR_8560 ||
409 ver == SVR_8541 || ver == SVR_8555) {
411 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
412 cache_ctl = 0xc8000000;
415 /* set L2E=1, L2I=1, & L2SRAM=0 */
416 cache_ctl = 0xc0000000;
421 /* set L2E=1, L2I=1, & L2SRAM=0 */
422 cache_ctl = 0xc0000000;
426 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
427 puts("already enabled");
428 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
429 u32 l2srbar = l2cache->l2srbar0;
430 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
431 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
432 l2srbar = CONFIG_SYS_INIT_L2_ADDR;
433 l2cache->l2srbar0 = l2srbar;
434 printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
436 #endif /* CONFIG_SYS_INIT_L2_ADDR */
440 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
444 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
445 if (SVR_SOC_VER(svr) == SVR_P2040) {
450 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
452 /* invalidate the L2 cache */
453 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
454 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
457 #ifdef CONFIG_SYS_CACHE_STASHING
458 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
459 mtspr(SPRN_L2CSR1, (32 + 1));
462 /* enable the cache */
463 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
465 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
466 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
468 printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
478 /* needs to be in ram since code uses global static vars */
481 #ifdef CONFIG_SYS_SRIO
483 #ifdef CONFIG_SRIOBOOT_MASTER
485 #ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF
486 srio_boot_master_release_slave();
491 #if defined(CONFIG_MP)
495 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC136
498 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
499 setbits_be32(p, 1 << (31 - 14));
503 #ifdef CONFIG_SYS_LBC_LCRR
505 * Modify the CLKDIV field of LCRR register to improve the writing
506 * speed for NOR flash.
508 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
509 __raw_readl(&lbc->lcrr);
511 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
516 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
518 ccsr_usb_phy_t *usb_phy1 =
519 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
520 out_be32(&usb_phy1->usb_enable_override,
521 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
524 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
526 ccsr_usb_phy_t *usb_phy2 =
527 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
528 out_be32(&usb_phy2->usb_enable_override,
529 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
533 #ifdef CONFIG_FMAN_ENET
537 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
539 * For P1022/1013 Rev1.0 silicon, after power on SATA host
540 * controller is configured in legacy mode instead of the
541 * expected enterprise mode. Software needs to clear bit[28]
542 * of HControl register to change to enterprise mode from
543 * legacy mode. We assume that the controller is offline.
545 if (IS_SVR_REV(svr, 1, 0) &&
546 ((SVR_SOC_VER(svr) == SVR_P1022) ||
547 (SVR_SOC_VER(svr) == SVR_P1013))) {
550 /* first SATA controller */
551 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
552 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
554 /* second SATA controller */
555 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
556 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
564 extern void setup_ivors(void);
566 void arch_preboot_os(void)
571 * We are changing interrupt offsets and are about to boot the OS so
572 * we need to make sure we disable all async interrupts. EE is already
573 * disabled by the time we get called.
576 msr &= ~(MSR_ME|MSR_CE);
582 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
583 int sata_initialize(void)
585 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
586 return __sata_initialize();
592 void cpu_secondary_init_r(void)
595 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
596 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
598 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
600 /* load QE firmware from NAND flash to DDR first */
601 ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND,
602 &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR);
604 if (ret && ret == -EUCLEAN) {
605 printf ("NAND read for QE firmware at offset %x failed %d\n",
606 CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret);