2 * Copyright 2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/fsl_serdes.h>
9 #include <asm/immap_85xx.h>
11 #include <asm/processor.h>
12 #include <asm/fsl_law.h>
13 #include <asm/errno.h>
14 #include <asm/fsl_errata.h>
15 #include "fsl_corenet2_serdes.h"
17 #ifdef CONFIG_SYS_FSL_SRDS_1
18 static u64 serdes1_prtcl_map;
20 #ifdef CONFIG_SYS_FSL_SRDS_2
21 static u64 serdes2_prtcl_map;
23 #ifdef CONFIG_SYS_FSL_SRDS_3
24 static u64 serdes3_prtcl_map;
26 #ifdef CONFIG_SYS_FSL_SRDS_4
27 static u64 serdes4_prtcl_map;
31 static const char *serdes_prtcl_str[] = {
41 [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1",
42 [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2",
43 [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3",
44 [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4",
45 [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5",
46 [SGMII_FM1_DTSEC6] = "SGMII_FM1_DTSEC6",
47 [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1",
48 [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
49 [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
50 [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
51 [XAUI_FM1] = "XAUI_FM1",
52 [XAUI_FM2] = "XAUI_FM2",
62 [XAUI_FM1_MAC9] = "XAUI_FM1_MAC9",
63 [XAUI_FM1_MAC10] = "XAUI_FM1_MAC10",
64 [XAUI_FM2_MAC9] = "XAUI_FM2_MAC9",
65 [XAUI_FM2_MAC10] = "XAUI_FM2_MAC10",
66 [HIGIG_FM1_MAC9] = "HiGig_FM1_MAC9",
67 [HIGIG_FM1_MAC10] = "HiGig_FM1_MAC10",
68 [HIGIG_FM2_MAC9] = "HiGig_FM2_MAC9",
69 [HIGIG_FM2_MAC10] = "HiGig_FM2_MAC10",
70 [QSGMII_FM1_A] = "QSGMII_FM1_A",
71 [QSGMII_FM1_B] = "QSGMII_FM1_B",
72 [QSGMII_FM2_A] = "QSGMII_FM2_A",
73 [QSGMII_FM2_B] = "QSGMII_FM2_B",
74 [XFI_FM1_MAC9] = "XFI_FM1_MAC9",
75 [XFI_FM1_MAC10] = "XFI_FM1_MAC10",
76 [XFI_FM2_MAC9] = "XFI_FM2_MAC9",
77 [XFI_FM2_MAC10] = "XFI_FM2_MAC10",
78 [INTERLAKEN] = "INTERLAKEN",
79 [QSGMII_SW1_A] = "QSGMII_SW1_A",
80 [QSGMII_SW1_B] = "QSGMII_SW1_B",
84 int is_serdes_configured(enum srds_prtcl device)
88 #ifdef CONFIG_SYS_FSL_SRDS_1
89 ret |= (1ULL << device) & serdes1_prtcl_map;
91 #ifdef CONFIG_SYS_FSL_SRDS_2
92 ret |= (1ULL << device) & serdes2_prtcl_map;
94 #ifdef CONFIG_SYS_FSL_SRDS_3
95 ret |= (1ULL << device) & serdes3_prtcl_map;
97 #ifdef CONFIG_SYS_FSL_SRDS_4
98 ret |= (1ULL << device) & serdes4_prtcl_map;
104 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
106 const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
107 u32 cfg = in_be32(&gur->rcwsr[4]);
111 #ifdef CONFIG_SYS_FSL_SRDS_1
113 cfg &= FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
114 cfg >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
117 #ifdef CONFIG_SYS_FSL_SRDS_2
119 cfg &= FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
120 cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
123 #ifdef CONFIG_SYS_FSL_SRDS_3
125 cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
126 cfg >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
129 #ifdef CONFIG_SYS_FSL_SRDS_4
131 cfg &= FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
132 cfg >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
136 printf("invalid SerDes%d\n", sd);
139 /* Is serdes enabled at all? */
140 if (unlikely(cfg == 0))
143 for (i = 0; i < SRDS_MAX_LANES; i++) {
144 if (serdes_get_prtcl(sd, cfg, i) == device)
164 #define FUSE_VAL_MASK 0x00000003
165 #define FUSE_VAL_SHIFT 30
166 #define CR0_DCBIAS_SHIFT 5
167 #define CR1_FCAP_SHIFT 15
168 #define CR1_BCAP_SHIFT 29
169 #define FCAP_MASK 0x001F8000
170 #define BCAP_MASK 0x20000000
171 #define BCAP_OVD_MASK 0x10000000
172 #define BYP_CAL_MASK 0x02000000
174 u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
176 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
177 u64 serdes_prtcl_map = 0;
180 #ifdef CONFIG_SYS_FSL_ERRATUM_A007186
181 struct ccsr_sfp_regs __iomem *sfp_regs =
182 (struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR);
183 u32 pll_num, pll_status, bc, dc, fc, pll_cr_upd, pll_cr0, pll_cr1;
184 u32 bc_status, fc_status, dc_status, pll_sr2;
185 serdes_corenet_t __iomem *srds_regs = (void *)sd_addr;
189 cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
192 * Freescale Scratch Pad Fuse Register n (SFP_FSPFR0)
193 * The workaround requires factory pre-set SerDes calibration values to be
194 * read from a fuse block(Freescale Scratch Pad Fuse Register SFP_FSPFR0)
195 * These values have been shown to work across the
196 * entire temperature range for all SerDes. These values are then written into
197 * the SerDes registers to calibrate the SerDes PLL.
199 * This workaround for the protocols and rates that only have the Ring VCO.
201 #ifdef CONFIG_SYS_FSL_ERRATUM_A007186
202 sfp_spfr0 = in_be32(&sfp_regs->fsl_spfr0);
203 debug("A007186: sfp_spfr0= %x\n", sfp_spfr0);
205 sel = (sfp_spfr0 >> FUSE_VAL_SHIFT) & FUSE_VAL_MASK;
207 if (has_erratum_a007186() && (sel == 0x01 || sel == 0x02)) {
208 for (pll_num = 0; pll_num < SRDS_MAX_BANK; pll_num++) {
209 pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
210 debug("A007186: pll_num=%x pllcr0=%x\n",
211 pll_num, pll_status);
213 /* Read factory pre-set SerDes calibration values
214 * from fuse block(SFP scratch register-sfp_spfr0)
216 switch (pll_status & SRDS_PLLCR0_FRATE_SEL_MASK) {
217 case SRDS_PLLCR0_FRATE_SEL_3_0:
218 case SRDS_PLLCR0_FRATE_SEL_3_072:
219 debug("A007186: 3.0/3.072 protocol rate\n");
220 bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
221 dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
222 fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
224 case SRDS_PLLCR0_FRATE_SEL_3_125:
225 debug("A007186: 3.125 protocol rate\n");
226 bc = (sfp_spfr0 >> BC2_SHIFT) & BC_MASK;
227 dc = (sfp_spfr0 >> DC2_SHIFT) & DC_MASK;
228 fc = (sfp_spfr0 >> FC2_SHIFT) & FC_MASK;
230 case SRDS_PLLCR0_FRATE_SEL_3_75:
231 debug("A007186: 3.75 protocol rate\n");
232 bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
233 dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
234 fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
241 /* Write SRDSxPLLnCR1[11:16] = FC
242 * Write SRDSxPLLnCR1[2] = BC
244 pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
245 pll_cr_upd = (((bc << CR1_BCAP_SHIFT) & BCAP_MASK) |
246 ((fc << CR1_FCAP_SHIFT) & FCAP_MASK));
247 out_be32(&srds_regs->bank[pll_num].pllcr1,
248 (pll_cr_upd | pll_cr1));
249 debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
250 pll_num, (pll_cr_upd | pll_cr1));
251 /* Write SRDSxPLLnCR0[24:26] = DC
253 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
254 out_be32(&srds_regs->bank[pll_num].pllcr0,
255 pll_cr0 | (dc << CR0_DCBIAS_SHIFT));
256 debug("A007186: pll_num=%x, Updated PLLCR0=%x\n",
257 pll_num, (pll_cr0 | (dc << CR0_DCBIAS_SHIFT)));
258 /* Write SRDSxPLLnCR1[3] = 1
259 * Write SRDSxPLLnCR1[6] = 1
261 pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
262 pll_cr_upd = (BCAP_OVD_MASK | BYP_CAL_MASK);
263 out_be32(&srds_regs->bank[pll_num].pllcr1,
264 (pll_cr_upd | pll_cr1));
265 debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
266 pll_num, (pll_cr_upd | pll_cr1));
269 /* Read the status Registers */
270 /* Verify SRDSxPLLnSR2[8] = BC */
271 pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2);
272 debug("A007186: pll_num=%x pllsr2=%x\n",
274 bc_status = (pll_sr2 >> 23) & BC_MASK;
276 debug("BC mismatch\n");
277 fc_status = (pll_sr2 >> 16) & FC_MASK;
279 debug("FC mismatch\n");
280 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
281 out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 |
283 pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2);
284 dc_status = (pll_sr2 >> 17) & DC_MASK;
286 debug("DC mismatch\n");
287 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
288 out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 &
292 /* Wait 750us to verify the PLL is locked
293 * by checking SRDSxPLLnCR0[8] = 1.
296 pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
297 debug("A007186: pll_num=%x pllcr0=%x\n",
298 pll_num, pll_status);
300 if ((pll_status & SRDS_PLLCR0_PLL_LCK) == 0)
301 printf("A007186 Serdes PLL not locked\n");
303 debug("A007186 Serdes PLL locked\n");
308 cfg >>= sd_prctl_shift;
309 printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
310 if (!is_serdes_prtcl_valid(sd, cfg))
311 printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
313 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
314 enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
315 serdes_prtcl_map |= (1ULL << lane_prtcl);
318 return serdes_prtcl_map;
321 void fsl_serdes_init(void)
324 #ifdef CONFIG_SYS_FSL_SRDS_1
325 serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
326 CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
327 FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
328 FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT);
330 #ifdef CONFIG_SYS_FSL_SRDS_2
331 serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
332 CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
333 FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
334 FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT);
336 #ifdef CONFIG_SYS_FSL_SRDS_3
337 serdes3_prtcl_map = serdes_init(FSL_SRDS_3,
338 CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
339 FSL_CORENET2_RCWSR4_SRDS3_PRTCL,
340 FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT);
342 #ifdef CONFIG_SYS_FSL_SRDS_4
343 serdes4_prtcl_map = serdes_init(FSL_SRDS_4,
344 CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
345 FSL_CORENET2_RCWSR4_SRDS4_PRTCL,
346 FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT);
351 const char *serdes_clock_to_string(u32 clock)
354 case SRDS_PLLCR0_RFCK_SEL_100:
356 case SRDS_PLLCR0_RFCK_SEL_125:
358 case SRDS_PLLCR0_RFCK_SEL_156_25:
360 case SRDS_PLLCR0_RFCK_SEL_161_13:
361 return "161.1328123";
363 #if defined(CONFIG_T4240QDS)