2 * Copyright 2008-2011 Freescale Semiconductor, Inc.
3 * Kumar Gala <kumar.gala@freescale.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm-offsets.h>
29 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
31 #include <ppc_asm.tmpl>
34 #include <asm/cache.h>
37 /* To boot secondary cpus, we need a place for them to start up.
38 * Normally, they start at 0xfffffffc, but that's usually the
39 * firmware, and we don't want to have to run the firmware again.
40 * Instead, the primary cpu will set the BPTR to point here to
41 * this page. We then set up the core, and head to
42 * start_secondary. Note that this means that the code below
43 * must never exceed 1023 instructions (the branch at the end
44 * would then be the 1024th).
46 .globl __secondary_start_page
48 __secondary_start_page:
49 /* First do some preliminary setup */
50 lis r3, HID0_EMCP@h /* enable machine check */
52 ori r3,r3,HID0_TBEN@l /* enable Timebase */
54 #ifdef CONFIG_PHYS_64BIT
55 ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */
60 li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
63 cmpwi r0,0x50@l /* if we are rev 5.0 or greater set MBDD */
65 /* Set MBDD bit also */
66 ori r3, r3, HID1_MBDD@l
71 #ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
77 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
80 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
84 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
85 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
90 /* Not a supported revision affected by erratum */
93 1: /* Erratum says set bits 55:60 to 001001 */
104 /* Enable branch prediction */
105 lis r3,BUCSR_ENABLE@h
106 ori r3,r3,BUCSR_ENABLE@l
114 /* Enable/invalidate the I-Cache */
115 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
116 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
123 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
124 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
129 andi. r1,r3,L1CSR1_ICE@l
132 /* Enable/invalidate the D-Cache */
133 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
134 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
141 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
142 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
147 andi. r1,r3,L1CSR0_DCE@l
150 #define toreset(x) (x - __secondary_start_page + 0xfffff000)
152 /* get our PIR to figure out our table entry */
153 lis r3,toreset(__spin_table)@h
154 ori r3,r3,toreset(__spin_table)@l
156 /* r10 has the base address for the entry */
159 rlwinm r4,r0,27,27,31
166 #if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
167 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
173 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
174 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
176 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
177 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
178 * also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
181 rlwinm r6,r3,24,~0x800 /* clear E bit */
184 ori r5,r5,SVR_P4080@l
193 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
194 lis r3,toreset(enable_cpu_a011_workaround)@ha
195 lwz r3,toreset(enable_cpu_a011_workaround)@l(r3)
200 oris r3,r3,(L1CSR2_DCWS)@h
205 #ifdef CONFIG_BACKSIDE_L2_CACHE
206 /* skip L2 setup on P2040/P2040E as they have no L2 */
208 rlwinm r6,r3,24,~0x800 /* clear E bit of SVR */
211 ori r3,r3,SVR_P2040@l
215 /* Enable/invalidate the L2 cache */
217 lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
218 ori r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
225 #ifdef CONFIG_SYS_CACHE_STASHING
226 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
231 lis r3,CONFIG_SYS_INIT_L2CSR0@h
232 ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l
237 andis. r1,r3,L2CSR0_L2E@h
242 #define EPAPR_MAGIC (0x45504150)
243 #define ENTRY_ADDR_UPPER 0
244 #define ENTRY_ADDR_LOWER 4
245 #define ENTRY_R3_UPPER 8
246 #define ENTRY_R3_LOWER 12
247 #define ENTRY_RESV 16
249 #define ENTRY_R6_UPPER 24
250 #define ENTRY_R6_LOWER 28
251 #define ENTRY_SIZE 32
253 /* setup the entry */
256 stw r0,ENTRY_PIR(r10)
257 stw r3,ENTRY_ADDR_UPPER(r10)
258 stw r8,ENTRY_ADDR_LOWER(r10)
259 stw r3,ENTRY_R3_UPPER(r10)
260 stw r4,ENTRY_R3_LOWER(r10)
261 stw r3,ENTRY_R6_UPPER(r10)
262 stw r3,ENTRY_R6_LOWER(r10)
264 /* load r13 with the address of the 'bootpg' in SDRAM */
265 lis r13,toreset(__bootpg_addr)@h
266 ori r13,r13,toreset(__bootpg_addr)@l
269 /* setup mapping for AS = 1, and jump there */
270 lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
272 lis r11,(MAS1_VALID|MAS1_IPROT)@h
273 ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
275 oris r11,r13,(MAS2_I|MAS2_G)@h
276 ori r11,r13,(MAS2_I|MAS2_G)@l
278 oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
279 ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
286 * OR in 0xfff to create a mask of the bootpg SDRAM address. We use
287 * this mask to fixup the cpu spin table and the address that we want
288 * to jump to, eg change them from 0xfffffxxx to 0x7ffffxxx if the
289 * bootpg is at 0x7ffff000 in SDRAM.
297 ori r12,r13,MSR_IS|MSR_DS@l
303 /* spin waiting for addr */
305 lwz r4,ENTRY_ADDR_LOWER(r10)
310 /* setup IVORs to match fixed offsets */
311 #include "fixed_ivor.S"
313 /* get the upper bits of the addr */
314 lwz r11,ENTRY_ADDR_UPPER(r10)
316 /* setup branch addr */
319 /* mark the entry as released */
321 stw r8,ENTRY_ADDR_LOWER(r10)
323 /* mask by ~64M to setup our tlb we will jump to */
326 /* setup r3, r4, r5, r6, r7, r8, r9 */
327 lwz r3,ENTRY_R3_LOWER(r10)
330 lwz r6,ENTRY_R6_LOWER(r10)
331 lis r7,(64*1024*1024)@h
335 /* load up the pir */
336 lwz r0,ENTRY_PIR(r10)
339 stw r0,ENTRY_PIR(r10)
343 * Coming here, we know the cpu has one TLB mapping in TLB1[0]
344 * which maps 0xfffff000-0xffffffff one-to-one. We set up a
345 * second mapping that maps addr 1:1 for 64M, and then we jump to
348 lis r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h
350 lis r10,(MAS1_VALID|MAS1_IPROT)@h
351 ori r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
353 /* WIMGE = 0b00000 for now */
355 ori r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR)
357 #ifdef CONFIG_ENABLE_36BIT_PHYS
362 /* Now we have another mapping for this page, so we jump to that
369 * Allocate some space for the SDRAM address of the bootpg.
370 * This variable has to be in the boot page so that it can
371 * be accessed by secondary cores when they come out of reset.
377 .align L1_CACHE_SHIFT
380 .space CONFIG_MAX_CPUS*ENTRY_SIZE
383 * This variable is set by cpu_init_r() after parsing hwconfig
384 * to enable workaround for erratum NMG_CPU_A011.
386 .align L1_CACHE_SHIFT
387 .global enable_cpu_a011_workaround
388 enable_cpu_a011_workaround:
391 /* Fill in the empty space. The actual reset vector is
392 * the last word of the page */
393 __secondary_start_code_end:
394 .space 4092 - (__secondary_start_code_end - __secondary_start_page)
395 __secondary_reset_vector:
396 b __secondary_start_page