arch/powerpc/cpu/mpc85xx/speed.c

   1 /*
   2  * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2003 Motorola Inc.
   5  * Xianghua Xiao, (X.Xiao@motorola.com)
   6  *
   7  * (C) Copyright 2000
   8  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 #include <common.h>
  30 #include <ppc_asm.tmpl>
  31 #include <linux/compiler.h>
  32 #include <asm/processor.h>
  33 #include <asm/io.h>
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 /* --------------------------------------------------------------- */
  38
  39 void get_sys_info (sys_info_t * sysInfo)
  40 {
  41         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  42 #ifdef CONFIG_FSL_IFC
  43         struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
  44         u32 ccr;
  45 #endif
  46 #ifdef CONFIG_FSL_CORENET
  47         volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
  48         unsigned int cpu;
  49
  50         const u8 core_cplx_PLL[16] = {
  51                 [ 0] = 0,       /* CC1 PPL / 1 */
  52                 [ 1] = 0,       /* CC1 PPL / 2 */
  53                 [ 2] = 0,       /* CC1 PPL / 4 */
  54                 [ 4] = 1,       /* CC2 PPL / 1 */
  55                 [ 5] = 1,       /* CC2 PPL / 2 */
  56                 [ 6] = 1,       /* CC2 PPL / 4 */
  57                 [ 8] = 2,       /* CC3 PPL / 1 */
  58                 [ 9] = 2,       /* CC3 PPL / 2 */
  59                 [10] = 2,       /* CC3 PPL / 4 */
  60                 [12] = 3,       /* CC4 PPL / 1 */
  61                 [13] = 3,       /* CC4 PPL / 2 */
  62                 [14] = 3,       /* CC4 PPL / 4 */
  63         };
  64
  65         const u8 core_cplx_PLL_div[16] = {
  66                 [ 0] = 1,       /* CC1 PPL / 1 */
  67                 [ 1] = 2,       /* CC1 PPL / 2 */
  68                 [ 2] = 4,       /* CC1 PPL / 4 */
  69                 [ 4] = 1,       /* CC2 PPL / 1 */
  70                 [ 5] = 2,       /* CC2 PPL / 2 */
  71                 [ 6] = 4,       /* CC2 PPL / 4 */
  72                 [ 8] = 1,       /* CC3 PPL / 1 */
  73                 [ 9] = 2,       /* CC3 PPL / 2 */
  74                 [10] = 4,       /* CC3 PPL / 4 */
  75                 [12] = 1,       /* CC4 PPL / 1 */
  76                 [13] = 2,       /* CC4 PPL / 2 */
  77                 [14] = 4,       /* CC4 PPL / 4 */
  78         };
  79         uint i, freqCC_PLL[6], rcw_tmp;
  80         uint ratio[6];
  81         unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
  82         uint mem_pll_rat;
  83
  84         sysInfo->freqSystemBus = sysclk;
  85 #ifdef CONFIG_DDR_CLK_FREQ
  86         sysInfo->freqDDRBus = CONFIG_DDR_CLK_FREQ;
  87 #else
  88         sysInfo->freqDDRBus = sysclk;
  89 #endif
  90
  91         sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
  92         mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
  93                         FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
  94                         & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
  95         if (mem_pll_rat > 2)
  96                 sysInfo->freqDDRBus *= mem_pll_rat;
  97         else
  98                 sysInfo->freqDDRBus = sysInfo->freqSystemBus * mem_pll_rat;
  99
 100         ratio[0] = (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
 101         ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
 102         ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
 103         ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
 104         ratio[4] = (in_be32(&clk->pllc5gsr) >> 1) & 0x3f;
 105         ratio[5] = (in_be32(&clk->pllc6gsr) >> 1) & 0x3f;
 106         for (i = 0; i < 6; i++) {
 107                 if (ratio[i] > 4)
 108                         freqCC_PLL[i] = sysclk * ratio[i];
 109                 else
 110                         freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i];
 111         }
 112 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 113         /*
 114          * Each cluster has up to 4 cores, sharing the same PLL selection.
 115          * The cluster assignment is fixed per SoC. There is no way identify the
 116          * assignment so far, presuming the "first configuration" which is to
 117          * fill the lower cluster group first before moving up to next group.
 118          * PLL1, PLL2, PLL3 are cluster group A, feeding core 0~3 on cluster 1
 119          * and core 4~7 on cluster 2
 120          * PLL4, PLL5, PLL6 are cluster group B, feeding core 8~11 on cluster 3
 121          * and core 12~15 on cluster 4 if existing
 122          */
 123         for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
 124                 u32 c_pll_sel = (in_be32(&clk->clkc0csr + (cpu / 4) * 8) >> 27)
 125                                 & 0xf;
 126                 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
 127                 if (cplx_pll > 3)
 128                         printf("Unsupported architecture configuration"
 129                                 " in function %s\n", __func__);
 130                 cplx_pll += (cpu / 8) * 3;
 131
 132                 sysInfo->freqProcessor[cpu] =
 133                          freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
 134         }
 135 #define PME_CLK_SEL     0xe0000000
 136 #define PME_CLK_SHIFT   29
 137 #define FM1_CLK_SEL     0x1c000000
 138 #define FM1_CLK_SHIFT   26
 139         rcw_tmp = in_be32(&gur->rcwsr[7]);
 140
 141 #ifdef CONFIG_SYS_DPAA_PME
 142         switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
 143         case 1:
 144                 sysInfo->freqPME = freqCC_PLL[0];
 145                 break;
 146         case 2:
 147                 sysInfo->freqPME = freqCC_PLL[0] / 2;
 148                 break;
 149         case 3:
 150                 sysInfo->freqPME = freqCC_PLL[0] / 3;
 151                 break;
 152         case 4:
 153                 sysInfo->freqPME = freqCC_PLL[0] / 4;
 154                 break;
 155         case 6:
 156                 sysInfo->freqPME = freqCC_PLL[1] / 2;
 157                 break;
 158         case 7:
 159                 sysInfo->freqPME = freqCC_PLL[1] / 3;
 160                 break;
 161         default:
 162                 printf("Error: Unknown PME clock select!\n");
 163         case 0:
 164                 sysInfo->freqPME = sysInfo->freqSystemBus / 2;
 165                 break;
 166
 167         }
 168 #endif
 169
 170 #ifdef CONFIG_SYS_DPAA_FMAN
 171         switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
 172         case 1:
 173                 sysInfo->freqFMan[0] = freqCC_PLL[3];
 174                 break;
 175         case 2:
 176                 sysInfo->freqFMan[0] = freqCC_PLL[3] / 2;
 177                 break;
 178         case 3:
 179                 sysInfo->freqFMan[0] = freqCC_PLL[3] / 3;
 180                 break;
 181         case 4:
 182                 sysInfo->freqFMan[0] = freqCC_PLL[3] / 4;
 183                 break;
 184         case 6:
 185                 sysInfo->freqFMan[0] = freqCC_PLL[4] / 2;
 186                 break;
 187         case 7:
 188                 sysInfo->freqFMan[0] = freqCC_PLL[4] / 3;
 189                 break;
 190         default:
 191                 printf("Error: Unknown FMan1 clock select!\n");
 192         case 0:
 193                 sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
 194                 break;
 195         }
 196 #if (CONFIG_SYS_NUM_FMAN) == 2
 197 #define FM2_CLK_SEL     0x00000038
 198 #define FM2_CLK_SHIFT   3
 199         rcw_tmp = in_be32(&gur->rcwsr[15]);
 200         switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
 201         case 1:
 202                 sysInfo->freqFMan[1] = freqCC_PLL[4];
 203                 break;
 204         case 2:
 205                 sysInfo->freqFMan[1] = freqCC_PLL[4] / 2;
 206                 break;
 207         case 3:
 208                 sysInfo->freqFMan[1] = freqCC_PLL[4] / 3;
 209                 break;
 210         case 4:
 211                 sysInfo->freqFMan[1] = freqCC_PLL[4] / 4;
 212                 break;
 213         case 6:
 214                 sysInfo->freqFMan[1] = freqCC_PLL[3] / 2;
 215                 break;
 216         case 7:
 217                 sysInfo->freqFMan[1] = freqCC_PLL[3] / 3;
 218                 break;
 219         default:
 220                 printf("Error: Unknown FMan2 clock select!\n");
 221         case 0:
 222                 sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
 223                 break;
 224         }
 225 #endif  /* CONFIG_SYS_NUM_FMAN == 2 */
 226 #endif  /* CONFIG_SYS_DPAA_FMAN */
 227
 228 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 229
 230         for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
 231                 u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf;
 232                 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
 233
 234                 sysInfo->freqProcessor[cpu] =
 235                          freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
 236         }
 237 #define PME_CLK_SEL     0x80000000
 238 #define FM1_CLK_SEL     0x40000000
 239 #define FM2_CLK_SEL     0x20000000
 240 #define HWA_ASYNC_DIV   0x04000000
 241 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
 242 #define HWA_CC_PLL      1
 243 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
 244 #define HWA_CC_PLL      2
 245 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
 246 #define HWA_CC_PLL      2
 247 #else
 248 #error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
 249 #endif
 250         rcw_tmp = in_be32(&gur->rcwsr[7]);
 251
 252 #ifdef CONFIG_SYS_DPAA_PME
 253         if (rcw_tmp & PME_CLK_SEL) {
 254                 if (rcw_tmp & HWA_ASYNC_DIV)
 255                         sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 4;
 256                 else
 257                         sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 2;
 258         } else {
 259                 sysInfo->freqPME = sysInfo->freqSystemBus / 2;
 260         }
 261 #endif
 262
 263 #ifdef CONFIG_SYS_DPAA_FMAN
 264         if (rcw_tmp & FM1_CLK_SEL) {
 265                 if (rcw_tmp & HWA_ASYNC_DIV)
 266                         sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 4;
 267                 else
 268                         sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 2;
 269         } else {
 270                 sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
 271         }
 272 #if (CONFIG_SYS_NUM_FMAN) == 2
 273         if (rcw_tmp & FM2_CLK_SEL) {
 274                 if (rcw_tmp & HWA_ASYNC_DIV)
 275                         sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 4;
 276                 else
 277                         sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 2;
 278         } else {
 279                 sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
 280         }
 281 #endif
 282 #endif
 283
 284 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 285
 286 #else /* CONFIG_FSL_CORENET */
 287         uint plat_ratio, e500_ratio, half_freqSystemBus;
 288         int i;
 289 #ifdef CONFIG_QE
 290         __maybe_unused u32 qe_ratio;
 291 #endif
 292
 293         plat_ratio = (gur->porpllsr) & 0x0000003e;
 294         plat_ratio >>= 1;
 295         sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
 296
 297         /* Divide before multiply to avoid integer
 298          * overflow for processor speeds above 2GHz */
 299         half_freqSystemBus = sysInfo->freqSystemBus/2;
 300         for (i = 0; i < cpu_numcores(); i++) {
 301                 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
 302                 sysInfo->freqProcessor[i] = e500_ratio * half_freqSystemBus;
 303         }
 304
 305         /* Note: freqDDRBus is the MCLK frequency, not the data rate. */
 306         sysInfo->freqDDRBus = sysInfo->freqSystemBus;
 307
 308 #ifdef CONFIG_DDR_CLK_FREQ
 309         {
 310                 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
 311                         >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
 312                 if (ddr_ratio != 0x7)
 313                         sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
 314         }
 315 #endif
 316
 317 #ifdef CONFIG_QE
 318 #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
 319         sysInfo->freqQE =  sysInfo->freqSystemBus;
 320 #else
 321         qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
 322                         >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
 323         sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
 324 #endif
 325 #endif
 326
 327 #ifdef CONFIG_SYS_DPAA_FMAN
 328                 sysInfo->freqFMan[0] = sysInfo->freqSystemBus;
 329 #endif
 330
 331 #endif /* CONFIG_FSL_CORENET */
 332
 333 #if defined(CONFIG_FSL_LBC)
 334         uint lcrr_div;
 335 #if defined(CONFIG_SYS_LBC_LCRR)
 336         /* We will program LCRR to this value later */
 337         lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
 338 #else
 339         lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
 340 #endif
 341         if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
 342 #if defined(CONFIG_FSL_CORENET)
 343                 /* If this is corenet based SoC, bit-representation
 344                  * for four times the clock divider values.
 345                  */
 346                 lcrr_div *= 4;
 347 #elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
 348     !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
 349                 /*
 350                  * Yes, the entire PQ38 family use the same
 351                  * bit-representation for twice the clock divider values.
 352                  */
 353                 lcrr_div *= 2;
 354 #endif
 355                 sysInfo->freqLocalBus = sysInfo->freqSystemBus / lcrr_div;
 356         } else {
 357                 /* In case anyone cares what the unknown value is */
 358                 sysInfo->freqLocalBus = lcrr_div;
 359         }
 360 #endif
 361
 362 #if defined(CONFIG_FSL_IFC)
 363         ccr = in_be32(&ifc_regs->ifc_ccr);
 364         ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
 365
 366         sysInfo->freqLocalBus = sysInfo->freqSystemBus / ccr;
 367 #endif
 368 }
 369
 370
 371 int get_clocks (void)
 372 {
 373         sys_info_t sys_info;
 374 #ifdef CONFIG_MPC8544
 375         volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
 376 #endif
 377 #if defined(CONFIG_CPM2)
 378         volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
 379         uint sccr, dfbrg;
 380
 381         /* set VCO = 4 * BRG */
 382         cpm->im_cpm_intctl.sccr &= 0xfffffffc;
 383         sccr = cpm->im_cpm_intctl.sccr;
 384         dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
 385 #endif
 386         get_sys_info (&sys_info);
 387         gd->cpu_clk = sys_info.freqProcessor[0];
 388         gd->bus_clk = sys_info.freqSystemBus;
 389         gd->mem_clk = sys_info.freqDDRBus;
 390         gd->lbc_clk = sys_info.freqLocalBus;
 391
 392 #ifdef CONFIG_QE
 393         gd->qe_clk = sys_info.freqQE;
 394         gd->brg_clk = gd->qe_clk / 2;
 395 #endif
 396         /*
 397          * The base clock for I2C depends on the actual SOC.  Unfortunately,
 398          * there is no pattern that can be used to determine the frequency, so
 399          * the only choice is to look up the actual SOC number and use the value
 400          * for that SOC. This information is taken from application note
 401          * AN2919.
 402          */
 403 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
 404         defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
 405         gd->i2c1_clk = sys_info.freqSystemBus;
 406 #elif defined(CONFIG_MPC8544)
 407         /*
 408          * On the 8544, the I2C clock is the same as the SEC clock.  This can be
 409          * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
 410          * 4.4.3.3 of the 8544 RM.  Note that this might actually work for all
 411          * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
 412          * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
 413          */
 414         if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
 415                 gd->i2c1_clk = sys_info.freqSystemBus / 3;
 416         else
 417                 gd->i2c1_clk = sys_info.freqSystemBus / 2;
 418 #else
 419         /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
 420         gd->i2c1_clk = sys_info.freqSystemBus / 2;
 421 #endif
 422         gd->i2c2_clk = gd->i2c1_clk;
 423
 424 #if defined(CONFIG_FSL_ESDHC)
 425 #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
 426        defined(CONFIG_P1014)
 427         gd->sdhc_clk = gd->bus_clk;
 428 #else
 429         gd->sdhc_clk = gd->bus_clk / 2;
 430 #endif
 431 #endif /* defined(CONFIG_FSL_ESDHC) */
 432
 433 #if defined(CONFIG_CPM2)
 434         gd->vco_out = 2*sys_info.freqSystemBus;
 435         gd->cpm_clk = gd->vco_out / 2;
 436         gd->scc_clk = gd->vco_out / 4;
 437         gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
 438 #endif
 439
 440         if(gd->cpu_clk != 0) return (0);
 441         else return (1);
 442 }
 443
 444
 445 /********************************************
 446  * get_bus_freq
 447  * return system bus freq in Hz
 448  *********************************************/
 449 ulong get_bus_freq (ulong dummy)
 450 {
 451         return gd->bus_clk;
 452 }
 453
 454 /********************************************
 455  * get_ddr_freq
 456  * return ddr bus freq in Hz
 457  *********************************************/
 458 ulong get_ddr_freq (ulong dummy)
 459 {
 460         return gd->mem_clk;
 461 }