2 * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc.
3 * Copyright (C) 2003 Motorola,Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
26 * The processor starts at 0xfffffffc and the code is first executed in the
27 * last 4K page(0xfffff000-0xffffffff) in flash/rom.
31 #include <asm-offsets.h>
36 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
38 #include <ppc_asm.tmpl>
41 #include <asm/cache.h>
45 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
48 * Set up GOT: Global Offset Table
50 * Use r12 to access the GOT
53 GOT_ENTRY(_GOT2_TABLE_)
54 GOT_ENTRY(_FIXUP_TABLE_)
56 #ifndef CONFIG_NAND_SPL
58 GOT_ENTRY(_start_of_vectors)
59 GOT_ENTRY(_end_of_vectors)
60 GOT_ENTRY(transfer_to_handler)
64 GOT_ENTRY(__bss_end__)
65 GOT_ENTRY(__bss_start)
69 * e500 Startup -- after reset only the last 4KB of the effective
70 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
71 * section is located at THIS LAST page and basically does three
72 * things: clear some registers, set up exception tables and
73 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
74 * continue the boot procedure.
76 * Once the boot rom is mapped by TLB entries we can proceed
77 * with normal startup.
85 /* Enable debug exception */
89 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
92 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
96 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
97 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
102 /* Not a supported revision affected by erratum */
106 1: li r27,1 /* Remember for later that we have the erratum */
107 /* Erratum says set bits 55:60 to 001001 */
118 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC)
119 /* ISBC uses L2 as stack.
120 * Disable L2 cache here so that u-boot can enable it later
121 * as part of it's normal flow
124 /* Check if L2 is enabled */
125 mfspr r3, SPRN_L2CSR0
127 ori r2, r2, L2CSR0_L2E@l
131 mfspr r3, SPRN_L2CSR0
133 lis r2,(L2CSR0_L2FL)@h
134 ori r2, r2, (L2CSR0_L2FL)@l
141 mfspr r3, SPRN_L2CSR0
145 mfspr r3, SPRN_L2CSR0
147 ori r2, r2, L2CSR0_L2E@l
157 /* clear registers/arrays not reset by hardware */
161 mtspr L1CSR0,r0 /* invalidate d-cache */
162 mtspr L1CSR1,r0 /* invalidate i-cache */
165 mtspr DBSR,r1 /* Clear all valid bits */
168 * Enable L1 Caches early
172 #ifdef CONFIG_SYS_CACHE_STASHING
173 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
178 /* Enable/invalidate the I-Cache */
179 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
180 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
187 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
188 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
193 andi. r1,r3,L1CSR1_ICE@l
196 /* Enable/invalidate the D-Cache */
197 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
198 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
205 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
206 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
211 andi. r1,r3,L1CSR0_DCE@l
214 .macro create_tlb1_entry esel ts tsize epn wimg rpn perm phy_high scratch
215 lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
216 ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
218 lis \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@h
219 ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@l
221 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
222 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
224 lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
225 ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
227 lis \scratch, \phy_high@h
228 ori \scratch, \scratch, \phy_high@l
236 .macro create_tlb0_entry esel ts tsize epn wimg rpn perm phy_high scratch
237 lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
238 ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
240 lis \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@h
241 ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@l
243 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
244 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
246 lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
247 ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
249 lis \scratch, \phy_high@h
250 ori \scratch, \scratch, \phy_high@l
258 .macro delete_tlb1_entry esel scratch
259 lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
260 ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
270 .macro delete_tlb0_entry esel epn wimg scratch
271 lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
272 ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
276 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
277 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
285 #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
287 * TLB entry for debuggging in AS1
288 * Create temporary TLB entry in AS0 to handle debug exception
289 * As on debug exception MSR is cleared i.e. Address space is changed
290 * to 0. A TLB entry (in AS0) is required to handle debug exception generated
294 #if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
296 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
297 * bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
298 * and this window is outside of 4K boot window.
300 create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
301 0, BOOKE_PAGESZ_4M, \
302 CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
303 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
306 #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
307 create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
308 0, BOOKE_PAGESZ_1M, \
309 CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
310 CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
314 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
315 * because "nexti" will resize TLB to 4K
317 create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
318 0, BOOKE_PAGESZ_256K, \
319 CONFIG_SYS_MONITOR_BASE, MAS2_I, \
320 CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \
326 * Ne need to setup interrupt vector for NAND SPL
327 * because NAND SPL never compiles it.
329 #if !defined(CONFIG_NAND_SPL)
330 /* Setup interrupt vectors */
331 lis r1,CONFIG_SYS_MONITOR_BASE@h
334 lis r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@h
335 ori r3,r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@l
337 addi r4,r3,CriticalInput - _start + _START_OFFSET
338 mtspr IVOR0,r4 /* 0: Critical input */
339 addi r4,r3,MachineCheck - _start + _START_OFFSET
340 mtspr IVOR1,r4 /* 1: Machine check */
341 addi r4,r3,DataStorage - _start + _START_OFFSET
342 mtspr IVOR2,r4 /* 2: Data storage */
343 addi r4,r3,InstStorage - _start + _START_OFFSET
344 mtspr IVOR3,r4 /* 3: Instruction storage */
345 addi r4,r3,ExtInterrupt - _start + _START_OFFSET
346 mtspr IVOR4,r4 /* 4: External interrupt */
347 addi r4,r3,Alignment - _start + _START_OFFSET
348 mtspr IVOR5,r4 /* 5: Alignment */
349 addi r4,r3,ProgramCheck - _start + _START_OFFSET
350 mtspr IVOR6,r4 /* 6: Program check */
351 addi r4,r3,FPUnavailable - _start + _START_OFFSET
352 mtspr IVOR7,r4 /* 7: floating point unavailable */
353 addi r4,r3,SystemCall - _start + _START_OFFSET
354 mtspr IVOR8,r4 /* 8: System call */
355 /* 9: Auxiliary processor unavailable(unsupported) */
356 addi r4,r3,Decrementer - _start + _START_OFFSET
357 mtspr IVOR10,r4 /* 10: Decrementer */
358 addi r4,r3,IntervalTimer - _start + _START_OFFSET
359 mtspr IVOR11,r4 /* 11: Interval timer */
360 addi r4,r3,WatchdogTimer - _start + _START_OFFSET
361 mtspr IVOR12,r4 /* 12: Watchdog timer */
362 addi r4,r3,DataTLBError - _start + _START_OFFSET
363 mtspr IVOR13,r4 /* 13: Data TLB error */
364 addi r4,r3,InstructionTLBError - _start + _START_OFFSET
365 mtspr IVOR14,r4 /* 14: Instruction TLB error */
366 addi r4,r3,DebugBreakpoint - _start + _START_OFFSET
367 mtspr IVOR15,r4 /* 15: Debug */
370 /* Clear and set up some registers. */
373 mtspr DEC,r0 /* prevent dec exceptions */
374 mttbl r0 /* prevent fit & wdt exceptions */
376 mtspr TSR,r1 /* clear all timer exception status */
377 mtspr TCR,r0 /* disable all */
378 mtspr ESR,r0 /* clear exception syndrome register */
379 mtspr MCSR,r0 /* machine check syndrome register */
380 mtxer r0 /* clear integer exception register */
382 #ifdef CONFIG_SYS_BOOK3E_HV
383 mtspr MAS8,r0 /* make sure MAS8 is clear */
386 /* Enable Time Base and Select Time Base Clock */
387 lis r0,HID0_EMCP@h /* Enable machine check */
388 #if defined(CONFIG_ENABLE_36BIT_PHYS)
389 ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */
391 #ifndef CONFIG_E500MC
392 ori r0,r0,HID0_TBEN@l /* Enable Timebase */
396 #ifndef CONFIG_E500MC
397 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
400 cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */
402 /* Set MBDD bit also */
403 ori r0, r0, HID1_MBDD@l
408 #ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
414 /* Enable Branch Prediction */
415 #if defined(CONFIG_BTB)
416 lis r0,BUCSR_ENABLE@h
417 ori r0,r0,BUCSR_ENABLE@l
421 #if defined(CONFIG_SYS_INIT_DBCR)
424 mtspr DBSR,r1 /* Clear all status bits */
425 lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */
426 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
430 #ifdef CONFIG_MPC8569
431 #define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
432 #define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
434 /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
435 * use address space which is more than 12bits, and it must be done in
436 * the 4K boot page. So we set this bit here.
439 /* create a temp mapping TLB0[0] for LBCR */
440 create_tlb0_entry 0, \
441 0, BOOKE_PAGESZ_4K, \
442 CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G, \
443 CONFIG_SYS_LBC_ADDR, MAS3_SW|MAS3_SR, \
446 /* Set LBCR register */
447 lis r4,CONFIG_SYS_LBCR_ADDR@h
448 ori r4,r4,CONFIG_SYS_LBCR_ADDR@l
450 lis r5,CONFIG_SYS_LBC_LBCR@h
451 ori r5,r5,CONFIG_SYS_LBC_LBCR@l
455 /* invalidate this temp TLB */
456 lis r4,CONFIG_SYS_LBC_ADDR@h
457 ori r4,r4,CONFIG_SYS_LBC_ADDR@l
461 #endif /* CONFIG_MPC8569 */
464 * Search for the TLB that covers the code we're executing, and shrink it
465 * so that it covers only this 4K page. That will ensure that any other
466 * TLB we create won't interfere with it. We assume that the TLB exists,
467 * which is why we don't check the Valid bit of MAS1. We also assume
470 * This is necessary, for example, when booting from the on-chip ROM,
471 * which (oddly) creates a single 4GB TLB that covers CCSR and DDR.
473 bl nexti /* Find our address */
474 nexti: mflr r1 /* R1 = our PC */
476 mtspr MAS6, r2 /* Assume the current PID and AS are 0 */
479 tlbsx 0, r1 /* This must succeed */
481 mfspr r14, MAS0 /* Save ESEL for later */
482 rlwinm r14, r14, 16, 0xfff
484 /* Set the size of the TLB to 4KB */
487 andc r3, r3, r2 /* Clear the TSIZE bits */
488 ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l
489 oris r3, r3, MAS1_IPROT@h
493 * Set the base address of the TLB to our PC. We assume that
494 * virtual == physical. We also assume that MAS2_EPN == MAS3_RPN.
497 ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */
499 and r1, r1, r3 /* Our PC, rounded down to the nearest page */
504 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
507 andi. r15, r2, MAS2_I|MAS2_G /* save the old I/G for later */
508 rlwinm r2, r2, 0, ~MAS2_I
512 mtspr MAS2, r2 /* Set the EPN to our PC base address */
517 mtspr MAS3, r2 /* Set the RPN to our PC base address */
524 * Clear out any other TLB entries that may exist, to avoid conflicts.
525 * Our TLB entry is in r14.
527 li r0, TLBIVAX_ALL | TLBIVAX_TLB0
531 mfspr r4, SPRN_TLB1CFG
532 rlwinm r4, r4, 0, TLBnCFG_NENTRY_MASK
537 #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
538 cmpwi cr1, r3, CONFIG_SYS_PPC_E500_DEBUG_TLB
539 cror cr0*4+eq, cr0*4+eq, cr1*4+eq
541 rlwinm r5, r3, 16, MAS0_ESEL_MSK
543 beq 2f /* skip the entry we're executing from */
545 oris r5, r5, MAS0_TLBSEL(1)@h
557 * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default
558 * location is not where we want it. This typically happens on a 36-bit
559 * system, where we want to move CCSR to near the top of 36-bit address space.
561 * To move CCSR, we create two temporary TLBs, one for the old location, and
562 * another for the new location. On CoreNet systems, we also need to create
563 * a special, temporary LAW.
565 * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for
566 * long-term TLBs, so we use TLB0 here.
568 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
570 #if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW)
571 #error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined."
576 * Create a TLB for the new location of CCSR. Register R8 is reserved
577 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR).
579 lis r8, CONFIG_SYS_CCSRBAR@h
580 ori r8, r8, CONFIG_SYS_CCSRBAR@l
581 lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
582 ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
583 create_tlb0_entry 0, \
584 0, BOOKE_PAGESZ_4K, \
585 CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \
586 CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \
587 CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
589 * Create a TLB for the current location of CCSR. Register R9 is reserved
590 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
593 create_tlb0_entry 1, \
594 0, BOOKE_PAGESZ_4K, \
595 CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \
596 CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \
597 0, r3 /* The default CCSR address is always a 32-bit number */
601 * We have a TLB for what we think is the current (old) CCSR. Let's
602 * verify that, otherwise we won't be able to move it.
603 * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only
604 * need to compare the lower 32 bits of CCSRBAR on CoreNet systems.
607 lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h
608 ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l
609 #ifdef CONFIG_FSL_CORENET
610 lwz r1, 4(r9) /* CCSRBARL */
612 lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */
619 * If the value we read from CCSRBARL is not what we expect, then
620 * enter an infinite loop. This will at least allow a debugger to
621 * halt execution and examine TLBs, etc. There's no point in going
625 bne infinite_debug_loop
627 #ifdef CONFIG_FSL_CORENET
629 #define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
630 #define LAW_EN 0x80000000
631 #define LAW_SIZE_4K 0xb
632 #define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K)
633 #define CCSRAR_C 0x80000000 /* Commit */
637 * On CoreNet systems, we create the temporary LAW using a special LAW
638 * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR.
640 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
641 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
642 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
643 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
644 lis r2, CCSRBAR_LAWAR@h
645 ori r2, r2, CCSRBAR_LAWAR@l
647 stw r0, 0xc00(r9) /* LAWBARH0 */
648 stw r1, 0xc04(r9) /* LAWBARL0 */
650 stw r2, 0xc08(r9) /* LAWAR0 */
653 * Read back from LAWAR to ensure the update is complete. e500mc
654 * cores also require an isync.
656 lwz r0, 0xc08(r9) /* LAWAR0 */
660 * Read the current CCSRBARH and CCSRBARL using load word instructions.
661 * Follow this with an isync instruction. This forces any outstanding
662 * accesses to configuration space to completion.
665 lwz r0, 0(r9) /* CCSRBARH */
666 lwz r0, 4(r9) /* CCSRBARL */
670 * Write the new values for CCSRBARH and CCSRBARL to their old
671 * locations. The CCSRBARH has a shadow register. When the CCSRBARH
672 * has a new value written it loads a CCSRBARH shadow register. When
673 * the CCSRBARL is written, the CCSRBARH shadow register contents
674 * along with the CCSRBARL value are loaded into the CCSRBARH and
675 * CCSRBARL registers, respectively. Follow this with a sync
679 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
680 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
681 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
682 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
684 ori r2, r2, CCSRAR_C@l
686 stw r0, 0(r9) /* Write to CCSRBARH */
687 sync /* Make sure we write to CCSRBARH first */
688 stw r1, 4(r9) /* Write to CCSRBARL */
692 * Write a 1 to the commit bit (C) of CCSRAR at the old location.
693 * Follow this with a sync instruction.
698 /* Delete the temporary LAW */
707 #else /* #ifdef CONFIG_FSL_CORENET */
711 * Read the current value of CCSRBAR using a load word instruction
712 * followed by an isync. This forces all accesses to configuration
719 /* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */
720 #define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \
721 (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12))
723 /* Write the new value to CCSRBAR. */
724 lis r0, CCSRBAR_PHYS_RS12@h
725 ori r0, r0, CCSRBAR_PHYS_RS12@l
730 * The manual says to perform a load of an address that does not
731 * access configuration space or the on-chip SRAM using an existing TLB,
732 * but that doesn't appear to be necessary. We will do the isync,
738 * Read the contents of CCSRBAR from its new location, followed by
744 #endif /* #ifdef CONFIG_FSL_CORENET */
746 /* Delete the temporary TLBs */
748 delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3
749 delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3
751 #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
753 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
756 * Create a TLB for the MMR location of CCSR
757 * to access L2CSR0 register
759 create_tlb0_entry 0, \
760 0, BOOKE_PAGESZ_4K, \
761 CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \
762 CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \
763 CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
765 enable_l2_cluster_l2:
766 /* enable L2 cache */
767 lis r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h
768 ori r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l
769 li r4, 33 /* stash id */
771 lis r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h
772 ori r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l
774 stw r4, 0(r3) /* invalidate L2 */
783 stw r4, 0(r3) /* eanble L2 */
785 delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
788 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
789 #define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
790 #define LAW_SIZE_1M 0x13
791 #define DCSRBAR_LAWAR (LAW_EN | (0x1d << 20) | LAW_SIZE_1M)
797 * Create a TLB entry for CCSR
799 * We're executing out of TLB1 entry in r14, and that's the only
800 * TLB entry that exists. To allocate some TLB entries for our
801 * own use, flip a bit high enough that we won't flip it again
806 lis r0, MAS0_TLBSEL(1)@h
807 rlwimi r0, r8, 16, MAS0_ESEL_MSK
808 lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@h
809 ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@l
810 lis r7, CONFIG_SYS_CCSRBAR@h
811 ori r7, r7, CONFIG_SYS_CCSRBAR@l
812 ori r2, r7, MAS2_I|MAS2_G
813 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
814 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
815 lis r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
816 ori r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
827 /* Map DCSR temporarily to physical address zero */
829 lis r3, DCSRBAR_LAWAR@h
830 ori r3, r3, DCSRBAR_LAWAR@l
832 stw r0, 0xc00(r7) /* LAWBARH0 */
833 stw r0, 0xc04(r7) /* LAWBARL0 */
835 stw r3, 0xc08(r7) /* LAWAR0 */
837 /* Read back from LAWAR to ensure the update is complete. */
838 lwz r3, 0xc08(r7) /* LAWAR0 */
841 /* Create a TLB entry for DCSR at zero */
844 lis r0, MAS0_TLBSEL(1)@h
845 rlwimi r0, r9, 16, MAS0_ESEL_MSK
846 lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h
847 ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l
848 li r6, 0 /* DCSR effective address */
849 ori r2, r6, MAS2_I|MAS2_G
850 li r3, MAS3_SW|MAS3_SR
862 /* enable the timebase */
863 #define CTBENR 0xe2084
865 addis r4, r7, CTBENR@ha
871 .macro erratum_set_ccsr offset value
872 addis r3, r7, \offset@ha
874 addi r3, r3, \offset@l
879 .macro erratum_set_dcsr offset value
880 addis r3, r6, \offset@ha
882 addi r3, r3, \offset@l
887 erratum_set_dcsr 0xb0e08 0xe0201800
888 erratum_set_dcsr 0xb0e18 0xe0201800
889 erratum_set_dcsr 0xb0e38 0xe0400000
890 erratum_set_dcsr 0xb0008 0x00900000
891 erratum_set_dcsr 0xb0e40 0xe00a0000
892 erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
893 erratum_set_ccsr 0x10f00 0x415e5000
894 erratum_set_ccsr 0x11f00 0x415e5000
896 /* Make temp mapping uncacheable again, if it was initially */
901 rlwimi r4, r15, 0, MAS2_I
902 rlwimi r4, r15, 0, MAS2_G
909 /* Clear the cache */
910 lis r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
911 ori r3,r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
921 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
922 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
932 /* Remove temporary mappings */
933 lis r0, MAS0_TLBSEL(1)@h
934 rlwimi r0, r9, 16, MAS0_ESEL_MSK
944 stw r3, 0xc08(r7) /* LAWAR0 */
948 lis r0, MAS0_TLBSEL(1)@h
949 rlwimi r0, r8, 16, MAS0_ESEL_MSK
960 /* r3 = addr, r4 = value, clobbers r5, r11, r12 */
962 /* Lock two cache lines into I-Cache */
964 mfspr r11, SPRN_L1CSR1
965 rlwinm r11, r11, 0, ~L1CSR1_ICUL
968 mtspr SPRN_L1CSR1, r11
979 mfspr r11, SPRN_L1CSR1
980 3: andi. r11, r11, L1CSR1_ICUL
987 mfspr r11, SPRN_L1CSR1
988 3: andi. r11, r11, L1CSR1_ICUL
993 /* Inside a locked cacheline, wait a while, write, then wait a while */
997 addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
998 4: mfspr r5, SPRN_TBRL
1005 addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
1006 4: mfspr r5, SPRN_TBRL
1013 * Fill out the rest of this cache line and the next with nops,
1014 * to ensure that nothing outside the locked area will be
1015 * fetched due to a branch.
1022 mfspr r11, SPRN_L1CSR1
1023 rlwinm r11, r11, 0, ~L1CSR1_ICUL
1026 mtspr SPRN_L1CSR1, r11
1035 create_init_ram_area:
1036 lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
1037 ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
1039 #if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
1040 /* create a temp mapping in AS=1 to the 4M boot window */
1041 create_tlb1_entry 15, \
1042 1, BOOKE_PAGESZ_4M, \
1043 CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
1044 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
1047 #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
1048 /* create a temp mapping in AS = 1 for Flash mapping
1049 * created by PBL for ISBC code
1051 create_tlb1_entry 15, \
1052 1, BOOKE_PAGESZ_1M, \
1053 CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
1054 CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
1058 * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
1059 * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage.
1061 create_tlb1_entry 15, \
1062 1, BOOKE_PAGESZ_1M, \
1063 CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
1064 CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \
1068 /* create a temp mapping in AS=1 to the stack */
1069 #if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
1070 defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
1071 create_tlb1_entry 14, \
1072 1, BOOKE_PAGESZ_16K, \
1073 CONFIG_SYS_INIT_RAM_ADDR, 0, \
1074 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \
1075 CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6
1078 create_tlb1_entry 14, \
1079 1, BOOKE_PAGESZ_16K, \
1080 CONFIG_SYS_INIT_RAM_ADDR, 0, \
1081 CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \
1085 lis r6,MSR_IS|MSR_DS|MSR_DE@h
1086 ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l
1088 ori r7,r7,switch_as@l
1095 /* L1 DCache is used for initial RAM */
1097 /* Allocate Initial RAM in data cache.
1099 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1100 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1103 /* cache size * 1024 / (2 * L1 line size) */
1104 slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
1110 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1113 /* Jump out the last 4K page and continue to 'normal' start */
1114 #ifdef CONFIG_SYS_RAMBOOT
1117 /* Calculate absolute address in FLASH and jump there */
1118 /*--------------------------------------------------------------*/
1119 lis r3,CONFIG_SYS_MONITOR_BASE@h
1120 ori r3,r3,CONFIG_SYS_MONITOR_BASE@l
1121 addi r3,r3,_start_cont - _start + _START_OFFSET
1129 .long 0x27051956 /* U-BOOT Magic Number */
1130 .globl version_string
1132 .ascii U_BOOT_VERSION_STRING, "\0"
1137 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
1138 lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
1139 ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
1141 stw r0,0(r3) /* Terminate Back Chain */
1142 stw r0,+4(r3) /* NULL return address. */
1143 mr r1,r3 /* Transfer to SP(r1) */
1148 /* switch back to AS = 0 */
1149 lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
1150 ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
1158 /* NOTREACHED - board_init_f() does not return */
1160 #ifndef CONFIG_NAND_SPL
1161 . = EXC_OFF_SYS_RESET
1162 .globl _start_of_vectors
1165 /* Critical input. */
1166 CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
1169 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
1171 /* Data Storage exception. */
1172 STD_EXCEPTION(0x0300, DataStorage, UnknownException)
1174 /* Instruction Storage exception. */
1175 STD_EXCEPTION(0x0400, InstStorage, UnknownException)
1177 /* External Interrupt exception. */
1178 STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
1180 /* Alignment exception. */
1183 EXCEPTION_PROLOG(SRR0, SRR1)
1188 addi r3,r1,STACK_FRAME_OVERHEAD
1189 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
1191 /* Program check exception */
1194 EXCEPTION_PROLOG(SRR0, SRR1)
1195 addi r3,r1,STACK_FRAME_OVERHEAD
1196 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
1197 MSR_KERNEL, COPY_EE)
1199 /* No FPU on MPC85xx. This exception is not supposed to happen.
1201 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
1205 * r0 - SYSCALL number
1209 addis r11,r0,0 /* get functions table addr */
1210 ori r11,r11,0 /* Note: this code is patched in trap_init */
1211 addis r12,r0,0 /* get number of functions */
1217 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
1221 li r20,0xd00-4 /* Get stack pointer */
1223 subi r12,r12,12 /* Adjust stack pointer */
1224 li r0,0xc00+_end_back-SystemCall
1225 cmplw 0,r0,r12 /* Check stack overflow */
1236 li r12,0xc00+_back-SystemCall
1244 mfmsr r11 /* Disable interrupts */
1248 SYNC /* Some chip revs need this... */
1252 li r12,0xd00-4 /* restore regs */
1262 addi r12,r12,12 /* Adjust stack pointer */
1270 STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
1271 STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
1272 STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
1274 STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
1275 STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
1277 CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
1279 .globl _end_of_vectors
1283 . = . + (0x100 - ( . & 0xff )) /* align for debug */
1286 * This code finishes saving the registers to the exception frame
1287 * and jumps to the appropriate handler for the exception.
1288 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1290 .globl transfer_to_handler
1291 transfer_to_handler:
1302 andi. r24,r23,0x3f00 /* get vector offset */
1306 mtspr SPRG2,r22 /* r1 is now kernel sp */
1308 lwz r24,0(r23) /* virtual address of handler */
1309 lwz r23,4(r23) /* where to go when done */
1314 rfi /* jump to handler, enable MMU */
1317 mfmsr r28 /* Disable interrupts */
1321 SYNC /* Some chip revs need this... */
1336 lwz r2,_NIP(r1) /* Restore environment */
1347 mfmsr r28 /* Disable interrupts */
1351 SYNC /* Some chip revs need this... */
1366 lwz r2,_NIP(r1) /* Restore environment */
1377 mfmsr r28 /* Disable interrupts */
1381 SYNC /* Some chip revs need this... */
1396 lwz r2,_NIP(r1) /* Restore environment */
1398 mtspr SPRN_MCSRR0,r2
1399 mtspr SPRN_MCSRR1,r0
1410 .globl invalidate_icache
1413 ori r0,r0,L1CSR1_ICFI
1418 blr /* entire I cache */
1420 .globl invalidate_dcache
1423 ori r0,r0,L1CSR0_DCFI
1430 .globl icache_enable
1433 bl invalidate_icache
1443 .globl icache_disable
1447 ori r3,r3,L1CSR1_ICE
1453 .globl icache_status
1456 andi. r3,r3,L1CSR1_ICE
1459 .globl dcache_enable
1462 bl invalidate_dcache
1474 .globl dcache_disable
1478 ori r4,r4,L1CSR0_DCE
1484 .globl dcache_status
1487 andi. r3,r3,L1CSR0_DCE
1510 /*------------------------------------------------------------------------------- */
1512 /* Description: Input 8 bits */
1513 /*------------------------------------------------------------------------------- */
1519 /*------------------------------------------------------------------------------- */
1520 /* Function: out8 */
1521 /* Description: Output 8 bits */
1522 /*------------------------------------------------------------------------------- */
1529 /*------------------------------------------------------------------------------- */
1530 /* Function: out16 */
1531 /* Description: Output 16 bits */
1532 /*------------------------------------------------------------------------------- */
1539 /*------------------------------------------------------------------------------- */
1540 /* Function: out16r */
1541 /* Description: Byte reverse and output 16 bits */
1542 /*------------------------------------------------------------------------------- */
1549 /*------------------------------------------------------------------------------- */
1550 /* Function: out32 */
1551 /* Description: Output 32 bits */
1552 /*------------------------------------------------------------------------------- */
1559 /*------------------------------------------------------------------------------- */
1560 /* Function: out32r */
1561 /* Description: Byte reverse and output 32 bits */
1562 /*------------------------------------------------------------------------------- */
1569 /*------------------------------------------------------------------------------- */
1570 /* Function: in16 */
1571 /* Description: Input 16 bits */
1572 /*------------------------------------------------------------------------------- */
1578 /*------------------------------------------------------------------------------- */
1579 /* Function: in16r */
1580 /* Description: Input 16 bits and byte reverse */
1581 /*------------------------------------------------------------------------------- */
1587 /*------------------------------------------------------------------------------- */
1588 /* Function: in32 */
1589 /* Description: Input 32 bits */
1590 /*------------------------------------------------------------------------------- */
1596 /*------------------------------------------------------------------------------- */
1597 /* Function: in32r */
1598 /* Description: Input 32 bits and byte reverse */
1599 /*------------------------------------------------------------------------------- */
1604 #endif /* !CONFIG_NAND_SPL */
1606 /*------------------------------------------------------------------------------*/
1609 * void write_tlb(mas0, mas1, mas2, mas3, mas7)
1617 #ifdef CONFIG_ENABLE_36BIT_PHYS
1621 #ifdef CONFIG_SYS_BOOK3E_HV
1631 * void relocate_code (addr_sp, gd, addr_moni)
1633 * This "function" does not return, instead it continues in RAM
1634 * after relocating the monitor code.
1638 * r5 = length in bytes
1639 * r6 = cachelinesize
1641 .globl relocate_code
1643 mr r1,r3 /* Set new stack pointer */
1644 mr r9,r4 /* Save copy of Init Data pointer */
1645 mr r10,r5 /* Save copy of Destination Address */
1648 mr r3,r5 /* Destination Address */
1649 lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1650 ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
1651 lwz r5,GOT(__init_end)
1653 li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
1658 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1664 /* First our own GOT */
1666 /* the the one used by the C code */
1676 beq cr1,4f /* In place copy is not necessary */
1677 beq 7f /* Protect against 0 count */
1696 * Now flush the cache: note that we must start from a cache aligned
1697 * address. Otherwise we might miss one cache line.
1701 beq 7f /* Always flush prefetch queue in any case */
1709 sync /* Wait for all dcbst to complete on bus */
1715 7: sync /* Wait for all icbi to complete on bus */
1719 * We are done. Do not return, instead branch to second part of board
1720 * initialization, now running from RAM.
1723 addi r0,r10,in_ram - _start + _START_OFFSET
1726 * As IVPR is going to point RAM address,
1727 * Make sure IVOR15 has valid opcode to support debugger
1732 * Re-point the IVPR at RAM
1737 blr /* NEVER RETURNS! */
1742 * Relocation Function, r12 point to got2+0x8000
1744 * Adjust got2 pointers, no need to check for 0, this code
1745 * already puts a few entries in the table.
1747 li r0,__got2_entries@sectoff@l
1748 la r3,GOT(_GOT2_TABLE_)
1749 lwz r11,GOT(_GOT2_TABLE_)
1761 * Now adjust the fixups and the pointers to the fixups
1762 * in case we need to move ourselves again.
1764 li r0,__fixup_entries@sectoff@l
1765 lwz r3,GOT(_FIXUP_TABLE_)
1781 * Now clear BSS segment
1783 lwz r3,GOT(__bss_start)
1784 lwz r4,GOT(__bss_end__)
1797 mr r3,r9 /* Init Data pointer */
1798 mr r4,r10 /* Destination Address */
1801 #ifndef CONFIG_NAND_SPL
1803 * Copy exception vector code to low memory
1806 * r7: source address, r8: end address, r9: target address
1810 mflr r4 /* save link register */
1812 lwz r7,GOT(_start_of_vectors)
1813 lwz r8,GOT(_end_of_vectors)
1815 li r9,0x100 /* reset vector always at 0x100 */
1818 bgelr /* return if r7>=r8 - just in case */
1828 * relocate `hdlr' and `int_return' entries
1830 li r7,.L_CriticalInput - _start + _START_OFFSET
1832 li r7,.L_MachineCheck - _start + _START_OFFSET
1834 li r7,.L_DataStorage - _start + _START_OFFSET
1836 li r7,.L_InstStorage - _start + _START_OFFSET
1838 li r7,.L_ExtInterrupt - _start + _START_OFFSET
1840 li r7,.L_Alignment - _start + _START_OFFSET
1842 li r7,.L_ProgramCheck - _start + _START_OFFSET
1844 li r7,.L_FPUnavailable - _start + _START_OFFSET
1846 li r7,.L_Decrementer - _start + _START_OFFSET
1848 li r7,.L_IntervalTimer - _start + _START_OFFSET
1849 li r8,_end_of_vectors - _start + _START_OFFSET
1852 addi r7,r7,0x100 /* next exception vector */
1856 /* Update IVORs as per relocated vector table address */
1858 mtspr IVOR0,r7 /* 0: Critical input */
1860 mtspr IVOR1,r7 /* 1: Machine check */
1862 mtspr IVOR2,r7 /* 2: Data storage */
1864 mtspr IVOR3,r7 /* 3: Instruction storage */
1866 mtspr IVOR4,r7 /* 4: External interrupt */
1868 mtspr IVOR5,r7 /* 5: Alignment */
1870 mtspr IVOR6,r7 /* 6: Program check */
1872 mtspr IVOR7,r7 /* 7: floating point unavailable */
1874 mtspr IVOR8,r7 /* 8: System call */
1875 /* 9: Auxiliary processor unavailable(unsupported) */
1877 mtspr IVOR10,r7 /* 10: Decrementer */
1879 mtspr IVOR11,r7 /* 11: Interval timer */
1881 mtspr IVOR12,r7 /* 12: Watchdog timer */
1883 mtspr IVOR13,r7 /* 13: Data TLB error */
1885 mtspr IVOR14,r7 /* 14: Instruction TLB error */
1887 mtspr IVOR15,r7 /* 15: Debug */
1892 mtlr r4 /* restore link register */
1895 .globl unlock_ram_in_cache
1896 unlock_ram_in_cache:
1897 /* invalidate the INIT_RAM section */
1898 lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
1899 ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
1902 slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
1905 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1909 /* Invalidate the TLB entries for the cache */
1910 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1911 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1924 mfspr r3,SPRN_L1CFG0
1926 rlwinm r5,r3,9,3 /* Extract cache block size */
1927 twlgti r5,1 /* Only 32 and 64 byte cache blocks
1928 * are currently defined.
1931 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
1932 * log2(number of ways)
1934 slw r5,r4,r5 /* r5 = cache block size */
1936 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
1937 mulli r7,r7,13 /* An 8-way cache will require 13
1942 /* save off HID0 and set DCFA */
1944 ori r9,r8,HID0_DCFA@l
1951 1: lwz r3,0(r4) /* Load... */
1959 1: dcbf 0,r4 /* ...and flush. */
1972 #include "fixed_ivor.S"
1974 #endif /* !CONFIG_NAND_SPL */