2 * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc.
3 * Copyright (C) 2003 Motorola,Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
26 * The processor starts at 0xfffffffc and the code is first executed in the
27 * last 4K page(0xfffff000-0xffffffff) in flash/rom.
31 #include <asm-offsets.h>
36 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
38 #include <ppc_asm.tmpl>
41 #include <asm/cache.h>
45 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
48 * Set up GOT: Global Offset Table
50 * Use r12 to access the GOT
53 GOT_ENTRY(_GOT2_TABLE_)
54 GOT_ENTRY(_FIXUP_TABLE_)
56 #ifndef CONFIG_NAND_SPL
58 GOT_ENTRY(_start_of_vectors)
59 GOT_ENTRY(_end_of_vectors)
60 GOT_ENTRY(transfer_to_handler)
64 GOT_ENTRY(__bss_end__)
65 GOT_ENTRY(__bss_start)
69 * e500 Startup -- after reset only the last 4KB of the effective
70 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
71 * section is located at THIS LAST page and basically does three
72 * things: clear some registers, set up exception tables and
73 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
74 * continue the boot procedure.
76 * Once the boot rom is mapped by TLB entries we can proceed
77 * with normal startup.
85 /* Enable debug exception */
89 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
92 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
96 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
97 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
102 /* Not a supported revision affected by erratum */
106 1: li r27,1 /* Remember for later that we have the erratum */
107 /* Erratum says set bits 55:60 to 001001 */
118 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC)
119 /* ISBC uses L2 as stack.
120 * Disable L2 cache here so that u-boot can enable it later
121 * as part of it's normal flow
124 /* Check if L2 is enabled */
125 mfspr r3, SPRN_L2CSR0
127 ori r2, r2, L2CSR0_L2E@l
131 mfspr r3, SPRN_L2CSR0
133 lis r2,(L2CSR0_L2FL)@h
134 ori r2, r2, (L2CSR0_L2FL)@l
141 mfspr r3, SPRN_L2CSR0
145 mfspr r3, SPRN_L2CSR0
147 ori r2, r2, L2CSR0_L2E@l
157 /* clear registers/arrays not reset by hardware */
161 mtspr L1CSR0,r0 /* invalidate d-cache */
162 mtspr L1CSR1,r0 /* invalidate i-cache */
165 mtspr DBSR,r1 /* Clear all valid bits */
168 * Enable L1 Caches early
172 #ifdef CONFIG_SYS_CACHE_STASHING
173 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
178 /* Enable/invalidate the I-Cache */
179 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
180 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
187 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
188 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
193 andi. r1,r3,L1CSR1_ICE@l
196 /* Enable/invalidate the D-Cache */
197 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
198 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
205 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
206 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
211 andi. r1,r3,L1CSR0_DCE@l
214 .macro create_tlb1_entry esel ts tsize epn wimg rpn perm phy_high scratch
215 lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
216 ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
218 lis \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@h
219 ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@l
221 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
222 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
224 lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
225 ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
227 lis \scratch, \phy_high@h
228 ori \scratch, \scratch, \phy_high@l
236 .macro create_tlb0_entry esel ts tsize epn wimg rpn perm phy_high scratch
237 lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
238 ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
240 lis \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@h
241 ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@l
243 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
244 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
246 lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
247 ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
249 lis \scratch, \phy_high@h
250 ori \scratch, \scratch, \phy_high@l
258 .macro delete_tlb1_entry esel scratch
259 lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
260 ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
270 .macro delete_tlb0_entry esel epn wimg scratch
271 lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
272 ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
276 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
277 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
286 * Ne need to setup interrupt vector for NAND SPL
287 * because NAND SPL never compiles it.
289 #if !defined(CONFIG_NAND_SPL)
290 /* Setup interrupt vectors */
291 lis r1,CONFIG_SYS_MONITOR_BASE@h
294 lis r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@h
295 ori r3,r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@l
297 addi r4,r3,CriticalInput - _start + _START_OFFSET
298 mtspr IVOR0,r4 /* 0: Critical input */
299 addi r4,r3,MachineCheck - _start + _START_OFFSET
300 mtspr IVOR1,r4 /* 1: Machine check */
301 addi r4,r3,DataStorage - _start + _START_OFFSET
302 mtspr IVOR2,r4 /* 2: Data storage */
303 addi r4,r3,InstStorage - _start + _START_OFFSET
304 mtspr IVOR3,r4 /* 3: Instruction storage */
305 addi r4,r3,ExtInterrupt - _start + _START_OFFSET
306 mtspr IVOR4,r4 /* 4: External interrupt */
307 addi r4,r3,Alignment - _start + _START_OFFSET
308 mtspr IVOR5,r4 /* 5: Alignment */
309 addi r4,r3,ProgramCheck - _start + _START_OFFSET
310 mtspr IVOR6,r4 /* 6: Program check */
311 addi r4,r3,FPUnavailable - _start + _START_OFFSET
312 mtspr IVOR7,r4 /* 7: floating point unavailable */
313 addi r4,r3,SystemCall - _start + _START_OFFSET
314 mtspr IVOR8,r4 /* 8: System call */
315 /* 9: Auxiliary processor unavailable(unsupported) */
316 addi r4,r3,Decrementer - _start + _START_OFFSET
317 mtspr IVOR10,r4 /* 10: Decrementer */
318 addi r4,r3,IntervalTimer - _start + _START_OFFSET
319 mtspr IVOR11,r4 /* 11: Interval timer */
320 addi r4,r3,WatchdogTimer - _start + _START_OFFSET
321 mtspr IVOR12,r4 /* 12: Watchdog timer */
322 addi r4,r3,DataTLBError - _start + _START_OFFSET
323 mtspr IVOR13,r4 /* 13: Data TLB error */
324 addi r4,r3,InstructionTLBError - _start + _START_OFFSET
325 mtspr IVOR14,r4 /* 14: Instruction TLB error */
326 addi r4,r3,DebugBreakpoint - _start + _START_OFFSET
327 mtspr IVOR15,r4 /* 15: Debug */
330 /* Clear and set up some registers. */
333 mtspr DEC,r0 /* prevent dec exceptions */
334 mttbl r0 /* prevent fit & wdt exceptions */
336 mtspr TSR,r1 /* clear all timer exception status */
337 mtspr TCR,r0 /* disable all */
338 mtspr ESR,r0 /* clear exception syndrome register */
339 mtspr MCSR,r0 /* machine check syndrome register */
340 mtxer r0 /* clear integer exception register */
342 #ifdef CONFIG_SYS_BOOK3E_HV
343 mtspr MAS8,r0 /* make sure MAS8 is clear */
346 /* Enable Time Base and Select Time Base Clock */
347 lis r0,HID0_EMCP@h /* Enable machine check */
348 #if defined(CONFIG_ENABLE_36BIT_PHYS)
349 ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */
351 #ifndef CONFIG_E500MC
352 ori r0,r0,HID0_TBEN@l /* Enable Timebase */
356 #ifndef CONFIG_E500MC
357 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
360 cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */
362 /* Set MBDD bit also */
363 ori r0, r0, HID1_MBDD@l
368 #ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
374 /* Enable Branch Prediction */
375 #if defined(CONFIG_BTB)
376 lis r0,BUCSR_ENABLE@h
377 ori r0,r0,BUCSR_ENABLE@l
381 #if defined(CONFIG_SYS_INIT_DBCR)
384 mtspr DBSR,r1 /* Clear all status bits */
385 lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */
386 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
390 #ifdef CONFIG_MPC8569
391 #define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
392 #define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
394 /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
395 * use address space which is more than 12bits, and it must be done in
396 * the 4K boot page. So we set this bit here.
399 /* create a temp mapping TLB0[0] for LBCR */
400 create_tlb0_entry 0, \
401 0, BOOKE_PAGESZ_4K, \
402 CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G, \
403 CONFIG_SYS_LBC_ADDR, MAS3_SW|MAS3_SR, \
406 /* Set LBCR register */
407 lis r4,CONFIG_SYS_LBCR_ADDR@h
408 ori r4,r4,CONFIG_SYS_LBCR_ADDR@l
410 lis r5,CONFIG_SYS_LBC_LBCR@h
411 ori r5,r5,CONFIG_SYS_LBC_LBCR@l
415 /* invalidate this temp TLB */
416 lis r4,CONFIG_SYS_LBC_ADDR@h
417 ori r4,r4,CONFIG_SYS_LBC_ADDR@l
421 #endif /* CONFIG_MPC8569 */
424 * Search for the TLB that covers the code we're executing, and shrink it
425 * so that it covers only this 4K page. That will ensure that any other
426 * TLB we create won't interfere with it. We assume that the TLB exists,
427 * which is why we don't check the Valid bit of MAS1. We also assume
430 * This is necessary, for example, when booting from the on-chip ROM,
431 * which (oddly) creates a single 4GB TLB that covers CCSR and DDR.
433 bl nexti /* Find our address */
434 nexti: mflr r1 /* R1 = our PC */
436 mtspr MAS6, r2 /* Assume the current PID and AS are 0 */
439 tlbsx 0, r1 /* This must succeed */
441 mfspr r14, MAS0 /* Save ESEL for later */
442 rlwinm r14, r14, 16, 0xfff
444 /* Set the size of the TLB to 4KB */
447 andc r3, r3, r2 /* Clear the TSIZE bits */
448 ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l
449 oris r3, r3, MAS1_IPROT@h
453 * Set the base address of the TLB to our PC. We assume that
454 * virtual == physical. We also assume that MAS2_EPN == MAS3_RPN.
457 ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */
459 and r1, r1, r3 /* Our PC, rounded down to the nearest page */
464 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
467 andi. r15, r2, MAS2_I|MAS2_G /* save the old I/G for later */
468 rlwinm r2, r2, 0, ~MAS2_I
472 mtspr MAS2, r2 /* Set the EPN to our PC base address */
477 mtspr MAS3, r2 /* Set the RPN to our PC base address */
484 * Clear out any other TLB entries that may exist, to avoid conflicts.
485 * Our TLB entry is in r14.
487 li r0, TLBIVAX_ALL | TLBIVAX_TLB0
491 mfspr r4, SPRN_TLB1CFG
492 rlwinm r4, r4, 0, TLBnCFG_NENTRY_MASK
497 rlwinm r5, r3, 16, MAS0_ESEL_MSK
499 beq 2f /* skip the entry we're executing from */
501 oris r5, r5, MAS0_TLBSEL(1)@h
512 #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)
514 * TLB entry for debuggging in AS1
515 * Create temporary TLB entry in AS0 to handle debug exception
516 * As on debug exception MSR is cleared i.e. Address space is changed
517 * to 0. A TLB entry (in AS0) is required to handle debug exception generated
521 #if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
523 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
524 * bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
525 * and this window is outside of 4K boot window.
527 create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
528 0, BOOKE_PAGESZ_4M, \
529 CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
530 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
533 #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
534 create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
535 0, BOOKE_PAGESZ_1M, \
536 CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
537 CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
541 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
542 * because "nexti" will resize TLB to 4K
544 create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
545 0, BOOKE_PAGESZ_256K, \
546 CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \
547 CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS3_SX|MAS3_SW|MAS3_SR, \
553 * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default
554 * location is not where we want it. This typically happens on a 36-bit
555 * system, where we want to move CCSR to near the top of 36-bit address space.
557 * To move CCSR, we create two temporary TLBs, one for the old location, and
558 * another for the new location. On CoreNet systems, we also need to create
559 * a special, temporary LAW.
561 * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for
562 * long-term TLBs, so we use TLB0 here.
564 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
566 #if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW)
567 #error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined."
572 * Create a TLB for the new location of CCSR. Register R8 is reserved
573 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR).
575 lis r8, CONFIG_SYS_CCSRBAR@h
576 ori r8, r8, CONFIG_SYS_CCSRBAR@l
577 lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
578 ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
579 create_tlb0_entry 0, \
580 0, BOOKE_PAGESZ_4K, \
581 CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \
582 CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \
583 CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
585 * Create a TLB for the current location of CCSR. Register R9 is reserved
586 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
589 create_tlb0_entry 1, \
590 0, BOOKE_PAGESZ_4K, \
591 CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \
592 CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \
593 0, r3 /* The default CCSR address is always a 32-bit number */
597 * We have a TLB for what we think is the current (old) CCSR. Let's
598 * verify that, otherwise we won't be able to move it.
599 * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only
600 * need to compare the lower 32 bits of CCSRBAR on CoreNet systems.
603 lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h
604 ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l
605 #ifdef CONFIG_FSL_CORENET
606 lwz r1, 4(r9) /* CCSRBARL */
608 lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */
615 * If the value we read from CCSRBARL is not what we expect, then
616 * enter an infinite loop. This will at least allow a debugger to
617 * halt execution and examine TLBs, etc. There's no point in going
621 bne infinite_debug_loop
623 #ifdef CONFIG_FSL_CORENET
625 #define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
626 #define LAW_EN 0x80000000
627 #define LAW_SIZE_4K 0xb
628 #define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K)
629 #define CCSRAR_C 0x80000000 /* Commit */
633 * On CoreNet systems, we create the temporary LAW using a special LAW
634 * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR.
636 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
637 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
638 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
639 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
640 lis r2, CCSRBAR_LAWAR@h
641 ori r2, r2, CCSRBAR_LAWAR@l
643 stw r0, 0xc00(r9) /* LAWBARH0 */
644 stw r1, 0xc04(r9) /* LAWBARL0 */
646 stw r2, 0xc08(r9) /* LAWAR0 */
649 * Read back from LAWAR to ensure the update is complete. e500mc
650 * cores also require an isync.
652 lwz r0, 0xc08(r9) /* LAWAR0 */
656 * Read the current CCSRBARH and CCSRBARL using load word instructions.
657 * Follow this with an isync instruction. This forces any outstanding
658 * accesses to configuration space to completion.
661 lwz r0, 0(r9) /* CCSRBARH */
662 lwz r0, 4(r9) /* CCSRBARL */
666 * Write the new values for CCSRBARH and CCSRBARL to their old
667 * locations. The CCSRBARH has a shadow register. When the CCSRBARH
668 * has a new value written it loads a CCSRBARH shadow register. When
669 * the CCSRBARL is written, the CCSRBARH shadow register contents
670 * along with the CCSRBARL value are loaded into the CCSRBARH and
671 * CCSRBARL registers, respectively. Follow this with a sync
675 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
676 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
677 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
678 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
680 ori r2, r2, CCSRAR_C@l
682 stw r0, 0(r9) /* Write to CCSRBARH */
683 sync /* Make sure we write to CCSRBARH first */
684 stw r1, 4(r9) /* Write to CCSRBARL */
688 * Write a 1 to the commit bit (C) of CCSRAR at the old location.
689 * Follow this with a sync instruction.
694 /* Delete the temporary LAW */
703 #else /* #ifdef CONFIG_FSL_CORENET */
707 * Read the current value of CCSRBAR using a load word instruction
708 * followed by an isync. This forces all accesses to configuration
715 /* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */
716 #define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \
717 (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12))
719 /* Write the new value to CCSRBAR. */
720 lis r0, CCSRBAR_PHYS_RS12@h
721 ori r0, r0, CCSRBAR_PHYS_RS12@l
726 * The manual says to perform a load of an address that does not
727 * access configuration space or the on-chip SRAM using an existing TLB,
728 * but that doesn't appear to be necessary. We will do the isync,
734 * Read the contents of CCSRBAR from its new location, followed by
740 #endif /* #ifdef CONFIG_FSL_CORENET */
742 /* Delete the temporary TLBs */
744 delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3
745 delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3
747 #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
749 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
752 * Create a TLB for the MMR location of CCSR
753 * to access L2CSR0 register
755 create_tlb0_entry 0, \
756 0, BOOKE_PAGESZ_4K, \
757 CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \
758 CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \
759 CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
761 enable_l2_cluster_l2:
762 /* enable L2 cache */
763 lis r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h
764 ori r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l
765 li r4, 33 /* stash id */
767 lis r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h
768 ori r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l
770 stw r4, 0(r3) /* invalidate L2 */
779 stw r4, 0(r3) /* eanble L2 */
781 delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
784 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
785 #define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
786 #define LAW_SIZE_1M 0x13
787 #define DCSRBAR_LAWAR (LAW_EN | (0x1d << 20) | LAW_SIZE_1M)
793 * Create a TLB entry for CCSR
795 * We're executing out of TLB1 entry in r14, and that's the only
796 * TLB entry that exists. To allocate some TLB entries for our
797 * own use, flip a bit high enough that we won't flip it again
802 lis r0, MAS0_TLBSEL(1)@h
803 rlwimi r0, r8, 16, MAS0_ESEL_MSK
804 lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@h
805 ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@l
806 lis r7, CONFIG_SYS_CCSRBAR@h
807 ori r7, r7, CONFIG_SYS_CCSRBAR@l
808 ori r2, r7, MAS2_I|MAS2_G
809 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
810 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
811 lis r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
812 ori r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
823 /* Map DCSR temporarily to physical address zero */
825 lis r3, DCSRBAR_LAWAR@h
826 ori r3, r3, DCSRBAR_LAWAR@l
828 stw r0, 0xc00(r7) /* LAWBARH0 */
829 stw r0, 0xc04(r7) /* LAWBARL0 */
831 stw r3, 0xc08(r7) /* LAWAR0 */
833 /* Read back from LAWAR to ensure the update is complete. */
834 lwz r3, 0xc08(r7) /* LAWAR0 */
837 /* Create a TLB entry for DCSR at zero */
840 lis r0, MAS0_TLBSEL(1)@h
841 rlwimi r0, r9, 16, MAS0_ESEL_MSK
842 lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h
843 ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l
844 li r6, 0 /* DCSR effective address */
845 ori r2, r6, MAS2_I|MAS2_G
846 li r3, MAS3_SW|MAS3_SR
858 /* enable the timebase */
859 #define CTBENR 0xe2084
861 addis r4, r7, CTBENR@ha
867 .macro erratum_set_ccsr offset value
868 addis r3, r7, \offset@ha
870 addi r3, r3, \offset@l
875 .macro erratum_set_dcsr offset value
876 addis r3, r6, \offset@ha
878 addi r3, r3, \offset@l
883 erratum_set_dcsr 0xb0e08 0xe0201800
884 erratum_set_dcsr 0xb0e18 0xe0201800
885 erratum_set_dcsr 0xb0e38 0xe0400000
886 erratum_set_dcsr 0xb0008 0x00900000
887 erratum_set_dcsr 0xb0e40 0xe00a0000
888 erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
889 erratum_set_ccsr 0x10f00 0x415e5000
890 erratum_set_ccsr 0x11f00 0x415e5000
892 /* Make temp mapping uncacheable again, if it was initially */
897 rlwimi r4, r15, 0, MAS2_I
898 rlwimi r4, r15, 0, MAS2_G
905 /* Clear the cache */
906 lis r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
907 ori r3,r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
917 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
918 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
928 /* Remove temporary mappings */
929 lis r0, MAS0_TLBSEL(1)@h
930 rlwimi r0, r9, 16, MAS0_ESEL_MSK
940 stw r3, 0xc08(r7) /* LAWAR0 */
944 lis r0, MAS0_TLBSEL(1)@h
945 rlwimi r0, r8, 16, MAS0_ESEL_MSK
956 /* r3 = addr, r4 = value, clobbers r5, r11, r12 */
958 /* Lock two cache lines into I-Cache */
960 mfspr r11, SPRN_L1CSR1
961 rlwinm r11, r11, 0, ~L1CSR1_ICUL
964 mtspr SPRN_L1CSR1, r11
975 mfspr r11, SPRN_L1CSR1
976 3: andi. r11, r11, L1CSR1_ICUL
983 mfspr r11, SPRN_L1CSR1
984 3: andi. r11, r11, L1CSR1_ICUL
989 /* Inside a locked cacheline, wait a while, write, then wait a while */
993 addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
994 4: mfspr r5, SPRN_TBRL
1001 addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
1002 4: mfspr r5, SPRN_TBRL
1009 * Fill out the rest of this cache line and the next with nops,
1010 * to ensure that nothing outside the locked area will be
1011 * fetched due to a branch.
1018 mfspr r11, SPRN_L1CSR1
1019 rlwinm r11, r11, 0, ~L1CSR1_ICUL
1022 mtspr SPRN_L1CSR1, r11
1031 create_init_ram_area:
1032 lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
1033 ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
1035 #if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
1036 /* create a temp mapping in AS=1 to the 4M boot window */
1037 create_tlb1_entry 15, \
1038 1, BOOKE_PAGESZ_4M, \
1039 CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
1040 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
1043 #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
1044 /* create a temp mapping in AS = 1 for Flash mapping
1045 * created by PBL for ISBC code
1047 create_tlb1_entry 15, \
1048 1, BOOKE_PAGESZ_1M, \
1049 CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
1050 CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
1054 * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
1055 * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage.
1057 create_tlb1_entry 15, \
1058 1, BOOKE_PAGESZ_1M, \
1059 CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
1060 CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \
1064 /* create a temp mapping in AS=1 to the stack */
1065 #if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
1066 defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
1067 create_tlb1_entry 14, \
1068 1, BOOKE_PAGESZ_16K, \
1069 CONFIG_SYS_INIT_RAM_ADDR, 0, \
1070 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \
1071 CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6
1074 create_tlb1_entry 14, \
1075 1, BOOKE_PAGESZ_16K, \
1076 CONFIG_SYS_INIT_RAM_ADDR, 0, \
1077 CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \
1081 lis r6,MSR_IS|MSR_DS|MSR_DE@h
1082 ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l
1084 ori r7,r7,switch_as@l
1091 /* L1 DCache is used for initial RAM */
1093 /* Allocate Initial RAM in data cache.
1095 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1096 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1099 /* cache size * 1024 / (2 * L1 line size) */
1100 slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
1106 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1109 /* Jump out the last 4K page and continue to 'normal' start */
1110 #ifdef CONFIG_SYS_RAMBOOT
1113 /* Calculate absolute address in FLASH and jump there */
1114 /*--------------------------------------------------------------*/
1115 lis r3,CONFIG_SYS_MONITOR_BASE@h
1116 ori r3,r3,CONFIG_SYS_MONITOR_BASE@l
1117 addi r3,r3,_start_cont - _start + _START_OFFSET
1125 .long 0x27051956 /* U-BOOT Magic Number */
1126 .globl version_string
1128 .ascii U_BOOT_VERSION_STRING, "\0"
1133 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
1134 lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
1135 ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
1137 stw r0,0(r3) /* Terminate Back Chain */
1138 stw r0,+4(r3) /* NULL return address. */
1139 mr r1,r3 /* Transfer to SP(r1) */
1144 /* switch back to AS = 0 */
1145 lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
1146 ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
1154 /* NOTREACHED - board_init_f() does not return */
1156 #ifndef CONFIG_NAND_SPL
1157 . = EXC_OFF_SYS_RESET
1158 .globl _start_of_vectors
1161 /* Critical input. */
1162 CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
1165 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
1167 /* Data Storage exception. */
1168 STD_EXCEPTION(0x0300, DataStorage, UnknownException)
1170 /* Instruction Storage exception. */
1171 STD_EXCEPTION(0x0400, InstStorage, UnknownException)
1173 /* External Interrupt exception. */
1174 STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
1176 /* Alignment exception. */
1179 EXCEPTION_PROLOG(SRR0, SRR1)
1184 addi r3,r1,STACK_FRAME_OVERHEAD
1185 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
1187 /* Program check exception */
1190 EXCEPTION_PROLOG(SRR0, SRR1)
1191 addi r3,r1,STACK_FRAME_OVERHEAD
1192 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
1193 MSR_KERNEL, COPY_EE)
1195 /* No FPU on MPC85xx. This exception is not supposed to happen.
1197 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
1201 * r0 - SYSCALL number
1205 addis r11,r0,0 /* get functions table addr */
1206 ori r11,r11,0 /* Note: this code is patched in trap_init */
1207 addis r12,r0,0 /* get number of functions */
1213 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
1217 li r20,0xd00-4 /* Get stack pointer */
1219 subi r12,r12,12 /* Adjust stack pointer */
1220 li r0,0xc00+_end_back-SystemCall
1221 cmplw 0,r0,r12 /* Check stack overflow */
1232 li r12,0xc00+_back-SystemCall
1240 mfmsr r11 /* Disable interrupts */
1244 SYNC /* Some chip revs need this... */
1248 li r12,0xd00-4 /* restore regs */
1258 addi r12,r12,12 /* Adjust stack pointer */
1266 STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
1267 STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
1268 STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
1270 STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
1271 STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
1273 CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
1275 .globl _end_of_vectors
1279 . = . + (0x100 - ( . & 0xff )) /* align for debug */
1282 * This code finishes saving the registers to the exception frame
1283 * and jumps to the appropriate handler for the exception.
1284 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1286 .globl transfer_to_handler
1287 transfer_to_handler:
1298 andi. r24,r23,0x3f00 /* get vector offset */
1302 mtspr SPRG2,r22 /* r1 is now kernel sp */
1304 lwz r24,0(r23) /* virtual address of handler */
1305 lwz r23,4(r23) /* where to go when done */
1310 rfi /* jump to handler, enable MMU */
1313 mfmsr r28 /* Disable interrupts */
1317 SYNC /* Some chip revs need this... */
1332 lwz r2,_NIP(r1) /* Restore environment */
1343 mfmsr r28 /* Disable interrupts */
1347 SYNC /* Some chip revs need this... */
1362 lwz r2,_NIP(r1) /* Restore environment */
1373 mfmsr r28 /* Disable interrupts */
1377 SYNC /* Some chip revs need this... */
1392 lwz r2,_NIP(r1) /* Restore environment */
1394 mtspr SPRN_MCSRR0,r2
1395 mtspr SPRN_MCSRR1,r0
1406 .globl invalidate_icache
1409 ori r0,r0,L1CSR1_ICFI
1414 blr /* entire I cache */
1416 .globl invalidate_dcache
1419 ori r0,r0,L1CSR0_DCFI
1426 .globl icache_enable
1429 bl invalidate_icache
1439 .globl icache_disable
1443 ori r3,r3,L1CSR1_ICE
1449 .globl icache_status
1452 andi. r3,r3,L1CSR1_ICE
1455 .globl dcache_enable
1458 bl invalidate_dcache
1470 .globl dcache_disable
1474 ori r4,r4,L1CSR0_DCE
1480 .globl dcache_status
1483 andi. r3,r3,L1CSR0_DCE
1506 /*------------------------------------------------------------------------------- */
1508 /* Description: Input 8 bits */
1509 /*------------------------------------------------------------------------------- */
1515 /*------------------------------------------------------------------------------- */
1516 /* Function: out8 */
1517 /* Description: Output 8 bits */
1518 /*------------------------------------------------------------------------------- */
1525 /*------------------------------------------------------------------------------- */
1526 /* Function: out16 */
1527 /* Description: Output 16 bits */
1528 /*------------------------------------------------------------------------------- */
1535 /*------------------------------------------------------------------------------- */
1536 /* Function: out16r */
1537 /* Description: Byte reverse and output 16 bits */
1538 /*------------------------------------------------------------------------------- */
1545 /*------------------------------------------------------------------------------- */
1546 /* Function: out32 */
1547 /* Description: Output 32 bits */
1548 /*------------------------------------------------------------------------------- */
1555 /*------------------------------------------------------------------------------- */
1556 /* Function: out32r */
1557 /* Description: Byte reverse and output 32 bits */
1558 /*------------------------------------------------------------------------------- */
1565 /*------------------------------------------------------------------------------- */
1566 /* Function: in16 */
1567 /* Description: Input 16 bits */
1568 /*------------------------------------------------------------------------------- */
1574 /*------------------------------------------------------------------------------- */
1575 /* Function: in16r */
1576 /* Description: Input 16 bits and byte reverse */
1577 /*------------------------------------------------------------------------------- */
1583 /*------------------------------------------------------------------------------- */
1584 /* Function: in32 */
1585 /* Description: Input 32 bits */
1586 /*------------------------------------------------------------------------------- */
1592 /*------------------------------------------------------------------------------- */
1593 /* Function: in32r */
1594 /* Description: Input 32 bits and byte reverse */
1595 /*------------------------------------------------------------------------------- */
1600 #endif /* !CONFIG_NAND_SPL */
1602 /*------------------------------------------------------------------------------*/
1605 * void write_tlb(mas0, mas1, mas2, mas3, mas7)
1613 #ifdef CONFIG_ENABLE_36BIT_PHYS
1617 #ifdef CONFIG_SYS_BOOK3E_HV
1627 * void relocate_code (addr_sp, gd, addr_moni)
1629 * This "function" does not return, instead it continues in RAM
1630 * after relocating the monitor code.
1634 * r5 = length in bytes
1635 * r6 = cachelinesize
1637 .globl relocate_code
1639 mr r1,r3 /* Set new stack pointer */
1640 mr r9,r4 /* Save copy of Init Data pointer */
1641 mr r10,r5 /* Save copy of Destination Address */
1644 mr r3,r5 /* Destination Address */
1645 lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1646 ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
1647 lwz r5,GOT(__init_end)
1649 li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
1654 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1660 /* First our own GOT */
1662 /* the the one used by the C code */
1672 beq cr1,4f /* In place copy is not necessary */
1673 beq 7f /* Protect against 0 count */
1692 * Now flush the cache: note that we must start from a cache aligned
1693 * address. Otherwise we might miss one cache line.
1697 beq 7f /* Always flush prefetch queue in any case */
1705 sync /* Wait for all dcbst to complete on bus */
1711 7: sync /* Wait for all icbi to complete on bus */
1715 * We are done. Do not return, instead branch to second part of board
1716 * initialization, now running from RAM.
1719 addi r0,r10,in_ram - _start + _START_OFFSET
1722 * As IVPR is going to point RAM address,
1723 * Make sure IVOR15 has valid opcode to support debugger
1728 * Re-point the IVPR at RAM
1733 blr /* NEVER RETURNS! */
1738 * Relocation Function, r12 point to got2+0x8000
1740 * Adjust got2 pointers, no need to check for 0, this code
1741 * already puts a few entries in the table.
1743 li r0,__got2_entries@sectoff@l
1744 la r3,GOT(_GOT2_TABLE_)
1745 lwz r11,GOT(_GOT2_TABLE_)
1757 * Now adjust the fixups and the pointers to the fixups
1758 * in case we need to move ourselves again.
1760 li r0,__fixup_entries@sectoff@l
1761 lwz r3,GOT(_FIXUP_TABLE_)
1777 * Now clear BSS segment
1779 lwz r3,GOT(__bss_start)
1780 lwz r4,GOT(__bss_end__)
1793 mr r3,r9 /* Init Data pointer */
1794 mr r4,r10 /* Destination Address */
1797 #ifndef CONFIG_NAND_SPL
1799 * Copy exception vector code to low memory
1802 * r7: source address, r8: end address, r9: target address
1806 mflr r4 /* save link register */
1808 lwz r7,GOT(_start_of_vectors)
1809 lwz r8,GOT(_end_of_vectors)
1811 li r9,0x100 /* reset vector always at 0x100 */
1814 bgelr /* return if r7>=r8 - just in case */
1824 * relocate `hdlr' and `int_return' entries
1826 li r7,.L_CriticalInput - _start + _START_OFFSET
1828 li r7,.L_MachineCheck - _start + _START_OFFSET
1830 li r7,.L_DataStorage - _start + _START_OFFSET
1832 li r7,.L_InstStorage - _start + _START_OFFSET
1834 li r7,.L_ExtInterrupt - _start + _START_OFFSET
1836 li r7,.L_Alignment - _start + _START_OFFSET
1838 li r7,.L_ProgramCheck - _start + _START_OFFSET
1840 li r7,.L_FPUnavailable - _start + _START_OFFSET
1842 li r7,.L_Decrementer - _start + _START_OFFSET
1844 li r7,.L_IntervalTimer - _start + _START_OFFSET
1845 li r8,_end_of_vectors - _start + _START_OFFSET
1848 addi r7,r7,0x100 /* next exception vector */
1852 /* Update IVORs as per relocated vector table address */
1854 mtspr IVOR0,r7 /* 0: Critical input */
1856 mtspr IVOR1,r7 /* 1: Machine check */
1858 mtspr IVOR2,r7 /* 2: Data storage */
1860 mtspr IVOR3,r7 /* 3: Instruction storage */
1862 mtspr IVOR4,r7 /* 4: External interrupt */
1864 mtspr IVOR5,r7 /* 5: Alignment */
1866 mtspr IVOR6,r7 /* 6: Program check */
1868 mtspr IVOR7,r7 /* 7: floating point unavailable */
1870 mtspr IVOR8,r7 /* 8: System call */
1871 /* 9: Auxiliary processor unavailable(unsupported) */
1873 mtspr IVOR10,r7 /* 10: Decrementer */
1875 mtspr IVOR11,r7 /* 11: Interval timer */
1877 mtspr IVOR12,r7 /* 12: Watchdog timer */
1879 mtspr IVOR13,r7 /* 13: Data TLB error */
1881 mtspr IVOR14,r7 /* 14: Instruction TLB error */
1883 mtspr IVOR15,r7 /* 15: Debug */
1888 mtlr r4 /* restore link register */
1891 .globl unlock_ram_in_cache
1892 unlock_ram_in_cache:
1893 /* invalidate the INIT_RAM section */
1894 lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
1895 ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
1898 slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
1901 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1905 /* Invalidate the TLB entries for the cache */
1906 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1907 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1920 mfspr r3,SPRN_L1CFG0
1922 rlwinm r5,r3,9,3 /* Extract cache block size */
1923 twlgti r5,1 /* Only 32 and 64 byte cache blocks
1924 * are currently defined.
1927 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
1928 * log2(number of ways)
1930 slw r5,r4,r5 /* r5 = cache block size */
1932 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
1933 mulli r7,r7,13 /* An 8-way cache will require 13
1938 /* save off HID0 and set DCFA */
1940 ori r9,r8,HID0_DCFA@l
1947 1: lwz r3,0(r4) /* Load... */
1955 1: dcbf 0,r4 /* ...and flush. */
1968 #include "fixed_ivor.S"
1970 #endif /* !CONFIG_NAND_SPL */