2 * Copyright 2004, 2007 Freescale Semiconductor.
3 * Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* U-Boot - Startup Code for 86xx PowerPC based Embedded Boards
27 * The processor starts at 0xfff00100 and the code is executed
28 * from flash. The code is organized to be at an other address
29 * in memory, but as long we don't jump around before relocating.
30 * board_init lies at a quite high address and when the cpu has
31 * jumped there, everything is ok.
35 #include <timestamp.h>
38 #include <ppc_asm.tmpl>
41 #include <asm/cache.h>
44 #ifndef CONFIG_IDENT_STRING
45 #define CONFIG_IDENT_STRING ""
49 * Need MSR_DR | MSR_IR enabled to access I/O (printf) in exceptions
53 * Set up GOT: Global Offset Table
55 * Use r12 to access the GOT
58 GOT_ENTRY(_GOT2_TABLE_)
59 GOT_ENTRY(_FIXUP_TABLE_)
62 GOT_ENTRY(_start_of_vectors)
63 GOT_ENTRY(_end_of_vectors)
64 GOT_ENTRY(transfer_to_handler)
68 GOT_ENTRY(__bss_start)
72 * r3 - 1st arg to board_init(): IMMP pointer
73 * r4 - 2nd arg to board_init(): boot flag
76 .long 0x27051956 /* U-Boot Magic Number */
80 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
81 .ascii CONFIG_IDENT_STRING, "\0"
88 /* the boot code is located below the exception table */
90 .globl _start_of_vectors
94 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
96 /* Data Storage exception. */
97 STD_EXCEPTION(0x300, DataStorage, UnknownException)
99 /* Instruction Storage exception. */
100 STD_EXCEPTION(0x400, InstStorage, UnknownException)
102 /* External Interrupt exception. */
103 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
105 /* Alignment exception. */
108 EXCEPTION_PROLOG(SRR0, SRR1)
113 addi r3,r1,STACK_FRAME_OVERHEAD
114 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
116 /* Program check exception */
119 EXCEPTION_PROLOG(SRR0, SRR1)
120 addi r3,r1,STACK_FRAME_OVERHEAD
121 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
124 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
126 /* I guess we could implement decrementer, and may have
127 * to someday for timekeeping.
129 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
130 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
131 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
132 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
133 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
134 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
135 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
136 STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
137 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
138 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
139 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
140 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
141 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
142 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
143 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
144 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
145 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
146 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
147 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
148 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
149 STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
150 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
151 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
153 .globl _end_of_vectors
160 * NOTE: Only Cpu 0 will ever come here. Other cores go to an
161 * address specified by the BPTR
164 #ifdef CONFIG_SYS_RAMBOOT
165 /* disable everything */
172 /* Invalidate BATs */
175 /* Invalidate all of TLB before MMU turn on */
180 /* init the L2 cache */
182 ori r3, r3, L2_INIT@l
184 /* invalidate the L2 cache */
185 bl l2cache_invalidate
190 * Calculate absolute address in FLASH and jump there
191 *------------------------------------------------------*/
192 lis r3, CONFIG_SYS_MONITOR_BASE_EARLY@h
193 ori r3, r3, CONFIG_SYS_MONITOR_BASE_EARLY@l
194 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
199 /* let the C-code set up the rest */
201 /* Be careful to keep code relocatable ! */
202 /*------------------------------------------------------*/
203 /* perform low-level init */
205 /* enable extended addressing */
212 * Cache must be enabled here for stack-in-cache trick.
213 * This means we need to enable the BATS.
214 * Cache should be turned on after BATs, since by default
215 * everything is write-through.
218 /* enable address translation */
220 ori r5, r5, (MSR_IR | MSR_DR)
221 lis r3,addr_trans_enabled@h
222 ori r3, r3, addr_trans_enabled@l
228 /* enable and invalidate the data cache */
229 /* bl l1dcache_enable */
237 #ifdef CONFIG_SYS_INIT_RAM_LOCK
242 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
246 /* set up the stack pointer in our newly created
248 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
249 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
251 li r0, 0 /* Make room for stack frame header and */
252 stwu r0, -4(r1) /* clear final stack frame so that */
253 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
255 GET_GOT /* initialize GOT access */
257 /* run low-level CPU init code (from Flash) */
263 /* Load PX_AUX register address in r4 */
266 /* Load contents of PX_AUX in r3 bits 24 to 31*/
269 /* Mask and obtain the bit in r3 */
270 rlwinm. r3, r3, 0, 24, 24
271 /* If not zero, jump and continue with u-boot */
274 /* Load back contents of PX_AUX in r3 bits 24 to 31 */
276 /* Set the MSB of the register value */
278 /* Write value in r3 back to PX_AUX */
281 /* Get the address to jump to in r3*/
282 lis r3, CONFIG_SYS_DIAG_ADDR@h
283 ori r3, r3, CONFIG_SYS_DIAG_ADDR@l
285 /* Load the LR with the branch address */
288 /* Branch to diagnostic */
294 /* bl l2cache_enable */
296 /* run 1st part of board init code (from Flash) */
300 /* NOTREACHED - board_init_f() does not return */
302 .globl invalidate_bats
306 /* invalidate BATs */
333 * Set up bats needed early on - this is usually the BAT for the
334 * stack-in-cache, the Flash, and CCSR space
339 lis r4, CONFIG_SYS_IBAT3L@h
340 ori r4, r4, CONFIG_SYS_IBAT3L@l
341 lis r3, CONFIG_SYS_IBAT3U@h
342 ori r3, r3, CONFIG_SYS_IBAT3U@l
348 lis r4, CONFIG_SYS_DBAT3L@h
349 ori r4, r4, CONFIG_SYS_DBAT3L@l
350 lis r3, CONFIG_SYS_DBAT3U@h
351 ori r3, r3, CONFIG_SYS_DBAT3U@l
357 lis r4, CONFIG_SYS_IBAT5L@h
358 ori r4, r4, CONFIG_SYS_IBAT5L@l
359 lis r3, CONFIG_SYS_IBAT5U@h
360 ori r3, r3, CONFIG_SYS_IBAT5U@l
366 lis r4, CONFIG_SYS_DBAT5L@h
367 ori r4, r4, CONFIG_SYS_DBAT5L@l
368 lis r3, CONFIG_SYS_DBAT5U@h
369 ori r3, r3, CONFIG_SYS_DBAT5U@l
375 lis r4, CONFIG_SYS_IBAT6L_EARLY@h
376 ori r4, r4, CONFIG_SYS_IBAT6L_EARLY@l
377 lis r3, CONFIG_SYS_IBAT6U_EARLY@h
378 ori r3, r3, CONFIG_SYS_IBAT6U_EARLY@l
384 lis r4, CONFIG_SYS_DBAT6L_EARLY@h
385 ori r4, r4, CONFIG_SYS_DBAT6L_EARLY@l
386 lis r3, CONFIG_SYS_DBAT6U_EARLY@h
387 ori r3, r3, CONFIG_SYS_DBAT6U_EARLY@l
392 #if(CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
394 lis r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@h
395 ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@l
396 lis r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@h
397 ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@l
403 lis r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@h
404 ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@l
405 lis r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@h
406 ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@l
426 .globl disable_addr_trans
428 /* disable address translation */
431 andi. r0, r3, (MSR_IR | MSR_DR)
439 * This code finishes saving the registers to the exception frame
440 * and jumps to the appropriate handler for the exception.
441 * Register r21 is pointer into trap frame, r1 has new stack pointer.
443 .globl transfer_to_handler
454 andi. r24,r23,0x3f00 /* get vector offset */
458 mtspr SPRG2,r22 /* r1 is now kernel sp */
459 lwz r24,0(r23) /* virtual address of handler */
460 lwz r23,4(r23) /* where to go when done */
465 rfi /* jump to handler, enable MMU */
468 mfmsr r28 /* Disable interrupts */
472 SYNC /* Some chip revs need this... */
487 lwz r2,_NIP(r1) /* Restore environment */
514 * Description: Input 8 bits
523 * Description: Output 8 bits
532 * Description: Output 16 bits
541 * Description: Byte reverse and output 16 bits
550 * Description: Output 32 bits
559 * Description: Byte reverse and output 32 bits
568 * Description: Input 16 bits
577 * Description: Input 16 bits and byte reverse
586 * Description: Input 32 bits
595 * Description: Input 32 bits and byte reverse
603 * void relocate_code (addr_sp, gd, addr_moni)
605 * This "function" does not return, instead it continues in RAM
606 * after relocating the monitor code.
610 * r5 = length in bytes
616 mr r1, r3 /* Set new stack pointer */
617 mr r9, r4 /* Save copy of Global Data pointer */
618 mr r10, r5 /* Save copy of Destination Address */
621 mr r3, r5 /* Destination Address */
622 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
623 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
624 lwz r5, GOT(__init_end)
626 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
631 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
637 /* First our own GOT */
639 /* then the one used by the C code */
648 beq cr1,4f /* In place copy is not necessary */
649 beq 7f /* Protect against 0 count */
667 * Now flush the cache: note that we must start from a cache aligned
668 * address. Otherwise we might miss one cache line.
672 beq 7f /* Always flush prefetch queue in any case */
680 sync /* Wait for all dcbst to complete on bus */
686 7: sync /* Wait for all icbi to complete on bus */
690 * We are done. Do not return, instead branch to second part of board
691 * initialization, now running from RAM.
693 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
699 * Relocation Function, r12 point to got2+0x8000
701 * Adjust got2 pointers, no need to check for 0, this code
702 * already puts a few entries in the table.
704 li r0,__got2_entries@sectoff@l
705 la r3,GOT(_GOT2_TABLE_)
706 lwz r11,GOT(_GOT2_TABLE_)
718 * Now adjust the fixups and the pointers to the fixups
719 * in case we need to move ourselves again.
721 li r0,__fixup_entries@sectoff@l
722 lwz r3,GOT(_FIXUP_TABLE_)
736 * Now clear BSS segment
738 lwz r3,GOT(__bss_start)
751 mr r3, r9 /* Init Date pointer */
752 mr r4, r10 /* Destination Address */
755 /* not reached - end relocate_code */
756 /*-----------------------------------------------------------------------*/
759 * Copy exception vector code to low memory
762 * r7: source address, r8: end address, r9: target address
766 mflr r4 /* save link register */
769 lwz r8, GOT(_end_of_vectors)
771 li r9, 0x100 /* reset vector always at 0x100 */
774 bgelr /* return if r7>=r8 - just in case */
784 * relocate `hdlr' and `int_return' entries
786 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
787 li r8, Alignment - _start + EXC_OFF_SYS_RESET
790 addi r7, r7, 0x100 /* next exception vector */
794 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
797 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
800 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
801 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
804 addi r7, r7, 0x100 /* next exception vector */
808 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
809 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
812 addi r7, r7, 0x100 /* next exception vector */
816 /* enable execptions from RAM vectors */
820 ori r7,r7,MSR_ME /* Enable Machine Check */
823 mtlr r4 /* restore link register */
826 .globl enable_ext_addr
829 lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
830 ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
836 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
839 /* Special sequence needed to update CCSRBAR itself */
840 lis r4, CONFIG_SYS_CCSRBAR_DEFAULT@h
841 ori r4, r4, CONFIG_SYS_CCSRBAR_DEFAULT@l
843 lis r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
844 ori r5, r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
846 li r6, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
848 stw r5, 0(r4) /* Store physical value of CCSR */
851 lis r5, CONFIG_SYS_TEXT_BASE@h
852 ori r5,r5,CONFIG_SYS_TEXT_BASE@l
856 /* Use VA of CCSR to do read */
857 lis r3, CONFIG_SYS_CCSRBAR@h
858 lwz r5, CONFIG_SYS_CCSRBAR@l(r3)
864 #ifdef CONFIG_SYS_INIT_RAM_LOCK
866 /* Allocate Initial RAM in data cache.
868 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
869 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
870 li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
871 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
878 /* Lock the data cache */
887 /* Lock the first way of the data cache */
890 #if defined(CONFIG_ALTIVEC)
900 .globl unlock_ram_in_cache
902 /* invalidate the INIT_RAM section */
903 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
904 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
905 li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
906 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
911 sync /* Wait for all icbi to complete on bus */
914 /* Unlock the data cache and invalidate it */
926 /* Unlock the first way of the data cache */
930 #ifdef CONFIG_ALTIVEC