arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c

   1 /*
   2  * Copyright 2008-2012 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  */
   9
  10 /*
  11  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
  12  * Based on code from spd_sdram.c
  13  * Author: James Yang [at freescale.com]
  14  */
  15
  16 #include <common.h>
  17 #include <asm/fsl_ddr_sdram.h>
  18
  19 #include "ddr.h"
  20
  21 #ifdef CONFIG_MPC83xx
  22         #define _DDR_ADDR CONFIG_SYS_MPC83xx_DDR_ADDR
  23 #elif defined(CONFIG_MPC85xx)
  24         #define _DDR_ADDR CONFIG_SYS_MPC85xx_DDR_ADDR
  25 #elif defined(CONFIG_MPC86xx)
  26         #define _DDR_ADDR CONFIG_SYS_MPC86xx_DDR_ADDR
  27 #else
  28         #error "Undefined _DDR_ADDR"
  29 #endif
  30
  31 u32 fsl_ddr_get_version(void)
  32 {
  33         ccsr_ddr_t *ddr;
  34         u32 ver_major_minor_errata;
  35
  36         ddr = (void *)_DDR_ADDR;
  37         ver_major_minor_errata = (in_be32(&ddr->ip_rev1) & 0xFFFF) << 8;
  38         ver_major_minor_errata |= (in_be32(&ddr->ip_rev2) & 0xFF00) >> 8;
  39
  40         return ver_major_minor_errata;
  41 }
  42
  43 unsigned int picos_to_mclk(unsigned int picos);
  44
  45 /*
  46  * Determine Rtt value.
  47  *
  48  * This should likely be either board or controller specific.
  49  *
  50  * Rtt(nominal) - DDR2:
  51  *      0 = Rtt disabled
  52  *      1 = 75 ohm
  53  *      2 = 150 ohm
  54  *      3 = 50 ohm
  55  * Rtt(nominal) - DDR3:
  56  *      0 = Rtt disabled
  57  *      1 = 60 ohm
  58  *      2 = 120 ohm
  59  *      3 = 40 ohm
  60  *      4 = 20 ohm
  61  *      5 = 30 ohm
  62  *
  63  * FIXME: Apparently 8641 needs a value of 2
  64  * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
  65  *
  66  * FIXME: There was some effort down this line earlier:
  67  *
  68  *      unsigned int i;
  69  *      for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
  70  *              if (popts->dimmslot[i].num_valid_cs
  71  *                  && (popts->cs_local_opts[2*i].odt_rd_cfg
  72  *                      || popts->cs_local_opts[2*i].odt_wr_cfg)) {
  73  *                      rtt = 2;
  74  *                      break;
  75  *              }
  76  *      }
  77  */
  78 static inline int fsl_ddr_get_rtt(void)
  79 {
  80         int rtt;
  81
  82 #if defined(CONFIG_FSL_DDR1)
  83         rtt = 0;
  84 #elif defined(CONFIG_FSL_DDR2)
  85         rtt = 3;
  86 #else
  87         rtt = 0;
  88 #endif
  89
  90         return rtt;
  91 }
  92
  93 /*
  94  * compute the CAS write latency according to DDR3 spec
  95  * CWL = 5 if tCK >= 2.5ns
  96  *       6 if 2.5ns > tCK >= 1.875ns
  97  *       7 if 1.875ns > tCK >= 1.5ns
  98  *       8 if 1.5ns > tCK >= 1.25ns
  99  *       9 if 1.25ns > tCK >= 1.07ns
 100  *       10 if 1.07ns > tCK >= 0.935ns
 101  *       11 if 0.935ns > tCK >= 0.833ns
 102  *       12 if 0.833ns > tCK >= 0.75ns
 103  */
 104 static inline unsigned int compute_cas_write_latency(void)
 105 {
 106         unsigned int cwl;
 107         const unsigned int mclk_ps = get_memory_clk_period_ps();
 108
 109         if (mclk_ps >= 2500)
 110                 cwl = 5;
 111         else if (mclk_ps >= 1875)
 112                 cwl = 6;
 113         else if (mclk_ps >= 1500)
 114                 cwl = 7;
 115         else if (mclk_ps >= 1250)
 116                 cwl = 8;
 117         else if (mclk_ps >= 1070)
 118                 cwl = 9;
 119         else if (mclk_ps >= 935)
 120                 cwl = 10;
 121         else if (mclk_ps >= 833)
 122                 cwl = 11;
 123         else if (mclk_ps >= 750)
 124                 cwl = 12;
 125         else {
 126                 cwl = 12;
 127                 printf("Warning: CWL is out of range\n");
 128         }
 129         return cwl;
 130 }
 131
 132 /* Chip Select Configuration (CSn_CONFIG) */
 133 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
 134                                const memctl_options_t *popts,
 135                                const dimm_params_t *dimm_params)
 136 {
 137         unsigned int cs_n_en = 0; /* Chip Select enable */
 138         unsigned int intlv_en = 0; /* Memory controller interleave enable */
 139         unsigned int intlv_ctl = 0; /* Interleaving control */
 140         unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
 141         unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
 142         unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
 143         unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
 144         unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
 145         unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
 146         int go_config = 0;
 147
 148         /* Compute CS_CONFIG only for existing ranks of each DIMM.  */
 149         switch (i) {
 150         case 0:
 151                 if (dimm_params[dimm_number].n_ranks > 0) {
 152                         go_config = 1;
 153                         /* These fields only available in CS0_CONFIG */
 154                         if (!popts->memctl_interleaving)
 155                                 break;
 156                         switch (popts->memctl_interleaving_mode) {
 157                         case FSL_DDR_CACHE_LINE_INTERLEAVING:
 158                         case FSL_DDR_PAGE_INTERLEAVING:
 159                         case FSL_DDR_BANK_INTERLEAVING:
 160                         case FSL_DDR_SUPERBANK_INTERLEAVING:
 161                                 intlv_en = popts->memctl_interleaving;
 162                                 intlv_ctl = popts->memctl_interleaving_mode;
 163                                 break;
 164                         default:
 165                                 break;
 166                         }
 167                 }
 168                 break;
 169         case 1:
 170                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
 171                     (dimm_number == 1 && dimm_params[1].n_ranks > 0))
 172                         go_config = 1;
 173                 break;
 174         case 2:
 175                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
 176                    (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
 177                         go_config = 1;
 178                 break;
 179         case 3:
 180                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
 181                     (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
 182                     (dimm_number == 3 && dimm_params[3].n_ranks > 0))
 183                         go_config = 1;
 184                 break;
 185         default:
 186                 break;
 187         }
 188         if (go_config) {
 189                 unsigned int n_banks_per_sdram_device;
 190                 cs_n_en = 1;
 191                 ap_n_en = popts->cs_local_opts[i].auto_precharge;
 192                 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
 193                 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
 194                 n_banks_per_sdram_device
 195                         = dimm_params[dimm_number].n_banks_per_sdram_device;
 196                 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
 197                 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
 198                 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
 199         }
 200         ddr->cs[i].config = (0
 201                 | ((cs_n_en & 0x1) << 31)
 202                 | ((intlv_en & 0x3) << 29)
 203                 | ((intlv_ctl & 0xf) << 24)
 204                 | ((ap_n_en & 0x1) << 23)
 205
 206                 /* XXX: some implementation only have 1 bit starting at left */
 207                 | ((odt_rd_cfg & 0x7) << 20)
 208
 209                 /* XXX: Some implementation only have 1 bit starting at left */
 210                 | ((odt_wr_cfg & 0x7) << 16)
 211
 212                 | ((ba_bits_cs_n & 0x3) << 14)
 213                 | ((row_bits_cs_n & 0x7) << 8)
 214                 | ((col_bits_cs_n & 0x7) << 0)
 215                 );
 216         debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
 217 }
 218
 219 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
 220 /* FIXME: 8572 */
 221 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
 222 {
 223         unsigned int pasr_cfg = 0;      /* Partial array self refresh config */
 224
 225         ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
 226         debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
 227 }
 228
 229 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
 230
 231 #if !defined(CONFIG_FSL_DDR1)
 232 /*
 233  * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
 234  *
 235  * Avoid writing for DDR I.  The new PQ38 DDR controller
 236  * dreams up non-zero default values to be backwards compatible.
 237  */
 238 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
 239                                 const memctl_options_t *popts)
 240 {
 241         unsigned char trwt_mclk = 0;   /* Read-to-write turnaround */
 242         unsigned char twrt_mclk = 0;   /* Write-to-read turnaround */
 243         /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
 244         unsigned char trrt_mclk = 0;   /* Read-to-read turnaround */
 245         unsigned char twwt_mclk = 0;   /* Write-to-write turnaround */
 246
 247         /* Active powerdown exit timing (tXARD and tXARDS). */
 248         unsigned char act_pd_exit_mclk;
 249         /* Precharge powerdown exit timing (tXP). */
 250         unsigned char pre_pd_exit_mclk;
 251         /* ODT powerdown exit timing (tAXPD). */
 252         unsigned char taxpd_mclk;
 253         /* Mode register set cycle time (tMRD). */
 254         unsigned char tmrd_mclk;
 255
 256 #ifdef CONFIG_FSL_DDR3
 257         /*
 258          * (tXARD and tXARDS). Empirical?
 259          * The DDR3 spec has not tXARD,
 260          * we use the tXP instead of it.
 261          * tXP=max(3nCK, 7.5ns) for DDR3.
 262          * spec has not the tAXPD, we use
 263          * tAXPD=1, need design to confirm.
 264          */
 265         int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
 266         unsigned int data_rate = get_ddr_freq(0);
 267         tmrd_mclk = 4;
 268         /* set the turnaround time */
 269         trwt_mclk = 1;
 270         if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
 271                 twrt_mclk = 1;
 272
 273         if (popts->dynamic_power == 0) {        /* powerdown is not used */
 274                 act_pd_exit_mclk = 1;
 275                 pre_pd_exit_mclk = 1;
 276                 taxpd_mclk = 1;
 277         } else {
 278                 /* act_pd_exit_mclk = tXARD, see above */
 279                 act_pd_exit_mclk = picos_to_mclk(tXP);
 280                 /* Mode register MR0[A12] is '1' - fast exit */
 281                 pre_pd_exit_mclk = act_pd_exit_mclk;
 282                 taxpd_mclk = 1;
 283         }
 284 #else /* CONFIG_FSL_DDR2 */
 285         /*
 286          * (tXARD and tXARDS). Empirical?
 287          * tXARD = 2 for DDR2
 288          * tXP=2
 289          * tAXPD=8
 290          */
 291         act_pd_exit_mclk = 2;
 292         pre_pd_exit_mclk = 2;
 293         taxpd_mclk = 8;
 294         tmrd_mclk = 2;
 295 #endif
 296
 297         if (popts->trwt_override)
 298                 trwt_mclk = popts->trwt;
 299
 300         ddr->timing_cfg_0 = (0
 301                 | ((trwt_mclk & 0x3) << 30)     /* RWT */
 302                 | ((twrt_mclk & 0x3) << 28)     /* WRT */
 303                 | ((trrt_mclk & 0x3) << 26)     /* RRT */
 304                 | ((twwt_mclk & 0x3) << 24)     /* WWT */
 305                 | ((act_pd_exit_mclk & 0x7) << 20)  /* ACT_PD_EXIT */
 306                 | ((pre_pd_exit_mclk & 0xF) << 16)  /* PRE_PD_EXIT */
 307                 | ((taxpd_mclk & 0xf) << 8)     /* ODT_PD_EXIT */
 308                 | ((tmrd_mclk & 0xf) << 0)      /* MRS_CYC */
 309                 );
 310         debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
 311 }
 312 #endif  /* defined(CONFIG_FSL_DDR2) */
 313
 314 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
 315 static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
 316                                const memctl_options_t *popts,
 317                                const common_timing_params_t *common_dimm,
 318                                unsigned int cas_latency)
 319 {
 320         /* Extended precharge to activate interval (tRP) */
 321         unsigned int ext_pretoact = 0;
 322         /* Extended Activate to precharge interval (tRAS) */
 323         unsigned int ext_acttopre = 0;
 324         /* Extended activate to read/write interval (tRCD) */
 325         unsigned int ext_acttorw = 0;
 326         /* Extended refresh recovery time (tRFC) */
 327         unsigned int ext_refrec;
 328         /* Extended MCAS latency from READ cmd */
 329         unsigned int ext_caslat = 0;
 330         /* Extended last data to precharge interval (tWR) */
 331         unsigned int ext_wrrec = 0;
 332         /* Control Adjust */
 333         unsigned int cntl_adj = 0;
 334
 335         ext_pretoact = picos_to_mclk(common_dimm->tRP_ps) >> 4;
 336         ext_acttopre = picos_to_mclk(common_dimm->tRAS_ps) >> 4;
 337         ext_acttorw = picos_to_mclk(common_dimm->tRCD_ps) >> 4;
 338         ext_caslat = (2 * cas_latency - 1) >> 4;
 339         ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
 340         /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
 341         ext_wrrec = (picos_to_mclk(common_dimm->tWR_ps) +
 342                 (popts->OTF_burst_chop_en ? 2 : 0)) >> 4;
 343
 344         ddr->timing_cfg_3 = (0
 345                 | ((ext_pretoact & 0x1) << 28)
 346                 | ((ext_acttopre & 0x2) << 24)
 347                 | ((ext_acttorw & 0x1) << 22)
 348                 | ((ext_refrec & 0x1F) << 16)
 349                 | ((ext_caslat & 0x3) << 12)
 350                 | ((ext_wrrec & 0x1) << 8)
 351                 | ((cntl_adj & 0x7) << 0)
 352                 );
 353         debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
 354 }
 355
 356 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
 357 static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
 358                                const memctl_options_t *popts,
 359                                const common_timing_params_t *common_dimm,
 360                                unsigned int cas_latency)
 361 {
 362         /* Precharge-to-activate interval (tRP) */
 363         unsigned char pretoact_mclk;
 364         /* Activate to precharge interval (tRAS) */
 365         unsigned char acttopre_mclk;
 366         /*  Activate to read/write interval (tRCD) */
 367         unsigned char acttorw_mclk;
 368         /* CASLAT */
 369         unsigned char caslat_ctrl;
 370         /*  Refresh recovery time (tRFC) ; trfc_low */
 371         unsigned char refrec_ctrl;
 372         /* Last data to precharge minimum interval (tWR) */
 373         unsigned char wrrec_mclk;
 374         /* Activate-to-activate interval (tRRD) */
 375         unsigned char acttoact_mclk;
 376         /* Last write data pair to read command issue interval (tWTR) */
 377         unsigned char wrtord_mclk;
 378         /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
 379         static const u8 wrrec_table[] = {
 380                 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
 381
 382         pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps);
 383         acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps);
 384         acttorw_mclk = picos_to_mclk(common_dimm->tRCD_ps);
 385
 386         /*
 387          * Translate CAS Latency to a DDR controller field value:
 388          *
 389          *      CAS Lat DDR I   DDR II  Ctrl
 390          *      Clocks  SPD Bit SPD Bit Value
 391          *      ------- ------- ------- -----
 392          *      1.0     0               0001
 393          *      1.5     1               0010
 394          *      2.0     2       2       0011
 395          *      2.5     3               0100
 396          *      3.0     4       3       0101
 397          *      3.5     5               0110
 398          *      4.0             4       0111
 399          *      4.5                     1000
 400          *      5.0             5       1001
 401          */
 402 #if defined(CONFIG_FSL_DDR1)
 403         caslat_ctrl = (cas_latency + 1) & 0x07;
 404 #elif defined(CONFIG_FSL_DDR2)
 405         caslat_ctrl = 2 * cas_latency - 1;
 406 #else
 407         /*
 408          * if the CAS latency more than 8 cycle,
 409          * we need set extend bit for it at
 410          * TIMING_CFG_3[EXT_CASLAT]
 411          */
 412         caslat_ctrl = 2 * cas_latency - 1;
 413 #endif
 414
 415         refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8;
 416         wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps);
 417
 418         if (wrrec_mclk > 16)
 419                 printf("Error: WRREC doesn't support more than 16 clocks\n");
 420         else
 421                 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
 422         if (popts->OTF_burst_chop_en)
 423                 wrrec_mclk += 2;
 424
 425         acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps);
 426         /*
 427          * JEDEC has min requirement for tRRD
 428          */
 429 #if defined(CONFIG_FSL_DDR3)
 430         if (acttoact_mclk < 4)
 431                 acttoact_mclk = 4;
 432 #endif
 433         wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps);
 434         /*
 435          * JEDEC has some min requirements for tWTR
 436          */
 437 #if defined(CONFIG_FSL_DDR2)
 438         if (wrtord_mclk < 2)
 439                 wrtord_mclk = 2;
 440 #elif defined(CONFIG_FSL_DDR3)
 441         if (wrtord_mclk < 4)
 442                 wrtord_mclk = 4;
 443 #endif
 444         if (popts->OTF_burst_chop_en)
 445                 wrtord_mclk += 2;
 446
 447         ddr->timing_cfg_1 = (0
 448                 | ((pretoact_mclk & 0x0F) << 28)
 449                 | ((acttopre_mclk & 0x0F) << 24)
 450                 | ((acttorw_mclk & 0xF) << 20)
 451                 | ((caslat_ctrl & 0xF) << 16)
 452                 | ((refrec_ctrl & 0xF) << 12)
 453                 | ((wrrec_mclk & 0x0F) << 8)
 454                 | ((acttoact_mclk & 0x0F) << 4)
 455                 | ((wrtord_mclk & 0x0F) << 0)
 456                 );
 457         debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
 458 }
 459
 460 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
 461 static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 462                                const memctl_options_t *popts,
 463                                const common_timing_params_t *common_dimm,
 464                                unsigned int cas_latency,
 465                                unsigned int additive_latency)
 466 {
 467         /* Additive latency */
 468         unsigned char add_lat_mclk;
 469         /* CAS-to-preamble override */
 470         unsigned short cpo;
 471         /* Write latency */
 472         unsigned char wr_lat;
 473         /*  Read to precharge (tRTP) */
 474         unsigned char rd_to_pre;
 475         /* Write command to write data strobe timing adjustment */
 476         unsigned char wr_data_delay;
 477         /* Minimum CKE pulse width (tCKE) */
 478         unsigned char cke_pls;
 479         /* Window for four activates (tFAW) */
 480         unsigned short four_act;
 481
 482         /* FIXME add check that this must be less than acttorw_mclk */
 483         add_lat_mclk = additive_latency;
 484         cpo = popts->cpo_override;
 485
 486 #if defined(CONFIG_FSL_DDR1)
 487         /*
 488          * This is a lie.  It should really be 1, but if it is
 489          * set to 1, bits overlap into the old controller's
 490          * otherwise unused ACSM field.  If we leave it 0, then
 491          * the HW will magically treat it as 1 for DDR 1.  Oh Yea.
 492          */
 493         wr_lat = 0;
 494 #elif defined(CONFIG_FSL_DDR2)
 495         wr_lat = cas_latency - 1;
 496 #else
 497         wr_lat = compute_cas_write_latency();
 498 #endif
 499
 500         rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps);
 501         /*
 502          * JEDEC has some min requirements for tRTP
 503          */
 504 #if defined(CONFIG_FSL_DDR2)
 505         if (rd_to_pre  < 2)
 506                 rd_to_pre  = 2;
 507 #elif defined(CONFIG_FSL_DDR3)
 508         if (rd_to_pre < 4)
 509                 rd_to_pre = 4;
 510 #endif
 511         if (additive_latency)
 512                 rd_to_pre += additive_latency;
 513         if (popts->OTF_burst_chop_en)
 514                 rd_to_pre += 2; /* according to UM */
 515
 516         wr_data_delay = popts->write_data_delay;
 517         cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
 518         four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
 519
 520         ddr->timing_cfg_2 = (0
 521                 | ((add_lat_mclk & 0xf) << 28)
 522                 | ((cpo & 0x1f) << 23)
 523                 | ((wr_lat & 0xf) << 19)
 524                 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
 525                 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
 526                 | ((cke_pls & 0x7) << 6)
 527                 | ((four_act & 0x3f) << 0)
 528                 );
 529         debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
 530 }
 531
 532 /* DDR SDRAM Register Control Word */
 533 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
 534                                const memctl_options_t *popts,
 535                                const common_timing_params_t *common_dimm)
 536 {
 537         if (common_dimm->all_DIMMs_registered
 538                 && !common_dimm->all_DIMMs_unbuffered) {
 539                 if (popts->rcw_override) {
 540                         ddr->ddr_sdram_rcw_1 = popts->rcw_1;
 541                         ddr->ddr_sdram_rcw_2 = popts->rcw_2;
 542                 } else {
 543                         ddr->ddr_sdram_rcw_1 =
 544                                 common_dimm->rcw[0] << 28 | \
 545                                 common_dimm->rcw[1] << 24 | \
 546                                 common_dimm->rcw[2] << 20 | \
 547                                 common_dimm->rcw[3] << 16 | \
 548                                 common_dimm->rcw[4] << 12 | \
 549                                 common_dimm->rcw[5] << 8 | \
 550                                 common_dimm->rcw[6] << 4 | \
 551                                 common_dimm->rcw[7];
 552                         ddr->ddr_sdram_rcw_2 =
 553                                 common_dimm->rcw[8] << 28 | \
 554                                 common_dimm->rcw[9] << 24 | \
 555                                 common_dimm->rcw[10] << 20 | \
 556                                 common_dimm->rcw[11] << 16 | \
 557                                 common_dimm->rcw[12] << 12 | \
 558                                 common_dimm->rcw[13] << 8 | \
 559                                 common_dimm->rcw[14] << 4 | \
 560                                 common_dimm->rcw[15];
 561                 }
 562                 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
 563                 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
 564         }
 565 }
 566
 567 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
 568 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 569                                const memctl_options_t *popts,
 570                                const common_timing_params_t *common_dimm)
 571 {
 572         unsigned int mem_en;            /* DDR SDRAM interface logic enable */
 573         unsigned int sren;              /* Self refresh enable (during sleep) */
 574         unsigned int ecc_en;            /* ECC enable. */
 575         unsigned int rd_en;             /* Registered DIMM enable */
 576         unsigned int sdram_type;        /* Type of SDRAM */
 577         unsigned int dyn_pwr;           /* Dynamic power management mode */
 578         unsigned int dbw;               /* DRAM dta bus width */
 579         unsigned int eight_be = 0;      /* 8-beat burst enable, DDR2 is zero */
 580         unsigned int ncap = 0;          /* Non-concurrent auto-precharge */
 581         unsigned int threeT_en;         /* Enable 3T timing */
 582         unsigned int twoT_en;           /* Enable 2T timing */
 583         unsigned int ba_intlv_ctl;      /* Bank (CS) interleaving control */
 584         unsigned int x32_en = 0;        /* x32 enable */
 585         unsigned int pchb8 = 0;         /* precharge bit 8 enable */
 586         unsigned int hse;               /* Global half strength override */
 587         unsigned int mem_halt = 0;      /* memory controller halt */
 588         unsigned int bi = 0;            /* Bypass initialization */
 589
 590         mem_en = 1;
 591         sren = popts->self_refresh_in_sleep;
 592         if (common_dimm->all_DIMMs_ECC_capable) {
 593                 /* Allow setting of ECC only if all DIMMs are ECC. */
 594                 ecc_en = popts->ECC_mode;
 595         } else {
 596                 ecc_en = 0;
 597         }
 598
 599         if (common_dimm->all_DIMMs_registered
 600                 && !common_dimm->all_DIMMs_unbuffered) {
 601                 rd_en = 1;
 602                 twoT_en = 0;
 603         } else {
 604                 rd_en = 0;
 605                 twoT_en = popts->twoT_en;
 606         }
 607
 608         sdram_type = CONFIG_FSL_SDRAM_TYPE;
 609
 610         dyn_pwr = popts->dynamic_power;
 611         dbw = popts->data_bus_width;
 612         /* 8-beat burst enable DDR-III case
 613          * we must clear it when use the on-the-fly mode,
 614          * must set it when use the 32-bits bus mode.
 615          */
 616         if (sdram_type == SDRAM_TYPE_DDR3) {
 617                 if (popts->burst_length == DDR_BL8)
 618                         eight_be = 1;
 619                 if (popts->burst_length == DDR_OTF)
 620                         eight_be = 0;
 621                 if (dbw == 0x1)
 622                         eight_be = 1;
 623         }
 624
 625         threeT_en = popts->threeT_en;
 626         ba_intlv_ctl = popts->ba_intlv_ctl;
 627         hse = popts->half_strength_driver_enable;
 628
 629         ddr->ddr_sdram_cfg = (0
 630                         | ((mem_en & 0x1) << 31)
 631                         | ((sren & 0x1) << 30)
 632                         | ((ecc_en & 0x1) << 29)
 633                         | ((rd_en & 0x1) << 28)
 634                         | ((sdram_type & 0x7) << 24)
 635                         | ((dyn_pwr & 0x1) << 21)
 636                         | ((dbw & 0x3) << 19)
 637                         | ((eight_be & 0x1) << 18)
 638                         | ((ncap & 0x1) << 17)
 639                         | ((threeT_en & 0x1) << 16)
 640                         | ((twoT_en & 0x1) << 15)
 641                         | ((ba_intlv_ctl & 0x7F) << 8)
 642                         | ((x32_en & 0x1) << 5)
 643                         | ((pchb8 & 0x1) << 4)
 644                         | ((hse & 0x1) << 3)
 645                         | ((mem_halt & 0x1) << 1)
 646                         | ((bi & 0x1) << 0)
 647                         );
 648         debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
 649 }
 650
 651 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
 652 static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 653                                const memctl_options_t *popts,
 654                                const unsigned int unq_mrs_en)
 655 {
 656         unsigned int frc_sr = 0;        /* Force self refresh */
 657         unsigned int sr_ie = 0;         /* Self-refresh interrupt enable */
 658         unsigned int dll_rst_dis;       /* DLL reset disable */
 659         unsigned int dqs_cfg;           /* DQS configuration */
 660         unsigned int odt_cfg = 0;       /* ODT configuration */
 661         unsigned int num_pr;            /* Number of posted refreshes */
 662         unsigned int slow = 0;          /* DDR will be run less than 1250 */
 663         unsigned int obc_cfg;           /* On-The-Fly Burst Chop Cfg */
 664         unsigned int ap_en;             /* Address Parity Enable */
 665         unsigned int d_init;            /* DRAM data initialization */
 666         unsigned int rcw_en = 0;        /* Register Control Word Enable */
 667         unsigned int md_en = 0;         /* Mirrored DIMM Enable */
 668         unsigned int qd_en = 0;         /* quad-rank DIMM Enable */
 669         int i;
 670
 671         dll_rst_dis = 1;        /* Make this configurable */
 672         dqs_cfg = popts->DQS_config;
 673         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 674                 if (popts->cs_local_opts[i].odt_rd_cfg
 675                         || popts->cs_local_opts[i].odt_wr_cfg) {
 676                         odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
 677                         break;
 678                 }
 679         }
 680
 681         num_pr = 1;     /* Make this configurable */
 682
 683         /*
 684          * 8572 manual says
 685          *     {TIMING_CFG_1[PRETOACT]
 686          *      + [DDR_SDRAM_CFG_2[NUM_PR]
 687          *        * ({EXT_REFREC || REFREC} + 8 + 2)]}
 688          *      << DDR_SDRAM_INTERVAL[REFINT]
 689          */
 690 #if defined(CONFIG_FSL_DDR3)
 691         obc_cfg = popts->OTF_burst_chop_en;
 692 #else
 693         obc_cfg = 0;
 694 #endif
 695
 696 #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
 697         slow = get_ddr_freq(0) < 1249000000;
 698 #endif
 699
 700         if (popts->registered_dimm_en) {
 701                 rcw_en = 1;
 702                 ap_en = popts->ap_en;
 703         } else {
 704                 ap_en = 0;
 705         }
 706
 707 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 708         /* Use the DDR controller to auto initialize memory. */
 709         d_init = popts->ECC_init_using_memctl;
 710         ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
 711         debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
 712 #else
 713         /* Memory will be initialized via DMA, or not at all. */
 714         d_init = 0;
 715 #endif
 716
 717 #if defined(CONFIG_FSL_DDR3)
 718         md_en = popts->mirrored_dimm;
 719 #endif
 720         qd_en = popts->quad_rank_present ? 1 : 0;
 721         ddr->ddr_sdram_cfg_2 = (0
 722                 | ((frc_sr & 0x1) << 31)
 723                 | ((sr_ie & 0x1) << 30)
 724                 | ((dll_rst_dis & 0x1) << 29)
 725                 | ((dqs_cfg & 0x3) << 26)
 726                 | ((odt_cfg & 0x3) << 21)
 727                 | ((num_pr & 0xf) << 12)
 728                 | ((slow & 1) << 11)
 729                 | (qd_en << 9)
 730                 | (unq_mrs_en << 8)
 731                 | ((obc_cfg & 0x1) << 6)
 732                 | ((ap_en & 0x1) << 5)
 733                 | ((d_init & 0x1) << 4)
 734                 | ((rcw_en & 0x1) << 2)
 735                 | ((md_en & 0x1) << 0)
 736                 );
 737         debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
 738 }
 739
 740 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
 741 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
 742                                 const memctl_options_t *popts,
 743                                 const unsigned int unq_mrs_en)
 744 {
 745         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
 746         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
 747
 748 #if defined(CONFIG_FSL_DDR3)
 749         int i;
 750         unsigned int rtt_wr = 0;        /* Rtt_WR - dynamic ODT off */
 751         unsigned int srt = 0;   /* self-refresh temerature, normal range */
 752         unsigned int asr = 0;   /* auto self-refresh disable */
 753         unsigned int cwl = compute_cas_write_latency() - 5;
 754         unsigned int pasr = 0;  /* partial array self refresh disable */
 755
 756         if (popts->rtt_override)
 757                 rtt_wr = popts->rtt_wr_override_value;
 758         else
 759                 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
 760         esdmode2 = (0
 761                 | ((rtt_wr & 0x3) << 9)
 762                 | ((srt & 0x1) << 7)
 763                 | ((asr & 0x1) << 6)
 764                 | ((cwl & 0x7) << 3)
 765                 | ((pasr & 0x7) << 0));
 766 #endif
 767         ddr->ddr_sdram_mode_2 = (0
 768                                  | ((esdmode2 & 0xFFFF) << 16)
 769                                  | ((esdmode3 & 0xFFFF) << 0)
 770                                  );
 771         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
 772
 773 #ifdef CONFIG_FSL_DDR3
 774         if (unq_mrs_en) {       /* unique mode registers are supported */
 775                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 776                         if (popts->rtt_override)
 777                                 rtt_wr = popts->rtt_wr_override_value;
 778                         else
 779                                 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
 780
 781                         esdmode2 &= 0xF9FF;     /* clear bit 10, 9 */
 782                         esdmode2 |= (rtt_wr & 0x3) << 9;
 783                         switch (i) {
 784                         case 1:
 785                                 ddr->ddr_sdram_mode_4 = (0
 786                                         | ((esdmode2 & 0xFFFF) << 16)
 787                                         | ((esdmode3 & 0xFFFF) << 0)
 788                                         );
 789                                 break;
 790                         case 2:
 791                                 ddr->ddr_sdram_mode_6 = (0
 792                                         | ((esdmode2 & 0xFFFF) << 16)
 793                                         | ((esdmode3 & 0xFFFF) << 0)
 794                                         );
 795                                 break;
 796                         case 3:
 797                                 ddr->ddr_sdram_mode_8 = (0
 798                                         | ((esdmode2 & 0xFFFF) << 16)
 799                                         | ((esdmode3 & 0xFFFF) << 0)
 800                                         );
 801                                 break;
 802                         }
 803                 }
 804                 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
 805                         ddr->ddr_sdram_mode_4);
 806                 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
 807                         ddr->ddr_sdram_mode_6);
 808                 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
 809                         ddr->ddr_sdram_mode_8);
 810         }
 811 #endif
 812 }
 813
 814 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
 815 static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
 816                                const memctl_options_t *popts,
 817                                const common_timing_params_t *common_dimm)
 818 {
 819         unsigned int refint;    /* Refresh interval */
 820         unsigned int bstopre;   /* Precharge interval */
 821
 822         refint = picos_to_mclk(common_dimm->refresh_rate_ps);
 823
 824         bstopre = popts->bstopre;
 825
 826         /* refint field used 0x3FFF in earlier controllers */
 827         ddr->ddr_sdram_interval = (0
 828                                    | ((refint & 0xFFFF) << 16)
 829                                    | ((bstopre & 0x3FFF) << 0)
 830                                    );
 831         debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
 832 }
 833
 834 #if defined(CONFIG_FSL_DDR3)
 835 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
 836 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 837                                const memctl_options_t *popts,
 838                                const common_timing_params_t *common_dimm,
 839                                unsigned int cas_latency,
 840                                unsigned int additive_latency,
 841                                const unsigned int unq_mrs_en)
 842 {
 843         unsigned short esdmode;         /* Extended SDRAM mode */
 844         unsigned short sdmode;          /* SDRAM mode */
 845
 846         /* Mode Register - MR1 */
 847         unsigned int qoff = 0;          /* Output buffer enable 0=yes, 1=no */
 848         unsigned int tdqs_en = 0;       /* TDQS Enable: 0=no, 1=yes */
 849         unsigned int rtt;
 850         unsigned int wrlvl_en = 0;      /* Write level enable: 0=no, 1=yes */
 851         unsigned int al = 0;            /* Posted CAS# additive latency (AL) */
 852         unsigned int dic = 0;           /* Output driver impedance, 40ohm */
 853         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
 854                                                        1=Disable (Test/Debug) */
 855
 856         /* Mode Register - MR0 */
 857         unsigned int dll_on;    /* DLL control for precharge PD, 0=off, 1=on */
 858         unsigned int wr = 0;    /* Write Recovery */
 859         unsigned int dll_rst;   /* DLL Reset */
 860         unsigned int mode;      /* Normal=0 or Test=1 */
 861         unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
 862         /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
 863         unsigned int bt;
 864         unsigned int bl;        /* BL: Burst Length */
 865
 866         unsigned int wr_mclk;
 867         /*
 868          * DDR_SDRAM_MODE doesn't support 9,11,13,15
 869          * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
 870          * for this table
 871          */
 872         static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
 873
 874         const unsigned int mclk_ps = get_memory_clk_period_ps();
 875         int i;
 876
 877         if (popts->rtt_override)
 878                 rtt = popts->rtt_override_value;
 879         else
 880                 rtt = popts->cs_local_opts[0].odt_rtt_norm;
 881
 882         if (additive_latency == (cas_latency - 1))
 883                 al = 1;
 884         if (additive_latency == (cas_latency - 2))
 885                 al = 2;
 886
 887         if (popts->quad_rank_present)
 888                 dic = 1;        /* output driver impedance 240/7 ohm */
 889
 890         /*
 891          * The esdmode value will also be used for writing
 892          * MR1 during write leveling for DDR3, although the
 893          * bits specifically related to the write leveling
 894          * scheme will be handled automatically by the DDR
 895          * controller. so we set the wrlvl_en = 0 here.
 896          */
 897         esdmode = (0
 898                 | ((qoff & 0x1) << 12)
 899                 | ((tdqs_en & 0x1) << 11)
 900                 | ((rtt & 0x4) << 7)   /* rtt field is split */
 901                 | ((wrlvl_en & 0x1) << 7)
 902                 | ((rtt & 0x2) << 5)   /* rtt field is split */
 903                 | ((dic & 0x2) << 4)   /* DIC field is split */
 904                 | ((al & 0x3) << 3)
 905                 | ((rtt & 0x1) << 2)  /* rtt field is split */
 906                 | ((dic & 0x1) << 1)   /* DIC field is split */
 907                 | ((dll_en & 0x1) << 0)
 908                 );
 909
 910         /*
 911          * DLL control for precharge PD
 912          * 0=slow exit DLL off (tXPDLL)
 913          * 1=fast exit DLL on (tXP)
 914          */
 915         dll_on = 1;
 916
 917         wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps;
 918         if (wr_mclk <= 16) {
 919                 wr = wr_table[wr_mclk - 5];
 920         } else {
 921                 printf("Error: unsupported write recovery for mode register "
 922                        "wr_mclk = %d\n", wr_mclk);
 923         }
 924
 925         dll_rst = 0;    /* dll no reset */
 926         mode = 0;       /* normal mode */
 927
 928         /* look up table to get the cas latency bits */
 929         if (cas_latency >= 5 && cas_latency <= 16) {
 930                 unsigned char cas_latency_table[] = {
 931                         0x2,    /* 5 clocks */
 932                         0x4,    /* 6 clocks */
 933                         0x6,    /* 7 clocks */
 934                         0x8,    /* 8 clocks */
 935                         0xa,    /* 9 clocks */
 936                         0xc,    /* 10 clocks */
 937                         0xe,    /* 11 clocks */
 938                         0x1,    /* 12 clocks */
 939                         0x3,    /* 13 clocks */
 940                         0x5,    /* 14 clocks */
 941                         0x7,    /* 15 clocks */
 942                         0x9,    /* 16 clocks */
 943                 };
 944                 caslat = cas_latency_table[cas_latency - 5];
 945         } else {
 946                 printf("Error: unsupported cas latency for mode register\n");
 947         }
 948
 949         bt = 0; /* Nibble sequential */
 950
 951         switch (popts->burst_length) {
 952         case DDR_BL8:
 953                 bl = 0;
 954                 break;
 955         case DDR_OTF:
 956                 bl = 1;
 957                 break;
 958         case DDR_BC4:
 959                 bl = 2;
 960                 break;
 961         default:
 962                 printf("Error: invalid burst length of %u specified. "
 963                         " Defaulting to on-the-fly BC4 or BL8 beats.\n",
 964                         popts->burst_length);
 965                 bl = 1;
 966                 break;
 967         }
 968
 969         sdmode = (0
 970                   | ((dll_on & 0x1) << 12)
 971                   | ((wr & 0x7) << 9)
 972                   | ((dll_rst & 0x1) << 8)
 973                   | ((mode & 0x1) << 7)
 974                   | (((caslat >> 1) & 0x7) << 4)
 975                   | ((bt & 0x1) << 3)
 976                   | ((caslat & 1) << 2)
 977                   | ((bl & 0x3) << 0)
 978                   );
 979
 980         ddr->ddr_sdram_mode = (0
 981                                | ((esdmode & 0xFFFF) << 16)
 982                                | ((sdmode & 0xFFFF) << 0)
 983                                );
 984
 985         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
 986
 987         if (unq_mrs_en) {       /* unique mode registers are supported */
 988                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 989                         if (popts->rtt_override)
 990                                 rtt = popts->rtt_override_value;
 991                         else
 992                                 rtt = popts->cs_local_opts[i].odt_rtt_norm;
 993
 994                         esdmode &= 0xFDBB;      /* clear bit 9,6,2 */
 995                         esdmode |= (0
 996                                 | ((rtt & 0x4) << 7)   /* rtt field is split */
 997                                 | ((rtt & 0x2) << 5)   /* rtt field is split */
 998                                 | ((rtt & 0x1) << 2)  /* rtt field is split */
 999                                 );
1000                         switch (i) {
1001                         case 1:
1002                                 ddr->ddr_sdram_mode_3 = (0
1003                                        | ((esdmode & 0xFFFF) << 16)
1004                                        | ((sdmode & 0xFFFF) << 0)
1005                                        );
1006                                 break;
1007                         case 2:
1008                                 ddr->ddr_sdram_mode_5 = (0
1009                                        | ((esdmode & 0xFFFF) << 16)
1010                                        | ((sdmode & 0xFFFF) << 0)
1011                                        );
1012                                 break;
1013                         case 3:
1014                                 ddr->ddr_sdram_mode_7 = (0
1015                                        | ((esdmode & 0xFFFF) << 16)
1016                                        | ((sdmode & 0xFFFF) << 0)
1017                                        );
1018                                 break;
1019                         }
1020                 }
1021                 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1022                         ddr->ddr_sdram_mode_3);
1023                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1024                         ddr->ddr_sdram_mode_5);
1025                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1026                         ddr->ddr_sdram_mode_5);
1027         }
1028 }
1029
1030 #else /* !CONFIG_FSL_DDR3 */
1031
1032 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1033 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
1034                                const memctl_options_t *popts,
1035                                const common_timing_params_t *common_dimm,
1036                                unsigned int cas_latency,
1037                                unsigned int additive_latency,
1038                                const unsigned int unq_mrs_en)
1039 {
1040         unsigned short esdmode;         /* Extended SDRAM mode */
1041         unsigned short sdmode;          /* SDRAM mode */
1042
1043         /*
1044          * FIXME: This ought to be pre-calculated in a
1045          * technology-specific routine,
1046          * e.g. compute_DDR2_mode_register(), and then the
1047          * sdmode and esdmode passed in as part of common_dimm.
1048          */
1049
1050         /* Extended Mode Register */
1051         unsigned int mrs = 0;           /* Mode Register Set */
1052         unsigned int outputs = 0;       /* 0=Enabled, 1=Disabled */
1053         unsigned int rdqs_en = 0;       /* RDQS Enable: 0=no, 1=yes */
1054         unsigned int dqs_en = 0;        /* DQS# Enable: 0=enable, 1=disable */
1055         unsigned int ocd = 0;           /* 0x0=OCD not supported,
1056                                            0x7=OCD default state */
1057         unsigned int rtt;
1058         unsigned int al;                /* Posted CAS# additive latency (AL) */
1059         unsigned int ods = 0;           /* Output Drive Strength:
1060                                                 0 = Full strength (18ohm)
1061                                                 1 = Reduced strength (4ohm) */
1062         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
1063                                                        1=Disable (Test/Debug) */
1064
1065         /* Mode Register (MR) */
1066         unsigned int mr;        /* Mode Register Definition */
1067         unsigned int pd;        /* Power-Down Mode */
1068         unsigned int wr;        /* Write Recovery */
1069         unsigned int dll_res;   /* DLL Reset */
1070         unsigned int mode;      /* Normal=0 or Test=1 */
1071         unsigned int caslat = 0;/* CAS# latency */
1072         /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1073         unsigned int bt;
1074         unsigned int bl;        /* BL: Burst Length */
1075
1076 #if defined(CONFIG_FSL_DDR2)
1077         const unsigned int mclk_ps = get_memory_clk_period_ps();
1078 #endif
1079         dqs_en = !popts->DQS_config;
1080         rtt = fsl_ddr_get_rtt();
1081
1082         al = additive_latency;
1083
1084         esdmode = (0
1085                 | ((mrs & 0x3) << 14)
1086                 | ((outputs & 0x1) << 12)
1087                 | ((rdqs_en & 0x1) << 11)
1088                 | ((dqs_en & 0x1) << 10)
1089                 | ((ocd & 0x7) << 7)
1090                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1091                 | ((al & 0x7) << 3)
1092                 | ((rtt & 0x1) << 2)   /* rtt field is split */
1093                 | ((ods & 0x1) << 1)
1094                 | ((dll_en & 0x1) << 0)
1095                 );
1096
1097         mr = 0;          /* FIXME: CHECKME */
1098
1099         /*
1100          * 0 = Fast Exit (Normal)
1101          * 1 = Slow Exit (Low Power)
1102          */
1103         pd = 0;
1104
1105 #if defined(CONFIG_FSL_DDR1)
1106         wr = 0;       /* Historical */
1107 #elif defined(CONFIG_FSL_DDR2)
1108         wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1;
1109 #endif
1110         dll_res = 0;
1111         mode = 0;
1112
1113 #if defined(CONFIG_FSL_DDR1)
1114         if (1 <= cas_latency && cas_latency <= 4) {
1115                 unsigned char mode_caslat_table[4] = {
1116                         0x5,    /* 1.5 clocks */
1117                         0x2,    /* 2.0 clocks */
1118                         0x6,    /* 2.5 clocks */
1119                         0x3     /* 3.0 clocks */
1120                 };
1121                 caslat = mode_caslat_table[cas_latency - 1];
1122         } else {
1123                 printf("Warning: unknown cas_latency %d\n", cas_latency);
1124         }
1125 #elif defined(CONFIG_FSL_DDR2)
1126         caslat = cas_latency;
1127 #endif
1128         bt = 0;
1129
1130         switch (popts->burst_length) {
1131         case DDR_BL4:
1132                 bl = 2;
1133                 break;
1134         case DDR_BL8:
1135                 bl = 3;
1136                 break;
1137         default:
1138                 printf("Error: invalid burst length of %u specified. "
1139                         " Defaulting to 4 beats.\n",
1140                         popts->burst_length);
1141                 bl = 2;
1142                 break;
1143         }
1144
1145         sdmode = (0
1146                   | ((mr & 0x3) << 14)
1147                   | ((pd & 0x1) << 12)
1148                   | ((wr & 0x7) << 9)
1149                   | ((dll_res & 0x1) << 8)
1150                   | ((mode & 0x1) << 7)
1151                   | ((caslat & 0x7) << 4)
1152                   | ((bt & 0x1) << 3)
1153                   | ((bl & 0x7) << 0)
1154                   );
1155
1156         ddr->ddr_sdram_mode = (0
1157                                | ((esdmode & 0xFFFF) << 16)
1158                                | ((sdmode & 0xFFFF) << 0)
1159                                );
1160         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1161 }
1162 #endif
1163
1164 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1165 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1166 {
1167         unsigned int init_value;        /* Initialization value */
1168
1169         init_value = 0xDEADBEEF;
1170         ddr->ddr_data_init = init_value;
1171 }
1172
1173 /*
1174  * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1175  * The old controller on the 8540/60 doesn't have this register.
1176  * Hope it's OK to set it (to 0) anyway.
1177  */
1178 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1179                                          const memctl_options_t *popts)
1180 {
1181         unsigned int clk_adjust;        /* Clock adjust */
1182
1183         clk_adjust = popts->clk_adjust;
1184         ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
1185         debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1186 }
1187
1188 /* DDR Initialization Address (DDR_INIT_ADDR) */
1189 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1190 {
1191         unsigned int init_addr = 0;     /* Initialization address */
1192
1193         ddr->ddr_init_addr = init_addr;
1194 }
1195
1196 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1197 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1198 {
1199         unsigned int uia = 0;   /* Use initialization address */
1200         unsigned int init_ext_addr = 0; /* Initialization address */
1201
1202         ddr->ddr_init_ext_addr = (0
1203                                   | ((uia & 0x1) << 31)
1204                                   | (init_ext_addr & 0xF)
1205                                   );
1206 }
1207
1208 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1209 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1210                                 const memctl_options_t *popts)
1211 {
1212         unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1213         unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1214         unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1215         unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1216         unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1217
1218 #if defined(CONFIG_FSL_DDR3)
1219         if (popts->burst_length == DDR_BL8) {
1220                 /* We set BL/2 for fixed BL8 */
1221                 rrt = 0;        /* BL/2 clocks */
1222                 wwt = 0;        /* BL/2 clocks */
1223         } else {
1224                 /* We need to set BL/2 + 2 to BC4 and OTF */
1225                 rrt = 2;        /* BL/2 + 2 clocks */
1226                 wwt = 2;        /* BL/2 + 2 clocks */
1227         }
1228         dll_lock = 1;   /* tDLLK = 512 clocks from spec */
1229 #endif
1230         ddr->timing_cfg_4 = (0
1231                              | ((rwt & 0xf) << 28)
1232                              | ((wrt & 0xf) << 24)
1233                              | ((rrt & 0xf) << 20)
1234                              | ((wwt & 0xf) << 16)
1235                              | (dll_lock & 0x3)
1236                              );
1237         debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1238 }
1239
1240 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1241 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1242 {
1243         unsigned int rodt_on = 0;       /* Read to ODT on */
1244         unsigned int rodt_off = 0;      /* Read to ODT off */
1245         unsigned int wodt_on = 0;       /* Write to ODT on */
1246         unsigned int wodt_off = 0;      /* Write to ODT off */
1247
1248 #if defined(CONFIG_FSL_DDR3)
1249         /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1250         rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1;
1251         rodt_off = 4;   /*  4 clocks */
1252         wodt_on = 1;    /*  1 clocks */
1253         wodt_off = 4;   /*  4 clocks */
1254 #endif
1255
1256         ddr->timing_cfg_5 = (0
1257                              | ((rodt_on & 0x1f) << 24)
1258                              | ((rodt_off & 0x7) << 20)
1259                              | ((wodt_on & 0x1f) << 12)
1260                              | ((wodt_off & 0x7) << 8)
1261                              );
1262         debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1263 }
1264
1265 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
1266 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
1267 {
1268         unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
1269         /* Normal Operation Full Calibration Time (tZQoper) */
1270         unsigned int zqoper = 0;
1271         /* Normal Operation Short Calibration Time (tZQCS) */
1272         unsigned int zqcs = 0;
1273
1274         if (zq_en) {
1275                 zqinit = 9;     /* 512 clocks */
1276                 zqoper = 8;     /* 256 clocks */
1277                 zqcs = 6;       /* 64 clocks */
1278         }
1279
1280         ddr->ddr_zq_cntl = (0
1281                             | ((zq_en & 0x1) << 31)
1282                             | ((zqinit & 0xF) << 24)
1283                             | ((zqoper & 0xF) << 16)
1284                             | ((zqcs & 0xF) << 8)
1285                             );
1286         debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
1287 }
1288
1289 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
1290 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
1291                                 const memctl_options_t *popts)
1292 {
1293         /*
1294          * First DQS pulse rising edge after margining mode
1295          * is programmed (tWL_MRD)
1296          */
1297         unsigned int wrlvl_mrd = 0;
1298         /* ODT delay after margining mode is programmed (tWL_ODTEN) */
1299         unsigned int wrlvl_odten = 0;
1300         /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
1301         unsigned int wrlvl_dqsen = 0;
1302         /* WRLVL_SMPL: Write leveling sample time */
1303         unsigned int wrlvl_smpl = 0;
1304         /* WRLVL_WLR: Write leveling repeition time */
1305         unsigned int wrlvl_wlr = 0;
1306         /* WRLVL_START: Write leveling start time */
1307         unsigned int wrlvl_start = 0;
1308
1309         /* suggest enable write leveling for DDR3 due to fly-by topology */
1310         if (wrlvl_en) {
1311                 /* tWL_MRD min = 40 nCK, we set it 64 */
1312                 wrlvl_mrd = 0x6;
1313                 /* tWL_ODTEN 128 */
1314                 wrlvl_odten = 0x7;
1315                 /* tWL_DQSEN min = 25 nCK, we set it 32 */
1316                 wrlvl_dqsen = 0x5;
1317                 /*
1318                  * Write leveling sample time at least need 6 clocks
1319                  * higher than tWLO to allow enough time for progagation
1320                  * delay and sampling the prime data bits.
1321                  */
1322                 wrlvl_smpl = 0xf;
1323                 /*
1324                  * Write leveling repetition time
1325                  * at least tWLO + 6 clocks clocks
1326                  * we set it 64
1327                  */
1328                 wrlvl_wlr = 0x6;
1329                 /*
1330                  * Write leveling start time
1331                  * The value use for the DQS_ADJUST for the first sample
1332                  * when write leveling is enabled. It probably needs to be
1333                  * overriden per platform.
1334                  */
1335                 wrlvl_start = 0x8;
1336                 /*
1337                  * Override the write leveling sample and start time
1338                  * according to specific board
1339                  */
1340                 if (popts->wrlvl_override) {
1341                         wrlvl_smpl = popts->wrlvl_sample;
1342                         wrlvl_start = popts->wrlvl_start;
1343                 }
1344         }
1345
1346         ddr->ddr_wrlvl_cntl = (0
1347                                | ((wrlvl_en & 0x1) << 31)
1348                                | ((wrlvl_mrd & 0x7) << 24)
1349                                | ((wrlvl_odten & 0x7) << 20)
1350                                | ((wrlvl_dqsen & 0x7) << 16)
1351                                | ((wrlvl_smpl & 0xf) << 12)
1352                                | ((wrlvl_wlr & 0x7) << 8)
1353                                | ((wrlvl_start & 0x1F) << 0)
1354                                );
1355         debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
1356         ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
1357         debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
1358         ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
1359         debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
1360
1361 }
1362
1363 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
1364 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
1365 {
1366         /* Self Refresh Idle Threshold */
1367         ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
1368 }
1369
1370 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1371 {
1372         if (popts->addr_hash) {
1373                 ddr->ddr_eor = 0x40000000;      /* address hash enable */
1374                 puts("Address hashing enabled.\n");
1375         }
1376 }
1377
1378 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1379 {
1380         ddr->ddr_cdr1 = popts->ddr_cdr1;
1381         debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
1382 }
1383
1384 static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1385 {
1386         ddr->ddr_cdr2 = popts->ddr_cdr2;
1387         debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
1388 }
1389
1390 unsigned int
1391 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
1392 {
1393         unsigned int res = 0;
1394
1395         /*
1396          * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
1397          * not set at the same time.
1398          */
1399         if (ddr->ddr_sdram_cfg & 0x10000000
1400             && ddr->ddr_sdram_cfg & 0x00008000) {
1401                 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
1402                                 " should not be set at the same time.\n");
1403                 res++;
1404         }
1405
1406         return res;
1407 }
1408
1409 unsigned int
1410 compute_fsl_memctl_config_regs(const memctl_options_t *popts,
1411                                fsl_ddr_cfg_regs_t *ddr,
1412                                const common_timing_params_t *common_dimm,
1413                                const dimm_params_t *dimm_params,
1414                                unsigned int dbw_cap_adj,
1415                                unsigned int size_only)
1416 {
1417         unsigned int i;
1418         unsigned int cas_latency;
1419         unsigned int additive_latency;
1420         unsigned int sr_it;
1421         unsigned int zq_en;
1422         unsigned int wrlvl_en;
1423         unsigned int ip_rev = 0;
1424         unsigned int unq_mrs_en = 0;
1425         int cs_en = 1;
1426
1427         memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
1428
1429         if (common_dimm == NULL) {
1430                 printf("Error: subset DIMM params struct null pointer\n");
1431                 return 1;
1432         }
1433
1434         /*
1435          * Process overrides first.
1436          *
1437          * FIXME: somehow add dereated caslat to this
1438          */
1439         cas_latency = (popts->cas_latency_override)
1440                 ? popts->cas_latency_override_value
1441                 : common_dimm->lowest_common_SPD_caslat;
1442
1443         additive_latency = (popts->additive_latency_override)
1444                 ? popts->additive_latency_override_value
1445                 : common_dimm->additive_latency;
1446
1447         sr_it = (popts->auto_self_refresh_en)
1448                 ? popts->sr_it
1449                 : 0;
1450         /* ZQ calibration */
1451         zq_en = (popts->zq_en) ? 1 : 0;
1452         /* write leveling */
1453         wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
1454
1455         /* Chip Select Memory Bounds (CSn_BNDS) */
1456         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1457                 unsigned long long ea, sa;
1458                 unsigned int cs_per_dimm
1459                         = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
1460                 unsigned int dimm_number
1461                         = i / cs_per_dimm;
1462                 unsigned long long rank_density
1463                         = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
1464
1465                 if (dimm_params[dimm_number].n_ranks == 0) {
1466                         debug("Skipping setup of CS%u "
1467                                 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
1468                         continue;
1469                 }
1470                 if (popts->memctl_interleaving) {
1471                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1472                         case FSL_DDR_CS0_CS1_CS2_CS3:
1473                                 break;
1474                         case FSL_DDR_CS0_CS1:
1475                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1476                                 if (i > 1)
1477                                         cs_en = 0;
1478                                 break;
1479                         case FSL_DDR_CS2_CS3:
1480                         default:
1481                                 if (i > 0)
1482                                         cs_en = 0;
1483                                 break;
1484                         }
1485                         sa = common_dimm->base_address;
1486                         ea = common_dimm->total_mem - 1;
1487                 } else if (!popts->memctl_interleaving) {
1488                         /*
1489                          * If memory interleaving between controllers is NOT
1490                          * enabled, the starting address for each memory
1491                          * controller is distinct.  However, because rank
1492                          * interleaving is enabled, the starting and ending
1493                          * addresses of the total memory on that memory
1494                          * controller needs to be programmed into its
1495                          * respective CS0_BNDS.
1496                          */
1497                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1498                         case FSL_DDR_CS0_CS1_CS2_CS3:
1499                                 sa = common_dimm->base_address;
1500                                 ea = common_dimm->total_mem - 1;
1501                                 break;
1502                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1503                                 if ((i >= 2) && (dimm_number == 0)) {
1504                                         sa = dimm_params[dimm_number].base_address +
1505                                               2 * rank_density;
1506                                         ea = sa + 2 * rank_density - 1;
1507                                 } else {
1508                                         sa = dimm_params[dimm_number].base_address;
1509                                         ea = sa + 2 * rank_density - 1;
1510                                 }
1511                                 break;
1512                         case FSL_DDR_CS0_CS1:
1513                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1514                                         sa = dimm_params[dimm_number].base_address;
1515                                         ea = sa + rank_density - 1;
1516                                         if (i != 1)
1517                                                 sa += (i % cs_per_dimm) * rank_density;
1518                                         ea += (i % cs_per_dimm) * rank_density;
1519                                 } else {
1520                                         sa = 0;
1521                                         ea = 0;
1522                                 }
1523                                 if (i == 0)
1524                                         ea += rank_density;
1525                                 break;
1526                         case FSL_DDR_CS2_CS3:
1527                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1528                                         sa = dimm_params[dimm_number].base_address;
1529                                         ea = sa + rank_density - 1;
1530                                         if (i != 3)
1531                                                 sa += (i % cs_per_dimm) * rank_density;
1532                                         ea += (i % cs_per_dimm) * rank_density;
1533                                 } else {
1534                                         sa = 0;
1535                                         ea = 0;
1536                                 }
1537                                 if (i == 2)
1538                                         ea += (rank_density >> dbw_cap_adj);
1539                                 break;
1540                         default:  /* No bank(chip-select) interleaving */
1541                                 sa = dimm_params[dimm_number].base_address;
1542                                 ea = sa + rank_density - 1;
1543                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1544                                         sa += (i % cs_per_dimm) * rank_density;
1545                                         ea += (i % cs_per_dimm) * rank_density;
1546                                 } else {
1547                                         sa = 0;
1548                                         ea = 0;
1549                                 }
1550                                 break;
1551                         }
1552                 }
1553
1554                 sa >>= 24;
1555                 ea >>= 24;
1556
1557                 ddr->cs[i].bnds = (0
1558                         | ((sa & 0xFFF) << 16)  /* starting address MSB */
1559                         | ((ea & 0xFFF) << 0)   /* ending address MSB */
1560                         );
1561
1562                 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
1563                 if (cs_en) {
1564                         set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1565                         set_csn_config_2(i, ddr);
1566                 } else
1567                         debug("CS%d is disabled.\n", i);
1568         }
1569
1570         /*
1571          * In the case we only need to compute the ddr sdram size, we only need
1572          * to set csn registers, so return from here.
1573          */
1574         if (size_only)
1575                 return 0;
1576
1577         set_ddr_eor(ddr, popts);
1578
1579 #if !defined(CONFIG_FSL_DDR1)
1580         set_timing_cfg_0(ddr, popts);
1581 #endif
1582
1583         set_timing_cfg_3(ddr, popts, common_dimm, cas_latency);
1584         set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
1585         set_timing_cfg_2(ddr, popts, common_dimm,
1586                                 cas_latency, additive_latency);
1587
1588         set_ddr_cdr1(ddr, popts);
1589         set_ddr_cdr2(ddr, popts);
1590         set_ddr_sdram_cfg(ddr, popts, common_dimm);
1591         ip_rev = fsl_ddr_get_version();
1592         if (ip_rev > 0x40400)
1593                 unq_mrs_en = 1;
1594
1595         set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
1596         set_ddr_sdram_mode(ddr, popts, common_dimm,
1597                                 cas_latency, additive_latency, unq_mrs_en);
1598         set_ddr_sdram_mode_2(ddr, popts, unq_mrs_en);
1599         set_ddr_sdram_interval(ddr, popts, common_dimm);
1600         set_ddr_data_init(ddr);
1601         set_ddr_sdram_clk_cntl(ddr, popts);
1602         set_ddr_init_addr(ddr);
1603         set_ddr_init_ext_addr(ddr);
1604         set_timing_cfg_4(ddr, popts);
1605         set_timing_cfg_5(ddr, cas_latency);
1606
1607         set_ddr_zq_cntl(ddr, zq_en);
1608         set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
1609
1610         set_ddr_sr_cntr(ddr, sr_it);
1611
1612         set_ddr_sdram_rcw(ddr, popts, common_dimm);
1613
1614         return check_fsl_memctl_config_regs(ddr);
1615 }