2 * Copyright 2008-2012 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
10 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
11 * Based on code from spd_sdram.c
12 * Author: James Yang [at freescale.com]
17 #include <asm/fsl_ddr_sdram.h>
18 #include <asm/fsl_law.h>
22 void fsl_ddr_set_lawbar(
23 const common_timing_params_t *memctl_common_params,
24 unsigned int memctl_interleaved,
25 unsigned int ctrl_num);
26 void fsl_ddr_set_intl3r(const unsigned int granule_size);
28 /* processor specific function */
29 extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
30 unsigned int ctrl_num);
32 #if defined(SPD_EEPROM_ADDRESS) || \
33 defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
34 defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
35 #if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
36 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
37 [0][0] = SPD_EEPROM_ADDRESS,
39 #elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
40 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
41 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
42 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
44 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
45 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
46 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
47 [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
49 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
50 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
51 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
52 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
53 [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
54 [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
56 #elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
57 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
58 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
59 [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
60 [2][0] = SPD_EEPROM_ADDRESS3, /* controller 3 */
62 #elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
63 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
64 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
65 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
66 [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
67 [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
68 [2][0] = SPD_EEPROM_ADDRESS5, /* controller 3 */
69 [2][1] = SPD_EEPROM_ADDRESS6, /* controller 3 */
74 static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
76 int ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
77 sizeof(generic_spd_eeprom_t));
81 #ifdef SPD_EEPROM_ADDRESS
83 #elif defined(SPD_EEPROM_ADDRESS1)
87 printf("DDR: failed to read SPD from address %u\n",
90 debug("DDR: failed to read SPD from address %u\n",
93 memset(spd, 0, sizeof(generic_spd_eeprom_t));
97 __attribute__((weak, alias("__get_spd")))
98 void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
100 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
101 unsigned int ctrl_num)
104 unsigned int i2c_address = 0;
106 if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) {
107 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
111 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
112 i2c_address = spd_i2c_addr[ctrl_num][i];
113 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
117 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
118 unsigned int ctrl_num)
121 #endif /* SPD_EEPROM_ADDRESSx */
125 * - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
126 * - Same memory data bus width on all controllers
130 * The memory controller and associated documentation use confusing
131 * terminology when referring to the orgranization of DRAM.
133 * Here is a terminology translation table:
135 * memory controller/documention |industry |this code |signals
136 * -------------------------------|-----------|-----------|-----------------
137 * physical bank/bank |rank |rank |chip select (CS)
138 * logical bank/sub-bank |bank |bank |bank address (BA)
139 * page/row |row |page |row address
140 * ??? |column |column |column address
142 * The naming confusion is further exacerbated by the descriptions of the
143 * memory controller interleaving feature, where accesses are interleaved
144 * _BETWEEN_ two seperate memory controllers. This is configured only in
145 * CS0_CONFIG[INTLV_CTL] of each memory controller.
147 * memory controller documentation | number of chip selects
148 * | per memory controller supported
149 * --------------------------------|-----------------------------------------
150 * cache line interleaving | 1 (CS0 only)
151 * page interleaving | 1 (CS0 only)
152 * bank interleaving | 1 (CS0 only)
153 * superbank interleraving | depends on bank (chip select)
154 * | interleraving [rank interleaving]
155 * | mode used on every memory controller
157 * Even further confusing is the existence of the interleaving feature
158 * _WITHIN_ each memory controller. The feature is referred to in
159 * documentation as chip select interleaving or bank interleaving,
160 * although it is configured in the DDR_SDRAM_CFG field.
162 * Name of field | documentation name | this code
163 * -----------------------------|-----------------------|------------------
164 * DDR_SDRAM_CFG[BA_INTLV_CTL] | Bank (chip select) | rank interleaving
168 const char *step_string_tbl[] = {
170 "STEP_COMPUTE_DIMM_PARMS",
171 "STEP_COMPUTE_COMMON_PARMS",
173 "STEP_ASSIGN_ADDRESSES",
179 const char * step_to_string(unsigned int step) {
181 unsigned int s = __ilog2(step);
183 if ((1 << s) != step)
184 return step_string_tbl[7];
186 return step_string_tbl[s];
189 static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
190 unsigned int dbw_cap_adj[])
193 unsigned long long total_mem, current_mem_base, total_ctlr_mem;
194 unsigned long long rank_density, ctlr_density = 0;
197 * If a reduced data width is requested, but the SPD
198 * specifies a physically wider device, adjust the
199 * computed dimm capacities accordingly before
200 * assigning addresses.
202 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
203 unsigned int found = 0;
205 switch (pinfo->memctl_opts[i].data_bus_width) {
208 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
210 if (!pinfo->dimm_params[i][j].n_ranks)
212 dw = pinfo->dimm_params[i][j].primary_sdram_width;
213 if ((dw == 72 || dw == 64)) {
216 } else if ((dw == 40 || dw == 32)) {
225 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
227 dw = pinfo->dimm_params[i][j].data_width;
228 if (pinfo->dimm_params[i][j].n_ranks
229 && (dw == 72 || dw == 64)) {
231 * FIXME: can't really do it
232 * like this because this just
233 * further reduces the memory
249 printf("unexpected data bus width "
250 "specified controller %u\n", i);
253 debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
256 current_mem_base = 0ull;
258 if (pinfo->memctl_opts[0].memctl_interleaving) {
259 rank_density = pinfo->dimm_params[0][0].rank_density >>
261 switch (pinfo->memctl_opts[0].ba_intlv_ctl &
262 FSL_DDR_CS0_CS1_CS2_CS3) {
263 case FSL_DDR_CS0_CS1_CS2_CS3:
264 ctlr_density = 4 * rank_density;
266 case FSL_DDR_CS0_CS1:
267 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
268 ctlr_density = 2 * rank_density;
270 case FSL_DDR_CS2_CS3:
272 ctlr_density = rank_density;
275 debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
276 rank_density, ctlr_density);
277 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
278 if (pinfo->memctl_opts[i].memctl_interleaving) {
279 switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
280 case FSL_DDR_CACHE_LINE_INTERLEAVING:
281 case FSL_DDR_PAGE_INTERLEAVING:
282 case FSL_DDR_BANK_INTERLEAVING:
283 case FSL_DDR_SUPERBANK_INTERLEAVING:
284 total_ctlr_mem = 2 * ctlr_density;
286 case FSL_DDR_3WAY_1KB_INTERLEAVING:
287 case FSL_DDR_3WAY_4KB_INTERLEAVING:
288 case FSL_DDR_3WAY_8KB_INTERLEAVING:
289 total_ctlr_mem = 3 * ctlr_density;
291 case FSL_DDR_4WAY_1KB_INTERLEAVING:
292 case FSL_DDR_4WAY_4KB_INTERLEAVING:
293 case FSL_DDR_4WAY_8KB_INTERLEAVING:
294 total_ctlr_mem = 4 * ctlr_density;
297 panic("Unknown interleaving mode");
299 pinfo->common_timing_params[i].base_address =
301 pinfo->common_timing_params[i].total_mem =
303 total_mem = current_mem_base + total_ctlr_mem;
304 debug("ctrl %d base 0x%llx\n", i, current_mem_base);
305 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
307 /* when 3rd controller not interleaved */
308 current_mem_base = total_mem;
310 pinfo->common_timing_params[i].base_address =
312 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
313 unsigned long long cap =
314 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
315 pinfo->dimm_params[i][j].base_address =
317 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
318 current_mem_base += cap;
319 total_ctlr_mem += cap;
321 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
322 pinfo->common_timing_params[i].total_mem =
324 total_mem += total_ctlr_mem;
329 * Simple linear assignment if memory
330 * controllers are not interleaved.
332 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
334 pinfo->common_timing_params[i].base_address =
336 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
337 /* Compute DIMM base addresses. */
338 unsigned long long cap =
339 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
340 pinfo->dimm_params[i][j].base_address =
342 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
343 current_mem_base += cap;
344 total_ctlr_mem += cap;
346 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
347 pinfo->common_timing_params[i].total_mem =
349 total_mem += total_ctlr_mem;
352 debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
357 /* Use weak function to allow board file to override the address assignment */
358 __attribute__((weak, alias("__step_assign_addresses")))
359 unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
360 unsigned int dbw_cap_adj[]);
363 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
364 unsigned int size_only)
367 unsigned long long total_mem = 0;
369 fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
370 common_timing_params_t *timing_params = pinfo->common_timing_params;
372 /* data bus width capacity adjust shift amount */
373 unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
375 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
376 dbw_capacity_adjust[i] = 0;
379 debug("starting at step %u (%s)\n",
380 start_step, step_to_string(start_step));
382 switch (start_step) {
384 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
385 /* STEP 1: Gather all DIMM SPD data */
386 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
387 fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i);
390 case STEP_COMPUTE_DIMM_PARMS:
391 /* STEP 2: Compute DIMM parameters from SPD data */
393 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
394 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
396 generic_spd_eeprom_t *spd =
397 &(pinfo->spd_installed_dimms[i][j]);
398 dimm_params_t *pdimm =
399 &(pinfo->dimm_params[i][j]);
401 retval = compute_dimm_parameters(spd, pdimm, i);
402 #ifdef CONFIG_SYS_DDR_RAW_TIMING
403 if (!i && !j && retval) {
404 printf("SPD error on controller %d! "
405 "Trying fallback to raw timing "
407 fsl_ddr_get_dimm_params(pdimm, i, j);
411 printf("Error: compute_dimm_parameters"
412 " non-zero returned FATAL value "
413 "for memctl=%u dimm=%u\n", i, j);
418 debug("Warning: compute_dimm_parameters"
419 " non-zero return value for memctl=%u "
425 #elif defined(CONFIG_SYS_DDR_RAW_TIMING)
426 case STEP_COMPUTE_DIMM_PARMS:
427 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
428 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
429 dimm_params_t *pdimm =
430 &(pinfo->dimm_params[i][j]);
431 fsl_ddr_get_dimm_params(pdimm, i, j);
434 debug("Filling dimm parameters from board specific file\n");
436 case STEP_COMPUTE_COMMON_PARMS:
438 * STEP 3: Compute a common set of timing parameters
439 * suitable for all of the DIMMs on each memory controller
441 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
442 debug("Computing lowest common DIMM"
443 " parameters for memctl=%u\n", i);
444 compute_lowest_common_dimm_parameters(
445 pinfo->dimm_params[i],
447 CONFIG_DIMM_SLOTS_PER_CTLR);
450 case STEP_GATHER_OPTS:
451 /* STEP 4: Gather configuration requirements from user */
452 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
453 debug("Reloading memory controller "
454 "configuration options for memctl=%u\n", i);
456 * This "reloads" the memory controller options
457 * to defaults. If the user "edits" an option,
458 * next_step points to the step after this,
459 * which is currently STEP_ASSIGN_ADDRESSES.
461 populate_memctl_options(
462 timing_params[i].all_DIMMs_registered,
463 &pinfo->memctl_opts[i],
464 pinfo->dimm_params[i], i);
466 case STEP_ASSIGN_ADDRESSES:
467 /* STEP 5: Assign addresses to chip selects */
468 check_interleaving_options(pinfo);
469 total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust);
471 case STEP_COMPUTE_REGS:
472 /* STEP 6: compute controller register values */
473 debug("FSL Memory ctrl register computation\n");
474 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
475 if (timing_params[i].ndimms_present == 0) {
476 memset(&ddr_reg[i], 0,
477 sizeof(fsl_ddr_cfg_regs_t));
481 compute_fsl_memctl_config_regs(
482 &pinfo->memctl_opts[i],
483 &ddr_reg[i], &timing_params[i],
484 pinfo->dimm_params[i],
485 dbw_capacity_adjust[i],
495 * Compute the amount of memory available just by
496 * looking for the highest valid CSn_BNDS value.
497 * This allows us to also experiment with using
498 * only CS0 when using dual-rank DIMMs.
500 unsigned int max_end = 0;
502 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
503 for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
504 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
505 if (reg->cs[j].config & 0x80000000) {
507 end = reg->cs[j].bnds & 0xFFF;
515 total_mem = 1 + (((unsigned long long)max_end << 24ULL)
523 * fsl_ddr_sdram() -- this is the main function to be called by
524 * initdram() in the board file.
526 * It returns amount of memory configured in bytes.
528 phys_size_t fsl_ddr_sdram(void)
531 unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
532 unsigned long long total_memory;
535 /* Reset info structure. */
536 memset(&info, 0, sizeof(fsl_ddr_info_t));
538 /* Compute it once normally. */
539 #ifdef CONFIG_FSL_DDR_INTERACTIVE
540 if (tstc() && (getc() == 'd')) { /* we got a key press of 'd' */
541 total_memory = fsl_ddr_interactive(&info, 0);
542 } else if (fsl_ddr_interactive_env_var_exists()) {
543 total_memory = fsl_ddr_interactive(&info, 1);
546 total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
548 /* setup 3-way interleaving before enabling DDRC */
549 if (info.memctl_opts[0].memctl_interleaving) {
550 switch (info.memctl_opts[0].memctl_interleaving_mode) {
551 case FSL_DDR_3WAY_1KB_INTERLEAVING:
552 case FSL_DDR_3WAY_4KB_INTERLEAVING:
553 case FSL_DDR_3WAY_8KB_INTERLEAVING:
555 info.memctl_opts[0].memctl_interleaving_mode);
562 /* Program configuration registers. */
563 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
564 debug("Programming controller %u\n", i);
565 if (info.common_timing_params[i].ndimms_present == 0) {
566 debug("No dimms present on controller %u; "
567 "skipping programming\n", i);
571 fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i);
575 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
576 if (info.memctl_opts[i].memctl_interleaving) {
577 switch (info.memctl_opts[i].memctl_interleaving_mode) {
578 case FSL_DDR_CACHE_LINE_INTERLEAVING:
579 case FSL_DDR_PAGE_INTERLEAVING:
580 case FSL_DDR_BANK_INTERLEAVING:
581 case FSL_DDR_SUPERBANK_INTERLEAVING:
583 law_memctl = LAW_TRGT_IF_DDR_INTRLV;
584 fsl_ddr_set_lawbar(&info.common_timing_params[i],
587 law_memctl = LAW_TRGT_IF_DDR_INTLV_34;
588 fsl_ddr_set_lawbar(&info.common_timing_params[i],
592 case FSL_DDR_3WAY_1KB_INTERLEAVING:
593 case FSL_DDR_3WAY_4KB_INTERLEAVING:
594 case FSL_DDR_3WAY_8KB_INTERLEAVING:
595 law_memctl = LAW_TRGT_IF_DDR_INTLV_123;
597 fsl_ddr_set_lawbar(&info.common_timing_params[i],
601 case FSL_DDR_4WAY_1KB_INTERLEAVING:
602 case FSL_DDR_4WAY_4KB_INTERLEAVING:
603 case FSL_DDR_4WAY_8KB_INTERLEAVING:
604 law_memctl = LAW_TRGT_IF_DDR_INTLV_1234;
606 fsl_ddr_set_lawbar(&info.common_timing_params[i],
608 /* place holder for future 4-way interleaving */
616 law_memctl = LAW_TRGT_IF_DDR_1;
619 law_memctl = LAW_TRGT_IF_DDR_2;
622 law_memctl = LAW_TRGT_IF_DDR_3;
625 law_memctl = LAW_TRGT_IF_DDR_4;
630 fsl_ddr_set_lawbar(&info.common_timing_params[i],
635 debug("total_memory by %s = %llu\n", __func__, total_memory);
637 #if !defined(CONFIG_PHYS_64BIT)
638 /* Check for 4G or more. Bad. */
639 if (total_memory >= (1ull << 32)) {
640 printf("Detected %lld MB of memory\n", total_memory >> 20);
641 printf(" This U-Boot only supports < 4G of DDR\n");
642 printf(" You could rebuild it with CONFIG_PHYS_64BIT\n");
643 printf(" "); /* re-align to match init_func_ram print */
644 total_memory = CONFIG_MAX_MEM_MAPPED;
652 * fsl_ddr_sdram_size() - This function only returns the size of the total
653 * memory without setting ddr control registers.
656 fsl_ddr_sdram_size(void)
659 unsigned long long total_memory = 0;
661 memset(&info, 0 , sizeof(fsl_ddr_info_t));
663 /* Compute it once normally. */
664 total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);