2 * Copyright 2008-2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
10 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
11 * Based on code from spd_sdram.c
12 * Author: James Yang [at freescale.com]
17 #include <asm/fsl_ddr_sdram.h>
21 extern void fsl_ddr_set_lawbar(
22 const common_timing_params_t *memctl_common_params,
23 unsigned int memctl_interleaved,
24 unsigned int ctrl_num);
26 /* processor specific function */
27 extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
28 unsigned int ctrl_num);
30 #if defined(SPD_EEPROM_ADDRESS) || \
31 defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
32 defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
33 #if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
34 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
35 [0][0] = SPD_EEPROM_ADDRESS,
37 #elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
38 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
39 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
40 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
42 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
43 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
44 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
45 [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
47 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
48 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
49 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
50 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
51 [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
52 [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
56 static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
58 int ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
59 sizeof(generic_spd_eeprom_t));
62 printf("DDR: failed to read SPD from address %u\n", i2c_address);
63 memset(spd, 0, sizeof(generic_spd_eeprom_t));
67 __attribute__((weak, alias("__get_spd")))
68 void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
70 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
71 unsigned int ctrl_num)
74 unsigned int i2c_address = 0;
76 if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) {
77 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
81 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
82 i2c_address = spd_i2c_addr[ctrl_num][i];
83 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
87 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
88 unsigned int ctrl_num)
91 #endif /* SPD_EEPROM_ADDRESSx */
95 * - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
96 * - Same memory data bus width on all controllers
100 * The memory controller and associated documentation use confusing
101 * terminology when referring to the orgranization of DRAM.
103 * Here is a terminology translation table:
105 * memory controller/documention |industry |this code |signals
106 * -------------------------------|-----------|-----------|-----------------
107 * physical bank/bank |rank |rank |chip select (CS)
108 * logical bank/sub-bank |bank |bank |bank address (BA)
109 * page/row |row |page |row address
110 * ??? |column |column |column address
112 * The naming confusion is further exacerbated by the descriptions of the
113 * memory controller interleaving feature, where accesses are interleaved
114 * _BETWEEN_ two seperate memory controllers. This is configured only in
115 * CS0_CONFIG[INTLV_CTL] of each memory controller.
117 * memory controller documentation | number of chip selects
118 * | per memory controller supported
119 * --------------------------------|-----------------------------------------
120 * cache line interleaving | 1 (CS0 only)
121 * page interleaving | 1 (CS0 only)
122 * bank interleaving | 1 (CS0 only)
123 * superbank interleraving | depends on bank (chip select)
124 * | interleraving [rank interleaving]
125 * | mode used on every memory controller
127 * Even further confusing is the existence of the interleaving feature
128 * _WITHIN_ each memory controller. The feature is referred to in
129 * documentation as chip select interleaving or bank interleaving,
130 * although it is configured in the DDR_SDRAM_CFG field.
132 * Name of field | documentation name | this code
133 * -----------------------------|-----------------------|------------------
134 * DDR_SDRAM_CFG[BA_INTLV_CTL] | Bank (chip select) | rank interleaving
139 const char *step_string_tbl[] = {
141 "STEP_COMPUTE_DIMM_PARMS",
142 "STEP_COMPUTE_COMMON_PARMS",
144 "STEP_ASSIGN_ADDRESSES",
150 const char * step_to_string(unsigned int step) {
152 unsigned int s = __ilog2(step);
154 if ((1 << s) != step)
155 return step_string_tbl[7];
157 return step_string_tbl[s];
161 int step_assign_addresses(fsl_ddr_info_t *pinfo,
162 unsigned int dbw_cap_adj[],
163 unsigned int *all_memctl_interleaving,
164 unsigned int *all_ctlr_rank_interleaving)
169 * If a reduced data width is requested, but the SPD
170 * specifies a physically wider device, adjust the
171 * computed dimm capacities accordingly before
172 * assigning addresses.
174 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
175 unsigned int found = 0;
177 switch (pinfo->memctl_opts[i].data_bus_width) {
180 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
182 if (!pinfo->dimm_params[i][j].n_ranks)
184 dw = pinfo->dimm_params[i][j].primary_sdram_width;
185 if ((dw == 72 || dw == 64)) {
188 } else if ((dw == 40 || dw == 32)) {
197 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
199 dw = pinfo->dimm_params[i][j].data_width;
200 if (pinfo->dimm_params[i][j].n_ranks
201 && (dw == 72 || dw == 64)) {
203 * FIXME: can't really do it
204 * like this because this just
205 * further reduces the memory
221 printf("unexpected data bus width "
222 "specified controller %u\n", i);
228 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
229 if (pinfo->memctl_opts[i].memctl_interleaving)
232 * Not support less than all memory controllers interleaving
233 * if more than two controllers
235 if (j == CONFIG_NUM_DDR_CONTROLLERS)
236 *all_memctl_interleaving = 1;
238 /* Check that all controllers are rank interleaving. */
240 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
241 if (pinfo->memctl_opts[i].ba_intlv_ctl)
244 * All memory controllers must be populated to qualify for
245 * all controller rank interleaving
247 if (j == CONFIG_NUM_DDR_CONTROLLERS)
248 *all_ctlr_rank_interleaving = 1;
250 if (*all_memctl_interleaving) {
251 unsigned long long addr, total_mem_per_ctlr = 0;
253 * If interleaving between memory controllers,
254 * make each controller start at a base address
257 * Also, if bank interleaving (chip select
258 * interleaving) is enabled on each memory
259 * controller, CS0 needs to be programmed to
260 * cover the entire memory range on that memory
263 * Bank interleaving also implies that each
264 * addressed chip select is identical in size.
267 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
269 pinfo->common_timing_params[i].base_address = 0ull;
270 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
271 unsigned long long cap
272 = pinfo->dimm_params[i][j].capacity;
274 pinfo->dimm_params[i][j].base_address = addr;
275 addr += cap >> dbw_cap_adj[i];
276 total_mem_per_ctlr += cap >> dbw_cap_adj[i];
279 pinfo->common_timing_params[0].total_mem = total_mem_per_ctlr;
282 * Simple linear assignment if memory
283 * controllers are not interleaved.
285 unsigned long long cur_memsize = 0;
286 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
287 u64 total_mem_per_ctlr = 0;
288 pinfo->common_timing_params[i].base_address =
290 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
291 /* Compute DIMM base addresses. */
292 unsigned long long cap =
293 pinfo->dimm_params[i][j].capacity;
294 pinfo->dimm_params[i][j].base_address =
296 cur_memsize += cap >> dbw_cap_adj[i];
297 total_mem_per_ctlr += cap >> dbw_cap_adj[i];
299 pinfo->common_timing_params[i].total_mem =
308 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
309 unsigned int size_only)
312 unsigned int all_controllers_memctl_interleaving = 0;
313 unsigned int all_controllers_rank_interleaving = 0;
314 unsigned long long total_mem = 0;
316 fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
317 common_timing_params_t *timing_params = pinfo->common_timing_params;
319 /* data bus width capacity adjust shift amount */
320 unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
322 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
323 dbw_capacity_adjust[i] = 0;
326 debug("starting at step %u (%s)\n",
327 start_step, step_to_string(start_step));
329 switch (start_step) {
331 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
332 /* STEP 1: Gather all DIMM SPD data */
333 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
334 fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i);
337 case STEP_COMPUTE_DIMM_PARMS:
338 /* STEP 2: Compute DIMM parameters from SPD data */
340 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
341 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
343 generic_spd_eeprom_t *spd =
344 &(pinfo->spd_installed_dimms[i][j]);
345 dimm_params_t *pdimm =
346 &(pinfo->dimm_params[i][j]);
348 retval = compute_dimm_parameters(spd, pdimm, i);
349 #ifdef CONFIG_SYS_DDR_RAW_TIMING
351 printf("SPD error! Trying fallback to "
352 "raw timing calculation\n");
353 fsl_ddr_get_dimm_params(pdimm, i, j);
357 printf("Error: compute_dimm_parameters"
358 " non-zero returned FATAL value "
359 "for memctl=%u dimm=%u\n", i, j);
364 debug("Warning: compute_dimm_parameters"
365 " non-zero return value for memctl=%u "
372 case STEP_COMPUTE_DIMM_PARMS:
373 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
374 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
375 dimm_params_t *pdimm =
376 &(pinfo->dimm_params[i][j]);
377 fsl_ddr_get_dimm_params(pdimm, i, j);
380 debug("Filling dimm parameters from board specific file\n");
382 case STEP_COMPUTE_COMMON_PARMS:
384 * STEP 3: Compute a common set of timing parameters
385 * suitable for all of the DIMMs on each memory controller
387 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
388 debug("Computing lowest common DIMM"
389 " parameters for memctl=%u\n", i);
390 compute_lowest_common_dimm_parameters(
391 pinfo->dimm_params[i],
393 CONFIG_DIMM_SLOTS_PER_CTLR);
396 case STEP_GATHER_OPTS:
397 /* STEP 4: Gather configuration requirements from user */
398 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
399 debug("Reloading memory controller "
400 "configuration options for memctl=%u\n", i);
402 * This "reloads" the memory controller options
403 * to defaults. If the user "edits" an option,
404 * next_step points to the step after this,
405 * which is currently STEP_ASSIGN_ADDRESSES.
407 populate_memctl_options(
408 timing_params[i].all_DIMMs_registered,
409 &pinfo->memctl_opts[i],
410 pinfo->dimm_params[i], i);
412 check_interleaving_options(pinfo);
413 case STEP_ASSIGN_ADDRESSES:
414 /* STEP 5: Assign addresses to chip selects */
415 step_assign_addresses(pinfo,
417 &all_controllers_memctl_interleaving,
418 &all_controllers_rank_interleaving);
420 case STEP_COMPUTE_REGS:
421 /* STEP 6: compute controller register values */
422 debug("FSL Memory ctrl cg register computation\n");
423 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
424 if (timing_params[i].ndimms_present == 0) {
425 memset(&ddr_reg[i], 0,
426 sizeof(fsl_ddr_cfg_regs_t));
430 compute_fsl_memctl_config_regs(
431 &pinfo->memctl_opts[i],
432 &ddr_reg[i], &timing_params[i],
433 pinfo->dimm_params[i],
434 dbw_capacity_adjust[i],
442 /* Compute the total amount of memory. */
445 * If bank interleaving but NOT memory controller interleaving
446 * CS_BNDS describe the quantity of memory on each memory
447 * controller, so the total is the sum across.
449 if (!all_controllers_memctl_interleaving
450 && all_controllers_rank_interleaving) {
452 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
453 total_mem += timing_params[i].total_mem;
458 * Compute the amount of memory available just by
459 * looking for the highest valid CSn_BNDS value.
460 * This allows us to also experiment with using
461 * only CS0 when using dual-rank DIMMs.
463 unsigned int max_end = 0;
465 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
466 for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
467 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
468 if (reg->cs[j].config & 0x80000000) {
470 end = reg->cs[j].bnds & 0xFFF;
478 total_mem = 1 + (((unsigned long long)max_end << 24ULL)
486 * fsl_ddr_sdram() -- this is the main function to be called by
487 * initdram() in the board file.
489 * It returns amount of memory configured in bytes.
491 phys_size_t fsl_ddr_sdram(void)
494 unsigned int memctl_interleaved;
495 unsigned long long total_memory;
498 /* Reset info structure. */
499 memset(&info, 0, sizeof(fsl_ddr_info_t));
501 /* Compute it once normally. */
502 total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
504 /* Check for memory controller interleaving. */
505 memctl_interleaved = 0;
506 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
507 memctl_interleaved +=
508 info.memctl_opts[i].memctl_interleaving;
511 if (memctl_interleaved) {
512 if (memctl_interleaved == CONFIG_NUM_DDR_CONTROLLERS) {
513 debug("memctl interleaving\n");
515 * Change the meaning of memctl_interleaved
518 memctl_interleaved = 1;
520 printf("Warning: memctl interleaving not "
521 "properly configured on all controllers\n");
522 memctl_interleaved = 0;
523 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
524 info.memctl_opts[i].memctl_interleaving = 0;
525 debug("Recomputing with memctl_interleaving off.\n");
526 total_memory = fsl_ddr_compute(&info,
527 STEP_ASSIGN_ADDRESSES,
532 /* Program configuration registers. */
533 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
534 debug("Programming controller %u\n", i);
535 if (info.common_timing_params[i].ndimms_present == 0) {
536 debug("No dimms present on controller %u; "
537 "skipping programming\n", i);
541 fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i);
544 if (memctl_interleaved) {
545 const unsigned int ctrl_num = 0;
547 /* Only set LAWBAR1 if memory controller interleaving is on. */
548 fsl_ddr_set_lawbar(&info.common_timing_params[0],
549 memctl_interleaved, ctrl_num);
552 * Memory controller interleaving is NOT on;
553 * set each lawbar individually.
555 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
556 fsl_ddr_set_lawbar(&info.common_timing_params[i],
561 debug("total_memory = %llu\n", total_memory);
563 #if !defined(CONFIG_PHYS_64BIT)
564 /* Check for 4G or more. Bad. */
565 if (total_memory >= (1ull << 32)) {
566 printf("Detected %lld MB of memory\n", total_memory >> 20);
567 printf(" This U-Boot only supports < 4G of DDR\n");
568 printf(" You could rebuild it with CONFIG_PHYS_64BIT\n");
569 printf(" "); /* re-align to match init_func_ram print */
570 total_memory = CONFIG_MAX_MEM_MAPPED;
578 * fsl_ddr_sdram_size() - This function only returns the size of the total
579 * memory without setting ddr control registers.
582 fsl_ddr_sdram_size(void)
585 unsigned long long total_memory = 0;
587 memset(&info, 0 , sizeof(fsl_ddr_info_t));
589 /* Compute it once normally. */
590 total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);