2 * Copyright 2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 #include <asm/fsl_law.h>
23 #include <asm/fsl_serdes.h>
24 #include <asm/fsl_srio.h>
25 #include <asm/errno.h>
27 #define SRIO_PORT_ACCEPT_ALL 0x10000001
28 #define SRIO_IB_ATMU_AR 0x80f55000
29 #define SRIO_OB_ATMU_AR_MAINT 0x80077000
30 #define SRIO_OB_ATMU_AR_RW 0x80045000
31 #define SRIO_LCSBA1CSR_OFFSET 0x5c
32 #define SRIO_MAINT_WIN_SIZE 0x1000000 /* 16M */
33 #define SRIO_RW_WIN_SIZE 0x100000 /* 1M */
34 #define SRIO_LCSBA1CSR 0x60000000
36 #if defined(CONFIG_FSL_CORENET)
37 #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1
38 #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2
39 #define _DEVDISR_RMU FSL_CORENET_DEVDISR_RMU
40 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
41 #elif defined(CONFIG_MPC85xx)
42 #define _DEVDISR_SRIO1 MPC85xx_DEVDISR_SRIO
43 #define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO
44 #define _DEVDISR_RMU MPC85xx_DEVDISR_RMSG
45 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
46 #elif defined(CONFIG_MPC86xx)
47 #define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO
48 #define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO
49 #define _DEVDISR_RMU MPC86xx_DEVDISR_RMSG
50 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \
51 (&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
53 #error "No defines for DEVDISR_SRIO"
56 #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
60 * Description: During port initialization, the SRIO port performs
61 * lane synchronization (detecting valid symbols on a lane) and
62 * lane alignment (coordinating multiple lanes to receive valid data
63 * across lanes). Internal errors in lane synchronization and lane
64 * alignment may cause failure to achieve link initialization at
65 * the configured port width.
66 * An SRIO port configured as a 4x port may see one of these scenarios:
67 * 1. One or more lanes fails to achieve lane synchronization. Depending
68 * on which lanes fail, this may result in downtraining from 4x to 1x
69 * on lane 0, 4x to 1x on lane R (redundant lane).
70 * 2. The link may fail to achieve lane alignment as a 4x, even though
71 * all 4 lanes achieve lane synchronization, and downtrain to a 1x.
72 * An SRIO port configured as a 1x port may fail to complete port
73 * initialization (PnESCSR[PU] never deasserts) because of scenario 1.
74 * Impact: SRIO port may downtrain to 1x, or may fail to complete
75 * link initialization. Once a port completes link initialization
76 * successfully, it will operate normally.
78 static int srio_erratum_a004034(u8 port)
80 serdes_corenet_t *srds_regs;
85 unsigned long long end_tick;
86 struct ccsr_rio *srio_regs = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
88 srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
89 conf_lane = (in_be32((void *)&srds_regs->srdspccr0)
90 >> (12 - port * 4)) & 0x3;
91 init_lane = (in_be32((void *)&srio_regs->lp_serial
92 .port[port].pccsr) >> 27) & 0x7;
95 * Start a counter set to ~2 ms after the SERDES reset is
96 * complete (SERDES SRDSBnRSTCTL[RST_DONE]=1 for n
97 * corresponding to the SERDES bank/PLL for the SRIO port).
99 if (in_be32((void *)&srds_regs->bank[0].rstctl)
100 & SRDS_RSTCTL_RSTDONE) {
102 * Poll the port uninitialized status (SRIO PnESCSR[PO]) until
103 * PO=1 or the counter expires. If the counter expires, the
104 * port has failed initialization: go to recover steps. If PO=1
105 * and the desired port width is 1x, go to normal steps. If
106 * PO = 1 and the desired port width is 4x, go to recover steps.
108 end_tick = usec2ticks(2000) + get_ticks();
110 if (in_be32((void *)&srio_regs->lp_serial
111 .port[port].pescsr) & 0x2) {
112 if (conf_lane == 0x1)
115 if (init_lane == 0x2)
121 } while (end_tick > get_ticks());
123 /* recover at most 3 times */
124 for (i = 0; i < 3; i++) {
125 /* Set SRIO PnCCSR[PD]=1 */
126 setbits_be32((void *)&srio_regs->lp_serial
130 * Set SRIO PnPCR[OBDEN] on the host to
131 * enable the discarding of any pending packets.
133 setbits_be32((void *)&srio_regs->impl.port[port].pcr,
137 /* Run sync command */
141 first = serdes_get_first_lane(SRIO2);
143 first = serdes_get_first_lane(SRIO1);
144 if (unlikely(first < 0))
146 if (conf_lane == 0x1)
151 * Set SERDES BnGCRm0[RRST]=0 for each SRIO
154 for (idx = first; idx <= last; idx++)
155 clrbits_be32(&srds_regs->lane[idx].gcr0,
158 * Read SERDES BnGCRm0 for each SRIO
161 for (idx = first; idx <= last; idx++)
162 in_be32(&srds_regs->lane[idx].gcr0);
163 /* Run sync command */
168 * Set SERDES BnGCRm0[RRST]=1 for each SRIO
171 for (idx = first; idx <= last; idx++)
172 setbits_be32(&srds_regs->lane[idx].gcr0,
175 * Read SERDES BnGCRm0 for each SRIO
178 for (idx = first; idx <= last; idx++)
179 in_be32(&srds_regs->lane[idx].gcr0);
180 /* Run sync command */
185 /* Write 1 to clear all bits in SRIO PnSLCSR */
186 out_be32((void *)&srio_regs->impl.port[port].slcsr,
188 /* Clear SRIO PnPCR[OBDEN] on the host */
189 clrbits_be32((void *)&srio_regs->impl.port[port].pcr,
191 /* Set SRIO PnCCSR[PD]=0 */
192 clrbits_be32((void *)&srio_regs->lp_serial
197 /* Poll the state of the port again */
199 (in_be32((void *)&srio_regs->lp_serial
200 .port[port].pccsr) >> 27) & 0x7;
201 if (in_be32((void *)&srio_regs->lp_serial
202 .port[port].pescsr) & 0x2) {
203 if (conf_lane == 0x1)
206 if (init_lane == 0x2)
217 /* Poll PnESCSR[OES] on the host until it is clear */
218 end_tick = usec2ticks(1000000) + get_ticks();
220 if (!(in_be32((void *)&srio_regs->lp_serial.port[port].pescsr)
222 out_be32(((void *)&srio_regs->lp_serial
223 .port[port].pescsr), 0xffffffff);
224 out_be32(((void *)&srio_regs->phys_err
225 .port[port].edcsr), 0);
226 out_be32(((void *)&srio_regs->logical_err.ltledcsr), 0);
229 } while (end_tick > get_ticks());
237 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
238 int srio1_used = 0, srio2_used = 0;
240 if (is_serdes_configured(SRIO1)) {
241 set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS,
242 law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE),
245 #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
246 if (srio_erratum_a004034(0) < 0)
247 printf("SRIO1: enabled but port error\n");
250 printf("SRIO1: enabled\n");
252 printf("SRIO1: disabled\n");
256 if (is_serdes_configured(SRIO2)) {
257 set_next_law(CONFIG_SYS_SRIO2_MEM_PHYS,
258 law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE),
261 #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
262 if (srio_erratum_a004034(1) < 0)
263 printf("SRIO2: enabled but port error\n");
266 printf("SRIO2: enabled\n");
269 printf("SRIO2: disabled\n");
273 #ifdef CONFIG_FSL_CORENET
274 /* On FSL_CORENET devices we can disable individual ports */
276 setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1);
278 setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2);
281 /* neither port is used - disable everything */
282 if (!srio1_used && !srio2_used) {
283 setbits_be32(&gur->devdisr, _DEVDISR_SRIO1);
284 setbits_be32(&gur->devdisr, _DEVDISR_SRIO2);
285 setbits_be32(&gur->devdisr, _DEVDISR_RMU);
289 #ifdef CONFIG_FSL_CORENET
290 void srio_boot_master(int port)
292 struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
294 /* set port accept-all */
295 out_be32((void *)&srio->impl.port[port - 1].ptaacr,
296 SRIO_PORT_ACCEPT_ALL);
298 debug("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n", port);
299 /* configure inbound window for slave's u-boot image */
300 debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
301 "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
302 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
303 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
304 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
305 out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwtar,
306 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
307 out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwbar,
308 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 >> 12);
309 out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwar,
311 | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE));
313 /* configure inbound window for slave's u-boot image */
314 debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
315 "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
316 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
317 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
318 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
319 out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwtar,
320 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
321 out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwbar,
322 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 >> 12);
323 out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwar,
325 | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE));
327 /* configure inbound window for slave's ucode and ENV */
328 debug("SRIOBOOT - MASTER: Inbound window for slave's ucode and ENV; "
329 "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
330 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
331 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
332 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
333 out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwtar,
334 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS >> 12);
335 out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwbar,
336 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS >> 12);
337 out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwar,
339 | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE));
342 void srio_boot_master_release_slave(int port)
344 struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
346 debug("SRIOBOOT - MASTER: "
347 "Check the port status and release slave core ...\n");
349 escsr = in_be32((void *)&srio->lp_serial.port[port - 1].pescsr);
351 if (escsr & 0x10100) {
352 debug("SRIOBOOT - MASTER: Port [ %d ] is error.\n",
355 debug("SRIOBOOT - MASTER: "
356 "Port [ %d ] is ready, now release slave's core ...\n",
359 * configure outbound window
360 * with maintenance attribute to set slave's LCSBA1CSR
362 out_be32((void *)&srio->atmu.port[port - 1]
363 .outbw[1].rowtar, 0);
364 out_be32((void *)&srio->atmu.port[port - 1]
365 .outbw[1].rowtear, 0);
367 out_be32((void *)&srio->atmu.port[port - 1]
369 CONFIG_SYS_SRIO2_MEM_PHYS >> 12);
371 out_be32((void *)&srio->atmu.port[port - 1]
373 CONFIG_SYS_SRIO1_MEM_PHYS >> 12);
374 out_be32((void *)&srio->atmu.port[port - 1]
376 SRIO_OB_ATMU_AR_MAINT
377 | atmu_size_mask(SRIO_MAINT_WIN_SIZE));
380 * configure outbound window
381 * with R/W attribute to set slave's BRR
383 out_be32((void *)&srio->atmu.port[port - 1]
385 SRIO_LCSBA1CSR >> 9);
386 out_be32((void *)&srio->atmu.port[port - 1]
387 .outbw[2].rowtear, 0);
389 out_be32((void *)&srio->atmu.port[port - 1]
391 (CONFIG_SYS_SRIO2_MEM_PHYS
392 + SRIO_MAINT_WIN_SIZE) >> 12);
394 out_be32((void *)&srio->atmu.port[port - 1]
396 (CONFIG_SYS_SRIO1_MEM_PHYS
397 + SRIO_MAINT_WIN_SIZE) >> 12);
398 out_be32((void *)&srio->atmu.port[port - 1]
401 | atmu_size_mask(SRIO_RW_WIN_SIZE));
404 * Set the LCSBA1CSR register in slave
405 * by the maint-outbound window
408 out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
409 + SRIO_LCSBA1CSR_OFFSET,
411 while (in_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
412 + SRIO_LCSBA1CSR_OFFSET)
416 * And then set the BRR register
417 * to release slave core
419 out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
420 + SRIO_MAINT_WIN_SIZE
421 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET,
422 CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
424 out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
425 + SRIO_LCSBA1CSR_OFFSET,
427 while (in_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
428 + SRIO_LCSBA1CSR_OFFSET)
432 * And then set the BRR register
433 * to release slave core
435 out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
436 + SRIO_MAINT_WIN_SIZE
437 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET,
438 CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
440 debug("SRIOBOOT - MASTER: "
441 "Release slave successfully! Now the slave should start up!\n");
444 debug("SRIOBOOT - MASTER: Port [ %d ] is not ready.\n", port);