2 * (C) Copyright 2000-2007
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
11 * written or collected and sometimes rewritten by
12 * Magnus Damm <damm@bitsmart.com>
14 * minor modifications by
15 * Wolfgang Denk <wd@denx.de>
21 #include <asm/cache.h>
22 #include <asm/ppc4xx.h>
25 DECLARE_GLOBAL_DATA_PTR;
27 void board_reset(void);
30 * To provide an interface to detect CPU number for boards that support
31 * more then one CPU, we implement the "weak" default functions here.
35 int __get_cpu_num(void)
37 return NA_OR_UNKNOWN_CPU;
39 int get_cpu_num(void) __attribute__((weak, alias("__get_cpu_num")));
41 #if defined(CONFIG_PCI)
42 #if defined(CONFIG_405GP) || \
43 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
44 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
48 static int pci_async_enabled(void)
50 #if defined(CONFIG_405GP)
51 return (mfdcr(CPC0_PSR) & PSR_PCI_ASYNC_EN);
54 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
55 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
56 defined(CONFIG_460EX) || defined(CONFIG_460GT)
59 mfsdr(SDR0_SDSTP1, val);
60 return (val & SDR0_SDSTP1_PAME_MASK);
64 #endif /* CONFIG_PCI */
66 #if defined(CONFIG_PCI) && \
67 !defined(CONFIG_405) && !defined(CONFIG_405EX)
68 int pci_arbiter_enabled(void)
70 #if defined(CONFIG_405GP)
71 return (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN);
74 #if defined(CONFIG_405EP)
75 return (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN);
78 #if defined(CONFIG_440GP)
79 return (mfdcr(CPC0_STRP1) & CPC0_STRP1_PAE_MASK);
82 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
85 mfsdr(SDR0_XCR0, val);
86 return (val & SDR0_XCR0_PAE_MASK);
88 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
89 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
90 defined(CONFIG_460EX) || defined(CONFIG_460GT)
93 mfsdr(SDR0_PCI0, val);
94 return (val & SDR0_PCI0_PAE_MASK);
99 #if defined(CONFIG_405EP)
102 static int i2c_bootrom_enabled(void)
104 #if defined(CONFIG_405EP)
105 return (mfdcr(CPC0_BOOT) & CPC0_BOOT_SEP);
109 mfsdr(SDR0_SDCS0, val);
110 return (val & SDR0_SDCS_SDD);
115 #if defined(CONFIG_440GX)
116 #define SDR0_PINSTP_SHIFT 29
117 static char *bootstrap_str[] = {
127 static char bootstrap_char[] = { 'A', 'B', 'C', 'B', 'D', 'E', 'x', 'F' };
130 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
131 #define SDR0_PINSTP_SHIFT 30
132 static char *bootstrap_str[] = {
138 static char bootstrap_char[] = { 'A', 'B', 'C', 'D'};
141 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
142 #define SDR0_PINSTP_SHIFT 29
143 static char *bootstrap_str[] = {
153 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
156 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
157 #define SDR0_PINSTP_SHIFT 29
158 static char *bootstrap_str[] = {
168 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
171 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
172 #define SDR0_PINSTP_SHIFT 29
173 static char *bootstrap_str[] = {
180 "I2C (Addr 0x54)", /* A8 */
181 "I2C (Addr 0x52)", /* A4 */
183 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
186 #if defined(CONFIG_460SX)
187 #define SDR0_PINSTP_SHIFT 29
188 static char *bootstrap_str[] = {
193 "I2C (Addr 0x54)", /* A8 */
194 "I2C (Addr 0x52)", /* A4 */
196 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G' };
199 #if defined(CONFIG_405EZ)
200 #define SDR0_PINSTP_SHIFT 28
201 static char *bootstrap_str[] = {
204 "NAND (512 page, 4 addr cycle)",
208 "NAND (2K page, 5 addr cycle)",
212 "NAND (2K page, 4 addr cycle)",
214 "NAND (512 page, 3 addr cycle)",
219 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \
220 'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' };
223 #if defined(CONFIG_405EX)
224 #define SDR0_PINSTP_SHIFT 29
225 static char *bootstrap_str[] = {
235 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
237 #if defined(CONFIG_APM821XX)
238 #define SDR0_PINSTP_SHIFT 29
239 static char *bootstrap_str[] = {
245 "NOR (8 bits) w/PLL Bypassed",
249 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
252 #if defined(SDR0_PINSTP_SHIFT)
253 static int bootstrap_option(void)
257 mfsdr(SDR0_PINSTP, val);
258 return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
260 #endif /* SDR0_PINSTP_SHIFT */
263 #if defined(CONFIG_440GP)
264 static int do_chip_reset (unsigned long sys0, unsigned long sys1)
266 /* Changes to CPC0_SYS0 and CPC0_SYS1 require chip
269 mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) | 0x80000000); /* Set SWE */
270 mtdcr (CPC0_SYS0, sys0);
271 mtdcr (CPC0_SYS1, sys1);
272 mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) & ~0x80000000); /* Clr SWE */
273 mtspr (SPRN_DBCR0, 0x20000000); /* Reset the chip */
277 #endif /* CONFIG_440GP */
282 #if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
283 uint pvr = get_pvr();
284 ulong clock = gd->cpu_clk;
286 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
290 char addstr[64] = "";
294 cpu_num = get_cpu_num();
296 printf("CPU%d: ", cpu_num);
300 get_sys_info(&sys_info);
302 #if defined(CONFIG_XILINX_440)
303 puts("IBM PowerPC ");
305 puts("AMCC PowerPC ");
310 #if !defined(CONFIG_440)
312 puts("405GP Rev. B");
316 puts("405GP Rev. C");
320 puts("405GP Rev. D");
324 puts("405GP Rev. E");
328 puts("405GPr Rev. B");
332 puts("405EP Rev. B");
336 puts("405EZ Rev. A");
340 puts("405EX Rev. A");
341 strcpy(addstr, "Security support");
345 puts("405EXr Rev. A");
346 strcpy(addstr, "No Security support");
350 puts("405EX Rev. C");
351 strcpy(addstr, "Security support");
355 puts("405EX Rev. C");
356 strcpy(addstr, "No Security support");
360 puts("405EXr Rev. C");
361 strcpy(addstr, "Security support");
365 puts("405EXr Rev. C");
366 strcpy(addstr, "No Security support");
370 puts("405EX Rev. D");
371 strcpy(addstr, "Security support");
375 puts("405EX Rev. D");
376 strcpy(addstr, "No Security support");
380 puts("405EXr Rev. D");
381 strcpy(addstr, "Security support");
385 puts("405EXr Rev. D");
386 strcpy(addstr, "No Security support");
389 #else /* CONFIG_440 */
391 #if defined(CONFIG_440GP)
393 puts("440GP Rev. B");
394 /* See errata 1.12: CHIP_4 */
395 if ((mfdcr(CPC0_SYS0) != mfdcr(CPC0_STRP0)) ||
396 (mfdcr(CPC0_SYS1) != mfdcr(CPC0_STRP1)) ){
397 puts ( "\n\t CPC0_SYSx DCRs corrupted. "
398 "Resetting chip ...\n");
399 udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
400 do_chip_reset ( mfdcr(CPC0_STRP0),
406 puts("440GP Rev. C");
408 #endif /* CONFIG_440GP */
411 puts("440GX Rev. A");
415 puts("440GX Rev. B");
419 puts("440GX Rev. C");
423 puts("440GX Rev. F");
427 puts("440EP Rev. A");
431 case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
432 puts("440EP Rev. B");
435 case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
436 puts("440EP Rev. C");
438 #endif /* CONFIG_440EP */
441 case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
442 puts("440GR Rev. A");
445 case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
446 puts("440GR Rev. B");
448 #endif /* CONFIG_440GR */
451 case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
452 puts("440EPx Rev. A");
453 strcpy(addstr, "Security/Kasumi support");
456 case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
457 puts("440EPx Rev. A");
458 strcpy(addstr, "No Security/Kasumi support");
460 #endif /* CONFIG_440EPX */
463 case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
464 puts("440GRx Rev. A");
465 strcpy(addstr, "Security/Kasumi support");
468 case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
469 puts("440GRx Rev. A");
470 strcpy(addstr, "No Security/Kasumi support");
472 #endif /* CONFIG_440GRX */
474 case PVR_440SP_6_RAB:
475 puts("440SP Rev. A/B");
476 strcpy(addstr, "RAID 6 support");
480 puts("440SP Rev. A/B");
481 strcpy(addstr, "No RAID 6 support");
485 puts("440SP Rev. C");
486 strcpy(addstr, "RAID 6 support");
490 puts("440SP Rev. C");
491 strcpy(addstr, "No RAID 6 support");
494 case PVR_440SPe_6_RA:
495 puts("440SPe Rev. A");
496 strcpy(addstr, "RAID 6 support");
500 puts("440SPe Rev. A");
501 strcpy(addstr, "No RAID 6 support");
504 case PVR_440SPe_6_RB:
505 puts("440SPe Rev. B");
506 strcpy(addstr, "RAID 6 support");
510 puts("440SPe Rev. B");
511 strcpy(addstr, "No RAID 6 support");
514 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
516 puts("460EX Rev. A");
517 strcpy(addstr, "No Security/Kasumi support");
520 case PVR_460EX_SE_RA:
521 puts("460EX Rev. A");
522 strcpy(addstr, "Security/Kasumi support");
526 puts("460EX Rev. B");
527 mfsdr(SDR0_ECID3, reg);
528 if (reg & 0x00100000)
529 strcpy(addstr, "No Security/Kasumi support");
531 strcpy(addstr, "Security/Kasumi support");
535 puts("460GT Rev. A");
536 strcpy(addstr, "No Security/Kasumi support");
539 case PVR_460GT_SE_RA:
540 puts("460GT Rev. A");
541 strcpy(addstr, "Security/Kasumi support");
545 puts("460GT Rev. B");
546 mfsdr(SDR0_ECID3, reg);
547 if (reg & 0x00100000)
548 strcpy(addstr, "No Security/Kasumi support");
550 strcpy(addstr, "Security/Kasumi support");
555 puts("460SX Rev. A");
556 strcpy(addstr, "Security support");
559 case PVR_460SX_RA_V1:
560 puts("460SX Rev. A");
561 strcpy(addstr, "No Security support");
565 puts("460GX Rev. A");
566 strcpy(addstr, "Security support");
569 case PVR_460GX_RA_V1:
570 puts("460GX Rev. A");
571 strcpy(addstr, "No Security support");
574 case PVR_APM821XX_RA:
575 puts("APM821XX Rev. A");
576 strcpy(addstr, "Security support");
580 puts("440x5 VIRTEX5");
582 #endif /* CONFIG_440 */
585 printf (" UNKNOWN (PVR=%08x)", pvr);
589 printf (" at %s MHz (PLB=%lu OPB=%lu EBC=%lu",
591 sys_info.freqPLB / 1000000,
592 get_OPB_freq() / 1000000,
593 sys_info.freqEBC / 1000000);
594 #if defined(CONFIG_PCI) && \
595 (defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
596 defined(CONFIG_440GR) || defined(CONFIG_440GRX))
597 printf(" PCI=%lu MHz", sys_info.freqPCI / 1000000);
602 printf(" %s\n", addstr);
604 #if defined(I2C_BOOTROM)
605 printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
606 #endif /* I2C_BOOTROM */
607 #if defined(SDR0_PINSTP_SHIFT)
608 printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]);
609 printf ("Boot ROM Location %s", bootstrap_str[bootstrap_option()]);
610 #ifdef CONFIG_NAND_U_BOOT
611 puts(", booting from NAND");
612 #endif /* CONFIG_NAND_U_BOOT */
614 #endif /* SDR0_PINSTP_SHIFT */
616 #if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
617 printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
620 #if defined(CONFIG_PCI) && defined(PCI_ASYNC)
621 if (pci_async_enabled()) {
622 printf (", PCI async ext clock used");
624 printf (", PCI sync clock at %lu MHz",
625 sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
629 #if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
633 #if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX)
634 printf(" 16 KiB I-Cache 16 KiB D-Cache");
635 #elif defined(CONFIG_440)
636 printf(" 32 KiB I-Cache 32 KiB D-Cache");
638 printf(" 16 KiB I-Cache %d KiB D-Cache",
639 ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
642 #endif /* !defined(CONFIG_405) */
649 int ppc440spe_revB() {
653 if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
659 /* ------------------------------------------------------------------------- */
661 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
663 #if defined(CONFIG_BOARD_RESET)
666 #if defined(CONFIG_SYS_4xx_RESET_TYPE)
667 mtspr(SPRN_DBCR0, CONFIG_SYS_4xx_RESET_TYPE << 28);
670 * Initiate system reset in debug control register DBCR
672 mtspr(SPRN_DBCR0, 0x30000000);
673 #endif /* defined(CONFIG_SYS_4xx_RESET_TYPE) */
674 #endif /* defined(CONFIG_BOARD_RESET) */
681 * Get timebase clock frequency
683 unsigned long get_tbclk (void)
687 get_sys_info(&sys_info);
688 return (sys_info.freqProcessor);
692 #if defined(CONFIG_WATCHDOG)
693 void watchdog_reset(void)
695 int re_enable = disable_interrupts();
696 reset_4xx_watchdog();
697 if (re_enable) enable_interrupts();
700 void reset_4xx_watchdog(void)
705 mtspr(SPRN_TSR, 0x40000000);
707 #endif /* CONFIG_WATCHDOG */
710 * Initializes on-chip ethernet controllers.
711 * to override, implement board_eth_init()
713 int cpu_eth_init(bd_t *bis)
715 #if defined(CONFIG_PPC4xx_EMAC)
716 ppc_4xx_eth_initialize(bis);