2 * (C) Copyright 2005-2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
6 * DAVE Srl <www.dave-tech.it>
8 * (C) Copyright 2002-2004
9 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
11 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/ppc4xx.h>
16 #include <asm/processor.h>
20 #ifdef CONFIG_SDRAM_BANK0
24 #ifndef CONFIG_SYS_SDRAM_TABLE
25 sdram_conf_t mb0cf[] = {
26 {(128 << 20), 13, 0x000A4001}, /* (0-128MB) Address Mode 3, 13x10(4) */
27 {(64 << 20), 13, 0x00084001}, /* (0-64MB) Address Mode 3, 13x9(4) */
28 {(32 << 20), 12, 0x00062001}, /* (0-32MB) Address Mode 2, 12x9(4) */
29 {(16 << 20), 12, 0x00046001}, /* (0-16MB) Address Mode 4, 12x8(4) */
30 {(4 << 20), 11, 0x00008001}, /* (0-4MB) Address Mode 5, 11x8(2) */
33 sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE;
36 #define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
38 #ifdef CONFIG_SYS_SDRAM_CASL
39 static ulong ns2clks(ulong ns)
41 ulong bus_period_x_10 = ONE_BILLION / (get_bus_freq(0) / 10);
43 return ((ns * 10) + bus_period_x_10) / bus_period_x_10;
45 #endif /* CONFIG_SYS_SDRAM_CASL */
47 static ulong compute_sdtr1(ulong speed)
49 #ifdef CONFIG_SYS_SDRAM_CASL
54 if (CONFIG_SYS_SDRAM_CASL < 2)
55 sdtr1 |= (1 << SDRAM0_TR_CASL);
57 if (CONFIG_SYS_SDRAM_CASL > 4)
58 sdtr1 |= (3 << SDRAM0_TR_CASL);
60 sdtr1 |= ((CONFIG_SYS_SDRAM_CASL-1) << SDRAM0_TR_CASL);
63 tmp = ns2clks(CONFIG_SYS_SDRAM_PTA);
64 if ((tmp >= 2) && (tmp <= 4))
65 sdtr1 |= ((tmp-1) << SDRAM0_TR_PTA);
67 sdtr1 |= ((4-1) << SDRAM0_TR_PTA);
70 tmp = ns2clks(CONFIG_SYS_SDRAM_CTP);
71 if ((tmp >= 2) && (tmp <= 4))
72 sdtr1 |= ((tmp-1) << SDRAM0_TR_CTP);
74 sdtr1 |= ((4-1) << SDRAM0_TR_CTP);
77 tmp = ns2clks(CONFIG_SYS_SDRAM_LDF);
78 if ((tmp >= 2) && (tmp <= 4))
79 sdtr1 |= ((tmp-1) << SDRAM0_TR_LDF);
81 sdtr1 |= ((2-1) << SDRAM0_TR_LDF);
84 tmp = ns2clks(CONFIG_SYS_SDRAM_RFTA);
85 if ((tmp >= 4) && (tmp <= 10))
86 sdtr1 |= ((tmp-4) << SDRAM0_TR_RFTA);
88 sdtr1 |= ((10-4) << SDRAM0_TR_RFTA);
91 tmp = ns2clks(CONFIG_SYS_SDRAM_RCD);
92 if ((tmp >= 2) && (tmp <= 4))
93 sdtr1 |= ((tmp-1) << SDRAM0_TR_RCD);
95 sdtr1 |= ((4-1) << SDRAM0_TR_RCD);
98 #else /* CONFIG_SYS_SDRAM_CASL */
100 * If no values are configured in the board config file
101 * use the default values, which seem to be ok for most
105 * For new board ports we strongly recommend to define the
106 * correct values for the used SDRAM chips in your board
107 * config file (see PPChameleonEVB.h)
109 if (speed > 100000000) {
116 * default: 100 MHz SDRAM
120 #endif /* CONFIG_SYS_SDRAM_CASL */
123 /* refresh is expressed in ms */
124 static ulong compute_rtr(ulong speed, ulong rows, ulong refresh)
126 #ifdef CONFIG_SYS_SDRAM_CASL
129 tmp = ((refresh*1000*1000) / (1 << rows)) * (speed / 1000);
132 return ((tmp & 0x00003FF8) << 16);
133 #else /* CONFIG_SYS_SDRAM_CASL */
134 if (speed > 100000000) {
141 * default: 100 MHz SDRAM
145 #endif /* CONFIG_SYS_SDRAM_CASL */
149 * Autodetect onboard SDRAM on 405 platforms
151 phys_size_t initdram(int board_type)
158 * Determine SDRAM speed
160 speed = get_bus_freq(0); /* parameter not used on ppc4xx */
163 * sdtr1 (register SDRAM0_TR) must take into account timings listed
164 * in SDRAM chip datasheet. rtr (register SDRAM0_RTR) must take into
165 * account actual SDRAM size. So we can set up sdtr1 according to what
166 * is specified in board configuration file while rtr dependds on SDRAM
167 * size we are assuming before detection.
169 sdtr1 = compute_sdtr1(speed);
171 for (i=0; i<N_MB0CF; i++) {
173 * Disable memory controller.
175 mtsdram(SDRAM0_CFG, 0x00000000);
178 * Set MB0CF for bank 0.
180 mtsdram(SDRAM0_B0CR, mb0cf[i].reg);
181 mtsdram(SDRAM0_TR, sdtr1);
182 mtsdram(SDRAM0_RTR, compute_rtr(speed, mb0cf[i].rows, 64));
187 * Set memory controller options reg, MCOPT1.
188 * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
191 mtsdram(SDRAM0_CFG, 0x80800000);
195 if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
196 phys_size_t size = mb0cf[i].size;
199 * OK, size detected. Enable second bank if
200 * defined (assumes same type as bank 0)
202 #ifdef CONFIG_SDRAM_BANK1
203 mtsdram(SDRAM0_CFG, 0x00000000);
204 mtsdram(SDRAM0_B1CR, mb0cf[i].size | mb0cf[i].reg);
205 mtsdram(SDRAM0_CFG, 0x80800000);
209 * Check if 2nd bank is really available.
210 * If the size not equal to the size of the first
211 * bank, then disable the 2nd bank completely.
213 if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) !=
215 mtsdram(SDRAM0_B1CR, 0);
216 mtsdram(SDRAM0_CFG, 0);
219 * We have two identical banks, so the size
220 * is twice the bank size
227 * OK, size detected -> all done
236 #else /* CONFIG_440 */
239 * Define some default values. Those can be overwritten in the
243 #ifndef CONFIG_SYS_SDRAM_TABLE
244 sdram_conf_t mb0cf[] = {
245 {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4) */
246 {(128 << 20), 13, 0x000A4001}, /* 128MB mode 3, 13x10(4) */
247 {(64 << 20), 12, 0x00082001} /* 64MB mode 2, 12x9(4) */
250 sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE;
253 #ifndef CONFIG_SYS_SDRAM0_TR0
254 #define CONFIG_SYS_SDRAM0_TR0 0x41094012
257 #ifndef CONFIG_SYS_SDRAM0_WDDCTR
258 #define CONFIG_SYS_SDRAM0_WDDCTR 0x00000000 /* wrcp=0 dcd=0 */
261 #ifndef CONFIG_SYS_SDRAM0_RTR
262 #define CONFIG_SYS_SDRAM0_RTR 0x04100000 /* 7.8us @ 133MHz PLB */
265 #ifndef CONFIG_SYS_SDRAM0_CFG0
266 #define CONFIG_SYS_SDRAM0_CFG0 0x82000000 /* DCEN=1, PMUD=0, 64-bit */
269 #define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
274 static void sdram_tr1_set(int ram_address, int* tr1_value)
278 volatile unsigned int* ram_pointer = (unsigned int *)ram_address;
279 int first_good = -1, last_bad = 0x1ff;
281 unsigned long test[NUM_TRIES] = {
282 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
283 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
284 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
285 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
286 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
287 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
288 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
289 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
290 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
291 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
292 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
293 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
294 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
295 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
296 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
297 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
299 /* go through all possible SDRAM0_TR1[RDCT] values */
300 for (i=0; i<=0x1ff; i++) {
301 /* set the current value for TR1 */
302 mtsdram(SDRAM0_TR1, (0x80800800 | i));
305 for (j=0; j<NUM_TRIES; j++) {
306 ram_pointer[j] = test[j];
308 /* clear any cache at ram location */
309 __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
312 /* read values back */
313 for (j=0; j<NUM_TRIES; j++) {
314 for (k=0; k<NUM_READS; k++) {
315 /* clear any cache at ram location */
316 __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
318 if (ram_pointer[j] != test[j])
327 /* we have a SDRAM0_TR1[RDCT] that is part of the window */
328 if (j == NUM_TRIES) {
329 if (first_good == -1)
330 first_good = i; /* found beginning of window */
331 } else { /* bad read */
332 /* if we have not had a good read then don't care */
333 if (first_good != -1) {
334 /* first failure after a good read */
341 /* return the current value for TR1 */
342 *tr1_value = (first_good + last_bad) / 2;
346 * Autodetect onboard DDR SDRAM on 440 platforms
348 * NOTE: Some of the hardcoded values are hardware dependant,
349 * so this should be extended for other future boards
350 * using this routine!
352 phys_size_t initdram(int board_type)
357 #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
358 defined(CONFIG_440GR) || defined(CONFIG_440SP)
360 * Soft-reset SDRAM controller.
362 mtsdr(SDR0_SRST, SDR0_SRST_DMC);
363 mtsdr(SDR0_SRST, 0x00000000);
366 for (i=0; i<N_MB0CF; i++) {
368 * Disable memory controller.
370 mtsdram(SDRAM0_CFG0, 0x00000000);
375 mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
376 mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
377 mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
378 mtsdram(SDRAM0_WDDCTR, CONFIG_SYS_SDRAM0_WDDCTR);
379 mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
382 * Following for CAS Latency = 2.5 @ 133 MHz PLB
384 mtsdram(SDRAM0_B0CR, mb0cf[i].reg);
385 mtsdram(SDRAM0_TR0, CONFIG_SYS_SDRAM0_TR0);
386 mtsdram(SDRAM0_TR1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
387 mtsdram(SDRAM0_RTR, CONFIG_SYS_SDRAM0_RTR);
388 mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM*/
389 udelay(400); /* Delay 200 usecs (min) */
392 * Enable the controller, then wait for DCEN to complete
394 mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0);
397 if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
398 phys_size_t size = mb0cf[i].size;
400 * Optimize TR1 to current hardware environment
402 sdram_tr1_set(0x00000000, &tr1_bank1);
403 mtsdram(SDRAM0_TR1, (tr1_bank1 | 0x80800800));
407 * OK, size detected. Enable second bank if
408 * defined (assumes same type as bank 0)
410 #ifdef CONFIG_SDRAM_BANK1
411 mtsdram(SDRAM0_CFG0, 0);
412 mtsdram(SDRAM0_B1CR, mb0cf[i].size | mb0cf[i].reg);
413 mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0);
417 * Check if 2nd bank is really available.
418 * If the size not equal to the size of the first
419 * bank, then disable the 2nd bank completely.
421 if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size)
423 mtsdram(SDRAM0_CFG0, 0);
424 mtsdram(SDRAM0_B1CR, 0);
425 mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0);
429 * We have two identical banks, so the size
430 * is twice the bank size
436 #ifdef CONFIG_SDRAM_ECC
441 * OK, size detected -> all done
447 return 0; /* nothing found ! */
450 #endif /* CONFIG_440 */
452 #endif /* CONFIG_SDRAM_BANK0 */