2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
6 * Copyright (c) 2008 Nuovation System Designs, LLC
7 * Grant Erickson <gerickson@nuovations.com>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 /*------------------------------------------------------------------------------+
28 * This source code is dual-licensed. You may use it under the terms of the
29 * GNU General Public License version 2, or under the license below.
31 * This source code has been made available to you by IBM on an AS-IS
32 * basis. Anyone receiving this source is licensed under IBM
33 * copyrights to use it in any way he or she deems fit, including
34 * copying it, modifying it, compiling it, and redistributing it either
35 * with or without modifications. No license under IBM patents or
36 * patent applications is to be implied by the copyright license.
38 * Any user of this software should understand that IBM cannot provide
39 * technical support for this software and will not be responsible for
40 * any consequences resulting from the use of this software.
42 * Any person who transfers this source code or any derivative work
43 * must include the IBM copyright notice, this paragraph, and the
44 * preceding two paragraphs in the transferred software.
46 * COPYRIGHT I B M CORPORATION 1995
47 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
48 *-------------------------------------------------------------------------------
51 /* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
54 * The processor starts at 0xfffffffc and the code is executed
56 * in memory, but as long we don't jump around before relocating.
57 * board_init lies at a quite high address and when the cpu has
58 * jumped there, everything is ok.
59 * This works because the cpu gives the FLASH (CS0) the whole
60 * address space at startup, and board_init lies as a echo of
61 * the flash somewhere up there in the memorymap.
63 * board_init will change CS0 to be positioned at the correct
64 * address and (s)dram will be positioned at address 0
67 #include <asm/ppc4xx.h>
68 #include <timestamp.h>
71 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
73 #include <ppc_asm.tmpl>
76 #include <asm/cache.h>
78 #include <asm/ppc4xx-isram.h>
80 #ifndef CONFIG_IDENT_STRING
81 #define CONFIG_IDENT_STRING ""
84 #ifdef CONFIG_SYS_INIT_DCACHE_CS
85 # if (CONFIG_SYS_INIT_DCACHE_CS == 0)
88 # if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
89 # define PBxAP_VAL CONFIG_SYS_EBC_PB0AP
90 # define PBxCR_VAL CONFIG_SYS_EBC_PB0CR
93 # if (CONFIG_SYS_INIT_DCACHE_CS == 1)
96 # if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR))
97 # define PBxAP_VAL CONFIG_SYS_EBC_PB1AP
98 # define PBxCR_VAL CONFIG_SYS_EBC_PB1CR
101 # if (CONFIG_SYS_INIT_DCACHE_CS == 2)
104 # if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR))
105 # define PBxAP_VAL CONFIG_SYS_EBC_PB2AP
106 # define PBxCR_VAL CONFIG_SYS_EBC_PB2CR
109 # if (CONFIG_SYS_INIT_DCACHE_CS == 3)
112 # if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR))
113 # define PBxAP_VAL CONFIG_SYS_EBC_PB3AP
114 # define PBxCR_VAL CONFIG_SYS_EBC_PB3CR
117 # if (CONFIG_SYS_INIT_DCACHE_CS == 4)
120 # if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR))
121 # define PBxAP_VAL CONFIG_SYS_EBC_PB4AP
122 # define PBxCR_VAL CONFIG_SYS_EBC_PB4CR
125 # if (CONFIG_SYS_INIT_DCACHE_CS == 5)
128 # if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR))
129 # define PBxAP_VAL CONFIG_SYS_EBC_PB5AP
130 # define PBxCR_VAL CONFIG_SYS_EBC_PB5CR
133 # if (CONFIG_SYS_INIT_DCACHE_CS == 6)
136 # if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR))
137 # define PBxAP_VAL CONFIG_SYS_EBC_PB6AP
138 # define PBxCR_VAL CONFIG_SYS_EBC_PB6CR
141 # if (CONFIG_SYS_INIT_DCACHE_CS == 7)
144 # if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR))
145 # define PBxAP_VAL CONFIG_SYS_EBC_PB7AP
146 # define PBxCR_VAL CONFIG_SYS_EBC_PB7CR
156 * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB
157 * used as temporary stack pointer for the primordial stack
159 # ifndef CONFIG_SYS_INIT_DCACHE_PBxAR
160 # define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \
161 EBC_BXAP_TWT_ENCODE(7) | \
162 EBC_BXAP_BCE_DISABLE | \
163 EBC_BXAP_BCT_2TRANS | \
164 EBC_BXAP_CSN_ENCODE(0) | \
165 EBC_BXAP_OEN_ENCODE(0) | \
166 EBC_BXAP_WBN_ENCODE(0) | \
167 EBC_BXAP_WBF_ENCODE(0) | \
168 EBC_BXAP_TH_ENCODE(2) | \
169 EBC_BXAP_RE_DISABLED | \
170 EBC_BXAP_SOR_NONDELAYED | \
171 EBC_BXAP_BEM_WRITEONLY | \
172 EBC_BXAP_PEN_DISABLED)
173 # endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */
174 # ifndef CONFIG_SYS_INIT_DCACHE_PBxCR
175 # define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \
179 # endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */
180 # ifndef CONFIG_SYS_INIT_RAM_PATTERN
181 # define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD
183 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
185 #if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_END > (4 << 10)))
186 #error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_END!
190 * Unless otherwise overriden, enable two 128MB cachable instruction regions
191 * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering
192 * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions.
194 #if !defined(CONFIG_SYS_FLASH_BASE)
195 /* If not already defined, set it to the "last" 128MByte region */
196 # define CONFIG_SYS_FLASH_BASE 0xf8000000
198 #if !defined(CONFIG_SYS_ICACHE_SACR_VALUE)
199 # define CONFIG_SYS_ICACHE_SACR_VALUE \
200 (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \
201 PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \
202 PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE))
203 #endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */
205 #if !defined(CONFIG_SYS_DCACHE_SACR_VALUE)
206 # define CONFIG_SYS_DCACHE_SACR_VALUE \
208 #endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */
210 #if !defined(CONFIG_SYS_TLB_FOR_BOOT_FLASH)
211 #define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0 /* use TLB 0 as default */
214 #define function_prolog(func_name) .text; \
218 #define function_epilog(func_name) .type func_name,@function; \
219 .size func_name,.-func_name
221 /* We don't want the MMU yet.
224 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
227 .extern ext_bus_cntlr_init
228 #ifdef CONFIG_NAND_U_BOOT
229 .extern reconfig_tlb0
233 * Set up GOT: Global Offset Table
235 * Use r12 to access the GOT
237 #if !defined(CONFIG_NAND_SPL)
239 GOT_ENTRY(_GOT2_TABLE_)
240 GOT_ENTRY(_FIXUP_TABLE_)
243 GOT_ENTRY(_start_of_vectors)
244 GOT_ENTRY(_end_of_vectors)
245 GOT_ENTRY(transfer_to_handler)
247 GOT_ENTRY(__init_end)
249 GOT_ENTRY(__bss_start)
251 #endif /* CONFIG_NAND_SPL */
253 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
255 * NAND U-Boot image is started from offset 0
258 #if defined(CONFIG_440)
262 bl cpu_init_f /* run low-level CPU init code (from Flash) */
266 #if defined(CONFIG_SYS_RAMBOOT)
268 * 4xx RAM-booting U-Boot image is started from offset 0
275 * 440 Startup -- on reset only the top 4k of the effective
276 * address space is mapped in by an entry in the instruction
277 * and data shadow TLB. The .bootpg section is located in the
278 * top 4k & does only what's necessary to map in the the rest
279 * of the boot rom. Once the boot rom is mapped in we can
280 * proceed with normal startup.
282 * NOTE: CS0 only covers the top 2MB of the effective address
286 #if defined(CONFIG_440)
287 #if !defined(CONFIG_NAND_SPL)
288 .section .bootpg,"ax"
292 /**************************************************************************/
294 /*--------------------------------------------------------------------+
295 | 440EPX BUP Change - Hardware team request
296 +--------------------------------------------------------------------*/
297 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
302 /*----------------------------------------------------------------+
303 | Core bug fix. Clear the esr
304 +-----------------------------------------------------------------*/
307 /*----------------------------------------------------------------*/
308 /* Clear and set up some registers. */
309 /*----------------------------------------------------------------*/
310 iccci r0,r0 /* NOTE: operands not used for 440 */
311 dccci r0,r0 /* NOTE: operands not used for 440 */
318 /* NOTE: 440GX adds machine check status regs */
319 #if defined(CONFIG_440) && !defined(CONFIG_440GP)
326 /*----------------------------------------------------------------*/
328 /*----------------------------------------------------------------*/
329 /* Disable store gathering & broadcast, guarantee inst/data
330 * cache block touch, force load/store alignment
331 * (see errata 1.12: 440_33)
333 lis r1,0x0030 /* store gathering & broadcast disable */
334 ori r1,r1,0x6000 /* cache touch */
337 /*----------------------------------------------------------------*/
338 /* Initialize debug */
339 /*----------------------------------------------------------------*/
341 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
342 bne skip_debug_init /* if set, don't clear debug register */
355 mtspr SPRN_DBSR,r1 /* Clear all valid bits */
358 #if defined (CONFIG_440SPE)
359 /*----------------------------------------------------------------+
360 | Initialize Core Configuration Reg1.
361 | a. ICDPEI: Record even parity. Normal operation.
362 | b. ICTPEI: Record even parity. Normal operation.
363 | c. DCTPEI: Record even parity. Normal operation.
364 | d. DCDPEI: Record even parity. Normal operation.
365 | e. DCUPEI: Record even parity. Normal operation.
366 | f. DCMPEI: Record even parity. Normal operation.
367 | g. FCOM: Normal operation
368 | h. MMUPEI: Record even parity. Normal operation.
369 | i. FFF: Flush only as much data as necessary.
370 | j. TCS: Timebase increments from CPU clock.
371 +-----------------------------------------------------------------*/
375 /*----------------------------------------------------------------+
376 | Reset the timebase.
377 | The previous write to CCR1 sets the timebase source.
378 +-----------------------------------------------------------------*/
383 /*----------------------------------------------------------------*/
384 /* Setup interrupt vectors */
385 /*----------------------------------------------------------------*/
386 mtspr SPRN_IVPR,r0 /* Vectors start at 0x0000_0000 */
388 mtspr SPRN_IVOR0,r1 /* Critical input */
390 mtspr SPRN_IVOR1,r1 /* Machine check */
392 mtspr SPRN_IVOR2,r1 /* Data storage */
394 mtspr SPRN_IVOR3,r1 /* Instruction storage */
396 mtspr SPRN_IVOR4,r1 /* External interrupt */
398 mtspr SPRN_IVOR5,r1 /* Alignment */
400 mtspr SPRN_IVOR6,r1 /* Program check */
402 mtspr SPRN_IVOR7,r1 /* Floating point unavailable */
404 mtspr SPRN_IVOR8,r1 /* System call */
406 mtspr SPRN_IVOR9,r1 /* Auxiliary Processor unavailable */
408 mtspr SPRN_IVOR10,r1 /* Decrementer */
410 mtspr SPRN_IVOR13,r1 /* Data TLB error */
412 mtspr SPRN_IVOR14,r1 /* Instr TLB error */
414 mtspr SPRN_IVOR15,r1 /* Debug */
416 /*----------------------------------------------------------------*/
417 /* Configure cache regions */
418 /*----------------------------------------------------------------*/
436 /*----------------------------------------------------------------*/
437 /* Cache victim limits */
438 /*----------------------------------------------------------------*/
439 /* floors 0, ceiling max to use the entire cache -- nothing locked
446 /*----------------------------------------------------------------+
447 |Initialize MMUCR[STID] = 0.
448 +-----------------------------------------------------------------*/
455 /*----------------------------------------------------------------*/
456 /* Clear all TLB entries -- TID = 0, TS = 0 */
457 /*----------------------------------------------------------------*/
459 #ifdef CONFIG_SYS_RAMBOOT
460 li r4,0 /* Start with TLB #0 */
462 li r4,1 /* Start with TLB #1 */
464 li r1,64 /* 64 TLB entries */
465 sub r1,r1,r4 /* calculate last TLB # */
468 #ifdef CONFIG_SYS_RAMBOOT
469 tlbre r3,r4,0 /* Read contents from TLB word #0 to get EPN */
470 rlwinm. r3,r3,0,0xfffffc00 /* Mask EPN */
471 beq tlbnxt /* Skip EPN=0 TLB, this is the SDRAM TLB */
473 tlbwe r0,r4,0 /* Invalidate all entries (V=0)*/
476 tlbnxt: addi r4,r4,1 /* Next TLB */
479 /*----------------------------------------------------------------*/
480 /* TLB entry setup -- step thru tlbtab */
481 /*----------------------------------------------------------------*/
482 #if defined(CONFIG_440SPE_REVA)
483 /*----------------------------------------------------------------*/
484 /* We have different TLB tables for revA and rev B of 440SPe */
485 /*----------------------------------------------------------------*/
497 bl tlbtab /* Get tlbtab pointer */
500 li r1,0x003f /* 64 TLB entries max */
506 #ifdef CONFIG_SYS_RAMBOOT
507 tlbre r3,r4,0 /* Read contents from TLB word #0 */
508 rlwinm. r3,r3,0,0x00000200 /* Mask V (valid) bit */
509 bne tlbnx2 /* Skip V=1 TLB, this is the SDRAM TLB */
513 beq 2f /* 0 marks end */
516 tlbwe r0,r4,0 /* TLB Word 0 */
517 tlbwe r1,r4,1 /* TLB Word 1 */
518 tlbwe r2,r4,2 /* TLB Word 2 */
519 tlbnx2: addi r4,r4,1 /* Next TLB */
522 /*----------------------------------------------------------------*/
523 /* Continue from 'normal' start */
524 /*----------------------------------------------------------------*/
530 mtspr SPRN_SRR1,r0 /* Keep things disabled for now */
534 #endif /* CONFIG_440 */
537 * r3 - 1st arg to board_init(): IMMP pointer
538 * r4 - 2nd arg to board_init(): boot flag
540 #ifndef CONFIG_NAND_SPL
542 .long 0x27051956 /* U-Boot Magic Number */
543 .globl version_string
545 .ascii U_BOOT_VERSION
546 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
547 .ascii CONFIG_IDENT_STRING, "\0"
549 . = EXC_OFF_SYS_RESET
550 .globl _start_of_vectors
553 /* Critical input. */
554 CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
558 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
560 CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
561 #endif /* CONFIG_440 */
563 /* Data Storage exception. */
564 STD_EXCEPTION(0x300, DataStorage, UnknownException)
566 /* Instruction Storage exception. */
567 STD_EXCEPTION(0x400, InstStorage, UnknownException)
569 /* External Interrupt exception. */
570 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
572 /* Alignment exception. */
575 EXCEPTION_PROLOG(SRR0, SRR1)
580 addi r3,r1,STACK_FRAME_OVERHEAD
581 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
583 /* Program check exception */
586 EXCEPTION_PROLOG(SRR0, SRR1)
587 addi r3,r1,STACK_FRAME_OVERHEAD
588 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
592 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
593 STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
594 STD_EXCEPTION(0xa00, APU, UnknownException)
596 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
599 STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
600 STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
602 STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
603 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
604 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
606 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
608 .globl _end_of_vectors
615 /*****************************************************************************/
616 #if defined(CONFIG_440)
618 /*----------------------------------------------------------------*/
619 /* Clear and set up some registers. */
620 /*----------------------------------------------------------------*/
623 mtspr SPRN_DEC,r0 /* prevent dec exceptions */
624 mtspr SPRN_TBWL,r0 /* prevent fit & wdt exceptions */
626 mtspr SPRN_TSR,r1 /* clear all timer exception status */
627 mtspr SPRN_TCR,r0 /* disable all */
628 mtspr SPRN_ESR,r0 /* clear exception syndrome register */
629 mtxer r0 /* clear integer exception register */
631 /*----------------------------------------------------------------*/
632 /* Debug setup -- some (not very good) ice's need an event*/
633 /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */
634 /* value you need in this case 0x8cff 0000 should do the trick */
635 /*----------------------------------------------------------------*/
636 #if defined(CONFIG_SYS_INIT_DBCR)
639 mtspr SPRN_DBSR,r1 /* Clear all status bits */
640 lis r0,CONFIG_SYS_INIT_DBCR@h
641 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
646 /*----------------------------------------------------------------*/
647 /* Setup the internal SRAM */
648 /*----------------------------------------------------------------*/
651 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
652 /* Clear Dcache to use as RAM */
653 addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
654 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
655 addis r4,r0,CONFIG_SYS_INIT_RAM_END@h
656 ori r4,r4,CONFIG_SYS_INIT_RAM_END@l
657 rlwinm. r5,r4,0,27,31
669 * Lock the init-ram/stack in d-cache, so that other regions
670 * may use d-cache as well
671 * Note, that this current implementation locks exactly 4k
672 * of d-cache, so please make sure that you don't define a
673 * bigger init-ram area. Take a look at the lwmon5 440EPx
674 * implementation as a reference.
678 /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
694 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
696 /* 440EP & 440GR are only 440er PPC's without internal SRAM */
697 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
698 /* not all PPC's have internal SRAM usable as L2-cache */
699 #if defined(CONFIG_440GX) || \
700 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
701 defined(CONFIG_460SX)
702 mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */
703 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
705 ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */
706 mtdcr L2_CACHE_CFG,r1
712 and r1,r1,r2 /* Disable parity check */
715 and r1,r1,r2 /* Disable pwr mgmt */
718 lis r1,0x8000 /* BAS = 8000_0000 */
719 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
720 ori r1,r1,0x0980 /* first 64k */
721 mtdcr ISRAM0_SB0CR,r1
723 ori r1,r1,0x0980 /* second 64k */
724 mtdcr ISRAM0_SB1CR,r1
726 ori r1,r1, 0x0980 /* third 64k */
727 mtdcr ISRAM0_SB2CR,r1
729 ori r1,r1, 0x0980 /* fourth 64k */
730 mtdcr ISRAM0_SB3CR,r1
731 #elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT)
732 lis r1,0x0000 /* BAS = X_0000_0000 */
733 ori r1,r1,0x0984 /* first 64k */
734 mtdcr ISRAM0_SB0CR,r1
736 ori r1,r1,0x0984 /* second 64k */
737 mtdcr ISRAM0_SB1CR,r1
739 ori r1,r1, 0x0984 /* third 64k */
740 mtdcr ISRAM0_SB2CR,r1
742 ori r1,r1, 0x0984 /* fourth 64k */
743 mtdcr ISRAM0_SB3CR,r1
744 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
748 and r1,r1,r2 /* Disable parity check */
751 and r1,r1,r2 /* Disable pwr mgmt */
754 lis r1,0x0004 /* BAS = 4_0004_0000 */
755 ori r1,r1,0x0984 /* 64k */
756 mtdcr ISRAM1_SB0CR,r1
758 #elif defined(CONFIG_460SX)
759 lis r1,0x0000 /* BAS = 0000_0000 */
760 ori r1,r1,0x0B84 /* first 128k */
761 mtdcr ISRAM0_SB0CR,r1
763 ori r1,r1,0x0B84 /* second 128k */
764 mtdcr ISRAM0_SB1CR,r1
766 ori r1,r1, 0x0B84 /* third 128k */
767 mtdcr ISRAM0_SB2CR,r1
769 ori r1,r1, 0x0B84 /* fourth 128k */
770 mtdcr ISRAM0_SB3CR,r1
771 #elif defined(CONFIG_440GP)
772 ori r1,r1,0x0380 /* 8k rw */
773 mtdcr ISRAM0_SB0CR,r1
774 mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */
776 #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
778 /*----------------------------------------------------------------*/
779 /* Setup the stack in internal SRAM */
780 /*----------------------------------------------------------------*/
781 lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
782 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
785 stwu r0,-4(r1) /* Terminate call chain */
787 stwu r1,-8(r1) /* Save back chain and move SP */
788 lis r0,RESET_VECTOR@h /* Address of reset vector */
789 ori r0,r0, RESET_VECTOR@l
790 stwu r1,-8(r1) /* Save back chain and move SP */
791 stw r0,+12(r1) /* Save return addr (underflow vect) */
793 #ifdef CONFIG_NAND_SPL
794 bl nand_boot_common /* will not return */
798 bl cpu_init_f /* run low-level CPU init code (from Flash) */
802 #endif /* CONFIG_440 */
804 /*****************************************************************************/
806 /*----------------------------------------------------------------------- */
807 /* Set up some machine state registers. */
808 /*----------------------------------------------------------------------- */
809 addi r0,r0,0x0000 /* initialize r0 to zero */
810 mtspr SPRN_ESR,r0 /* clear Exception Syndrome Reg */
811 mttcr r0 /* timer control register */
812 mtexier r0 /* disable all interrupts */
813 addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
814 ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
815 mtdbsr r4 /* clear/reset the dbsr */
816 mtexisr r4 /* clear all pending interrupts */
818 mtexier r4 /* enable critical exceptions */
819 addis r4,r0,0x0000 /* assume 403GCX - enable core clk */
820 ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */
821 mtiocr r4 /* since bit not used) & DRC to latch */
822 /* data bus on rising edge of CAS */
823 /*----------------------------------------------------------------------- */
825 /*----------------------------------------------------------------------- */
827 /*----------------------------------------------------------------------- */
828 /* Invalidate i-cache and d-cache TAG arrays. */
829 /*----------------------------------------------------------------------- */
830 addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */
831 addi r4,0,1024 /* 1/4 of I-cache */
836 addic. r3,r3,-16 /* move back one cache line */
837 bne ..cloop /* loop back to do rest until r3 = 0 */
840 /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
841 /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
844 /* first copy IOP480 register base address into r3 */
845 addis r3,0,0x5000 /* IOP480 register base address hi */
846 /* ori r3,r3,0x0000 / IOP480 register base address lo */
849 /* use r4 as the working variable */
850 /* turn on CS3 (LOCCTL.7) */
851 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
852 andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */
853 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
856 #ifdef CONFIG_DASA_SIM
857 /* use r4 as the working variable */
858 /* turn on MA17 (LOCCTL.7) */
859 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
860 ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */
861 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
864 /* turn on MA16..13 (LCS0BRD.12 = 0) */
865 lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
866 andi. r4,r4,0xefff /* make bit 12 = 0 */
867 stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
869 /* make sure above stores all comlete before going on */
872 /* last thing, set local init status done bit (DEVINIT.31) */
873 lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */
874 oris r4,r4,0x8000 /* make bit 31 = 1 */
875 stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */
877 /* clear all pending interrupts and disable all interrupts */
878 li r4,-1 /* set p1 to 0xffffffff */
879 stw r4,0x1b0(r3) /* clear all pending interrupts */
880 stw r4,0x1b8(r3) /* clear all pending interrupts */
881 li r4,0 /* set r4 to 0 */
882 stw r4,0x1b4(r3) /* disable all interrupts */
883 stw r4,0x1bc(r3) /* disable all interrupts */
885 /* make sure above stores all comlete before going on */
888 /* Set-up icache cacheability. */
889 lis r1, CONFIG_SYS_ICACHE_SACR_VALUE@h
890 ori r1, r1, CONFIG_SYS_ICACHE_SACR_VALUE@l
894 /* Set-up dcache cacheability. */
895 lis r1, CONFIG_SYS_DCACHE_SACR_VALUE@h
896 ori r1, r1, CONFIG_SYS_DCACHE_SACR_VALUE@l
899 addis r1,r0,CONFIG_SYS_INIT_RAM_ADDR@h
900 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack to SDRAM */
901 li r0, 0 /* Make room for stack frame header and */
902 stwu r0, -4(r1) /* clear final stack frame so that */
903 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
905 GET_GOT /* initialize GOT access */
907 bl board_init_f /* run first part of init code (from Flash) */
909 #endif /* CONFIG_IOP480 */
911 /*****************************************************************************/
912 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
913 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
914 defined(CONFIG_405EX) || defined(CONFIG_405)
915 /*----------------------------------------------------------------------- */
916 /* Clear and set up some registers. */
917 /*----------------------------------------------------------------------- */
919 #if !defined(CONFIG_405EX)
923 * On 405EX, completely clearing the SGR leads to PPC hangup
924 * upon PCIe configuration access. The PCIe memory regions
925 * need to be guarded!
932 mtesr r4 /* clear Exception Syndrome Reg */
933 mttcr r4 /* clear Timer Control Reg */
934 mtxer r4 /* clear Fixed-Point Exception Reg */
935 mtevpr r4 /* clear Exception Vector Prefix Reg */
936 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
937 /* dbsr is cleared by setting bits to 1) */
938 mtdbsr r4 /* clear/reset the dbsr */
940 /* Invalidate the i- and d-caches. */
944 /* Set-up icache cacheability. */
945 lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h
946 ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l
950 /* Set-up dcache cacheability. */
951 lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h
952 ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l
955 #if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\
956 && !defined (CONFIG_XILINX_405)
957 /*----------------------------------------------------------------------- */
958 /* Tune the speed and size for flash CS0 */
959 /*----------------------------------------------------------------------- */
960 bl ext_bus_cntlr_init
963 #if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM))
965 * For boards that don't have OCM and can't use the data cache
966 * for their primordial stack, setup stack here directly after the
967 * SDRAM is initialized in ext_bus_cntlr_init.
969 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
970 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */
972 li r0, 0 /* Make room for stack frame header and */
973 stwu r0, -4(r1) /* clear final stack frame so that */
974 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
976 * Set up a dummy frame to store reset vector as return address.
977 * this causes stack underflow to reset board.
979 stwu r1, -8(r1) /* Save back chain and move SP */
980 lis r0, RESET_VECTOR@h /* Address of reset vector */
981 ori r0, r0, RESET_VECTOR@l
982 stwu r1, -8(r1) /* Save back chain and move SP */
983 stw r0, +12(r1) /* Save return addr (underflow vect) */
984 #endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */
986 #if defined(CONFIG_405EP)
987 /*----------------------------------------------------------------------- */
988 /* DMA Status, clear to come up clean */
989 /*----------------------------------------------------------------------- */
990 addis r3,r0, 0xFFFF /* Clear all existing DMA status */
994 bl ppc405ep_init /* do ppc405ep specific init */
995 #endif /* CONFIG_405EP */
997 #if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)
998 #if defined(CONFIG_405EZ)
999 /********************************************************************
1000 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
1001 *******************************************************************/
1003 * We can map the OCM on the PLB3, so map it at
1004 * CONFIG_SYS_OCM_DATA_ADDR + 0x8000
1006 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1007 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
1008 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
1009 mtdcr OCM0_PLBCR1,r3 /* Set PLB Access */
1010 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
1011 mtdcr OCM0_PLBCR2,r3 /* Set PLB Access */
1014 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1015 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
1016 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
1017 mtdcr OCM0_DSRC1, r3 /* Set Data Side */
1018 mtdcr OCM0_ISRC1, r3 /* Set Instruction Side */
1019 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
1020 mtdcr OCM0_DSRC2, r3 /* Set Data Side */
1021 mtdcr OCM0_ISRC2, r3 /* Set Instruction Side */
1022 addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
1023 mtdcr OCM0_DISDPC,r3
1026 #else /* CONFIG_405EZ */
1027 /********************************************************************
1028 * Setup OCM - On Chip Memory
1029 *******************************************************************/
1033 mfdcr r3, OCM0_ISCNTL /* get instr-side IRAM config */
1034 mfdcr r4, OCM0_DSCNTL /* get data-side IRAM config */
1035 and r3, r3, r0 /* disable data-side IRAM */
1036 and r4, r4, r0 /* disable data-side IRAM */
1037 mtdcr OCM0_ISCNTL, r3 /* set instr-side IRAM config */
1038 mtdcr OCM0_DSCNTL, r4 /* set data-side IRAM config */
1041 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1042 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
1043 mtdcr OCM0_DSARC, r3
1044 addis r4, 0, 0xC000 /* OCM data area enabled */
1045 mtdcr OCM0_DSCNTL, r4
1047 #endif /* CONFIG_405EZ */
1050 /*----------------------------------------------------------------------- */
1051 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
1052 /*----------------------------------------------------------------------- */
1053 #ifdef CONFIG_SYS_INIT_DCACHE_CS
1055 mtdcr EBC0_CFGADDR, r4
1056 lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h
1057 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l
1058 mtdcr EBC0_CFGDATA, r4
1061 mtdcr EBC0_CFGADDR, r4
1062 lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h
1063 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l
1064 mtdcr EBC0_CFGDATA, r4
1067 * Enable the data cache for the 128MB storage access control region
1068 * at CONFIG_SYS_INIT_RAM_ADDR.
1071 oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1072 ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1076 * Preallocate data cache lines to be used to avoid a subsequent
1077 * cache miss and an ensuing machine check exception when exceptions
1082 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1083 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1085 lis r4, CONFIG_SYS_INIT_RAM_END@h
1086 ori r4, r4, CONFIG_SYS_INIT_RAM_END@l
1089 * Convert the size, in bytes, to the number of cache lines/blocks
1092 clrlwi. r5, r4, (32 - L1_CACHE_SHIFT)
1093 srwi r5, r4, L1_CACHE_SHIFT
1099 /* Preallocate the computed number of cache blocks. */
1100 ..alloc_dcache_block:
1102 addi r3, r3, L1_CACHE_BYTES
1103 bdnz ..alloc_dcache_block
1107 * Load the initial stack pointer and data area and convert the size,
1108 * in bytes, to the number of words to initialize to a known value.
1110 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
1111 ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
1113 lis r4, (CONFIG_SYS_INIT_RAM_END >> 2)@h
1114 ori r4, r4, (CONFIG_SYS_INIT_RAM_END >> 2)@l
1117 lis r2, CONFIG_SYS_INIT_RAM_ADDR@h
1118 ori r2, r2, CONFIG_SYS_INIT_RAM_END@l
1120 lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h
1121 ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
1128 * Make room for stack frame header and clear final stack frame so
1129 * that stack backtraces terminate cleanly.
1135 * Set up a dummy frame to store reset vector as return address.
1136 * this causes stack underflow to reset board.
1138 stwu r1, -8(r1) /* Save back chain and move SP */
1139 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
1140 ori r0, r0, RESET_VECTOR@l
1141 stwu r1, -8(r1) /* Save back chain and move SP */
1142 stw r0, +12(r1) /* Save return addr (underflow vect) */
1144 #elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \
1145 (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE))
1150 /* Set up Stack at top of OCM */
1151 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h
1152 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l
1154 /* Set up a zeroized stack frame so that backtrace works right */
1160 * Set up a dummy frame to store reset vector as return address.
1161 * this causes stack underflow to reset board.
1163 stwu r1, -8(r1) /* Save back chain and move SP */
1164 lis r0, RESET_VECTOR@h /* Address of reset vector */
1165 ori r0, r0, RESET_VECTOR@l
1166 stwu r1, -8(r1) /* Save back chain and move SP */
1167 stw r0, +12(r1) /* Save return addr (underflow vect) */
1168 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
1170 #ifdef CONFIG_NAND_SPL
1171 bl nand_boot_common /* will not return */
1173 GET_GOT /* initialize GOT access */
1175 bl cpu_init_f /* run low-level CPU init code (from Flash) */
1177 /* NEVER RETURNS! */
1178 bl board_init_f /* run first part of init code (from Flash) */
1179 #endif /* CONFIG_NAND_SPL */
1181 #endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
1182 /*----------------------------------------------------------------------- */
1185 #ifndef CONFIG_NAND_SPL
1187 * This code finishes saving the registers to the exception frame
1188 * and jumps to the appropriate handler for the exception.
1189 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1191 .globl transfer_to_handler
1192 transfer_to_handler:
1202 andi. r24,r23,0x3f00 /* get vector offset */
1206 mtspr SPRG2,r22 /* r1 is now kernel sp */
1207 lwz r24,0(r23) /* virtual address of handler */
1208 lwz r23,4(r23) /* where to go when done */
1213 rfi /* jump to handler, enable MMU */
1216 mfmsr r28 /* Disable interrupts */
1220 SYNC /* Some chip revs need this... */
1235 lwz r2,_NIP(r1) /* Restore environment */
1246 mfmsr r28 /* Disable interrupts */
1250 SYNC /* Some chip revs need this... */
1265 lwz r2,_NIP(r1) /* Restore environment */
1277 mfmsr r28 /* Disable interrupts */
1281 SYNC /* Some chip revs need this... */
1296 lwz r2,_NIP(r1) /* Restore environment */
1298 mtspr SPRN_MCSRR0,r2
1299 mtspr SPRN_MCSRR1,r0
1305 #endif /* CONFIG_440 */
1313 /*------------------------------------------------------------------------------- */
1314 /* Function: out16 */
1315 /* Description: Output 16 bits */
1316 /*------------------------------------------------------------------------------- */
1322 /*------------------------------------------------------------------------------- */
1323 /* Function: out16r */
1324 /* Description: Byte reverse and output 16 bits */
1325 /*------------------------------------------------------------------------------- */
1331 /*------------------------------------------------------------------------------- */
1332 /* Function: out32r */
1333 /* Description: Byte reverse and output 32 bits */
1334 /*------------------------------------------------------------------------------- */
1340 /*------------------------------------------------------------------------------- */
1341 /* Function: in16 */
1342 /* Description: Input 16 bits */
1343 /*------------------------------------------------------------------------------- */
1349 /*------------------------------------------------------------------------------- */
1350 /* Function: in16r */
1351 /* Description: Input 16 bits and byte reverse */
1352 /*------------------------------------------------------------------------------- */
1358 /*------------------------------------------------------------------------------- */
1359 /* Function: in32r */
1360 /* Description: Input 32 bits and byte reverse */
1361 /*------------------------------------------------------------------------------- */
1368 * void relocate_code (addr_sp, gd, addr_moni)
1370 * This "function" does not return, instead it continues in RAM
1371 * after relocating the monitor code.
1373 * r3 = Relocated stack pointer
1374 * r4 = Relocated global data pointer
1375 * r5 = Relocated text pointer
1377 .globl relocate_code
1379 #if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS)
1381 * We need to flush the initial global data (gd_t) before the dcache
1382 * will be invalidated.
1385 /* Save registers */
1390 /* Flush initial global data range */
1392 addi r4, r4, CONFIG_SYS_GBL_DATA_SIZE@l
1393 bl flush_dcache_range
1395 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
1397 * Undo the earlier data cache set-up for the primordial stack and
1398 * data area. First, invalidate the data cache and then disable data
1399 * cacheability for that area. Finally, restore the EBC values, if
1403 /* Invalidate the primordial stack and data area in cache */
1404 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1405 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1407 lis r4, CONFIG_SYS_INIT_RAM_END@h
1408 ori r4, r4, CONFIG_SYS_INIT_RAM_END@l
1411 bl invalidate_dcache_range
1413 /* Disable cacheability for the region */
1415 lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1416 ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1420 /* Restore the EBC parameters */
1422 mtdcr EBC0_CFGADDR, r3
1424 ori r3, r3, PBxAP_VAL@l
1425 mtdcr EBC0_CFGDATA, r3
1428 mtdcr EBC0_CFGADDR, r3
1430 ori r3, r3, PBxCR_VAL@l
1431 mtdcr EBC0_CFGDATA, r3
1432 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
1434 /* Restore registers */
1438 #endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */
1440 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
1442 * Unlock the previously locked d-cache
1446 /* set TFLOOR/NFLOOR to 0 again */
1463 /* Invalidate data cache, now no longer our stack */
1467 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
1470 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1471 * to speed up the boot process. Now this cache needs to be disabled.
1473 #if defined(CONFIG_440)
1474 /* Clear all potential pending exceptions */
1477 addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */
1478 tlbre r0,r1,0x0002 /* Read contents */
1479 ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
1480 tlbwe r0,r1,0x0002 /* Save it out */
1483 #endif /* defined(CONFIG_440) */
1484 mr r1, r3 /* Set new stack pointer */
1485 mr r9, r4 /* Save copy of Init Data pointer */
1486 mr r10, r5 /* Save copy of Destination Address */
1489 mr r3, r5 /* Destination Address */
1490 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1491 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
1492 lwz r5, GOT(__init_end)
1494 li r6, L1_CACHE_BYTES /* Cache Line Size */
1499 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1505 /* First our own GOT */
1507 /* then the one used by the C code */
1517 beq cr1,4f /* In place copy is not necessary */
1518 beq 7f /* Protect against 0 count */
1537 * Now flush the cache: note that we must start from a cache aligned
1538 * address. Otherwise we might miss one cache line.
1542 beq 7f /* Always flush prefetch queue in any case */
1550 sync /* Wait for all dcbst to complete on bus */
1556 7: sync /* Wait for all icbi to complete on bus */
1560 * We are done. Do not return, instead branch to second part of board
1561 * initialization, now running from RAM.
1564 addi r0, r10, in_ram - _start + _START_OFFSET
1566 blr /* NEVER RETURNS! */
1571 * Relocation Function, r12 point to got2+0x8000
1573 * Adjust got2 pointers, no need to check for 0, this code
1574 * already puts a few entries in the table.
1576 li r0,__got2_entries@sectoff@l
1577 la r3,GOT(_GOT2_TABLE_)
1578 lwz r11,GOT(_GOT2_TABLE_)
1590 * Now adjust the fixups and the pointers to the fixups
1591 * in case we need to move ourselves again.
1593 li r0,__fixup_entries@sectoff@l
1594 lwz r3,GOT(_FIXUP_TABLE_)
1608 * Now clear BSS segment
1610 lwz r3,GOT(__bss_start)
1633 mr r3, r9 /* Init Data pointer */
1634 mr r4, r10 /* Destination Address */
1638 * Copy exception vector code to low memory
1641 * r7: source address, r8: end address, r9: target address
1645 mflr r4 /* save link register */
1647 lwz r7, GOT(_start_of_vectors)
1648 lwz r8, GOT(_end_of_vectors)
1650 li r9, 0x100 /* reset vector always at 0x100 */
1653 bgelr /* return if r7>=r8 - just in case */
1663 * relocate `hdlr' and `int_return' entries
1665 li r7, .L_MachineCheck - _start + _START_OFFSET
1666 li r8, Alignment - _start + _START_OFFSET
1669 addi r7, r7, 0x100 /* next exception vector */
1673 li r7, .L_Alignment - _start + _START_OFFSET
1676 li r7, .L_ProgramCheck - _start + _START_OFFSET
1680 li r7, .L_FPUnavailable - _start + _START_OFFSET
1683 li r7, .L_Decrementer - _start + _START_OFFSET
1686 li r7, .L_APU - _start + _START_OFFSET
1689 li r7, .L_InstructionTLBError - _start + _START_OFFSET
1692 li r7, .L_DataTLBError - _start + _START_OFFSET
1694 #else /* CONFIG_440 */
1695 li r7, .L_PIT - _start + _START_OFFSET
1698 li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
1701 li r7, .L_DataTLBMiss - _start + _START_OFFSET
1703 #endif /* CONFIG_440 */
1705 li r7, .L_DebugBreakpoint - _start + _START_OFFSET
1708 #if !defined(CONFIG_440)
1709 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1710 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1711 mtmsr r7 /* change MSR */
1714 b __440_msr_continue
1717 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1718 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1726 mtlr r4 /* restore link register */
1729 #if defined(CONFIG_440)
1730 /*----------------------------------------------------------------------------+
1732 +----------------------------------------------------------------------------*/
1733 function_prolog(dcbz_area)
1734 rlwinm. r5,r4,0,27,31
1735 rlwinm r5,r4,27,5,31
1744 function_epilog(dcbz_area)
1745 #endif /* CONFIG_440 */
1746 #endif /* CONFIG_NAND_SPL */
1748 /*------------------------------------------------------------------------------- */
1750 /* Description: Input 8 bits */
1751 /*------------------------------------------------------------------------------- */
1757 /*------------------------------------------------------------------------------- */
1758 /* Function: out8 */
1759 /* Description: Output 8 bits */
1760 /*------------------------------------------------------------------------------- */
1766 /*------------------------------------------------------------------------------- */
1767 /* Function: out32 */
1768 /* Description: Output 32 bits */
1769 /*------------------------------------------------------------------------------- */
1775 /*------------------------------------------------------------------------------- */
1776 /* Function: in32 */
1777 /* Description: Input 32 bits */
1778 /*------------------------------------------------------------------------------- */
1784 /**************************************************************************/
1785 /* PPC405EP specific stuff */
1786 /**************************************************************************/
1790 #ifdef CONFIG_BUBINGA
1792 * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1793 * function) to support FPGA and NVRAM accesses below.
1796 lis r3,GPIO0_OSRH@h /* config GPIO output select */
1797 ori r3,r3,GPIO0_OSRH@l
1798 lis r4,CONFIG_SYS_GPIO0_OSRH@h
1799 ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l
1802 ori r3,r3,GPIO0_OSRL@l
1803 lis r4,CONFIG_SYS_GPIO0_OSRL@h
1804 ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l
1807 lis r3,GPIO0_ISR1H@h /* config GPIO input select */
1808 ori r3,r3,GPIO0_ISR1H@l
1809 lis r4,CONFIG_SYS_GPIO0_ISR1H@h
1810 ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l
1812 lis r3,GPIO0_ISR1L@h
1813 ori r3,r3,GPIO0_ISR1L@l
1814 lis r4,CONFIG_SYS_GPIO0_ISR1L@h
1815 ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l
1818 lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
1819 ori r3,r3,GPIO0_TSRH@l
1820 lis r4,CONFIG_SYS_GPIO0_TSRH@h
1821 ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l
1824 ori r3,r3,GPIO0_TSRL@l
1825 lis r4,CONFIG_SYS_GPIO0_TSRL@h
1826 ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l
1829 lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
1830 ori r3,r3,GPIO0_TCR@l
1831 lis r4,CONFIG_SYS_GPIO0_TCR@h
1832 ori r4,r4,CONFIG_SYS_GPIO0_TCR@l
1835 li r3,PB1AP /* program EBC bank 1 for RTC access */
1836 mtdcr EBC0_CFGADDR,r3
1837 lis r3,CONFIG_SYS_EBC_PB1AP@h
1838 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1839 mtdcr EBC0_CFGDATA,r3
1841 mtdcr EBC0_CFGADDR,r3
1842 lis r3,CONFIG_SYS_EBC_PB1CR@h
1843 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1844 mtdcr EBC0_CFGDATA,r3
1846 li r3,PB1AP /* program EBC bank 1 for RTC access */
1847 mtdcr EBC0_CFGADDR,r3
1848 lis r3,CONFIG_SYS_EBC_PB1AP@h
1849 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1850 mtdcr EBC0_CFGDATA,r3
1852 mtdcr EBC0_CFGADDR,r3
1853 lis r3,CONFIG_SYS_EBC_PB1CR@h
1854 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1855 mtdcr EBC0_CFGDATA,r3
1857 li r3,PB4AP /* program EBC bank 4 for FPGA access */
1858 mtdcr EBC0_CFGADDR,r3
1859 lis r3,CONFIG_SYS_EBC_PB4AP@h
1860 ori r3,r3,CONFIG_SYS_EBC_PB4AP@l
1861 mtdcr EBC0_CFGDATA,r3
1863 mtdcr EBC0_CFGADDR,r3
1864 lis r3,CONFIG_SYS_EBC_PB4CR@h
1865 ori r3,r3,CONFIG_SYS_EBC_PB4CR@l
1866 mtdcr EBC0_CFGDATA,r3
1870 !-----------------------------------------------------------------------
1871 ! Check to see if chip is in bypass mode.
1872 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1873 ! CPU reset Otherwise, skip this step and keep going.
1874 ! Note: Running BIOS in bypass mode is not supported since PLB speed
1875 ! will not be fast enough for the SDRAM (min 66MHz)
1876 !-----------------------------------------------------------------------
1878 mfdcr r5, CPC0_PLLMR1
1879 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
1882 beq pll_done /* if SSCS =b'1' then PLL has */
1883 /* already been set */
1884 /* and CPU has been reset */
1885 /* so skip to next section */
1887 #ifdef CONFIG_BUBINGA
1889 !-----------------------------------------------------------------------
1890 ! Read NVRAM to get value to write in PLLMR.
1891 ! If value has not been correctly saved, write default value
1892 ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1893 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1895 ! WARNING: This code assumes the first three words in the nvram_t
1896 ! structure in openbios.h. Changing the beginning of
1897 ! the structure will break this code.
1899 !-----------------------------------------------------------------------
1901 addis r3,0,NVRAM_BASE@h
1902 addi r3,r3,NVRAM_BASE@l
1905 addis r5,0,NVRVFY1@h
1906 addi r5,r5,NVRVFY1@l
1907 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
1911 addis r5,0,NVRVFY2@h
1912 addi r5,r5,NVRVFY2@l
1913 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
1915 addi r3,r3,8 /* Skip over conf_size */
1916 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1917 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1918 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1919 cmpi cr0,0,r5,1 /* See if PLL is locked */
1922 #endif /* CONFIG_BUBINGA */
1926 andi. r5, r4, CPC0_BOOT_SEP@l
1927 bne strap_1 /* serial eeprom present */
1928 addis r5,0,CPLD_REG0_ADDR@h
1929 ori r5,r5,CPLD_REG0_ADDR@l
1932 #endif /* CONFIG_TAIHU */
1934 #if defined(CONFIG_ZEUS)
1936 andi. r5, r4, CPC0_BOOT_SEP@l
1937 bne strap_1 /* serial eeprom present */
1944 mfdcr r3, CPC0_PLLMR0
1945 mfdcr r4, CPC0_PLLMR1
1949 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1950 ori r3,r3,PLLMR0_DEFAULT@l /* */
1951 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1952 ori r4,r4,PLLMR1_DEFAULT@l /* */
1957 addis r3,0,PLLMR0_DEFAULT_PCI66@h
1958 ori r3,r3,PLLMR0_DEFAULT_PCI66@l
1959 addis r4,0,PLLMR1_DEFAULT_PCI66@h
1960 ori r4,r4,PLLMR1_DEFAULT_PCI66@l
1963 mfdcr r3, CPC0_PLLMR0
1964 mfdcr r4, CPC0_PLLMR1
1965 #endif /* CONFIG_TAIHU */
1968 b pll_write /* Write the CPC0_PLLMR with new value */
1972 !-----------------------------------------------------------------------
1973 ! Clear Soft Reset Register
1974 ! This is needed to enable PCI if not booting from serial EPROM
1975 !-----------------------------------------------------------------------
1985 blr /* return to main code */
1988 !-----------------------------------------------------------------------------
1989 ! Function: pll_write
1990 ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
1992 ! 1. Pll is first disabled (de-activated by putting in bypass mode)
1994 ! 3. Clock dividers are set while PLL is held in reset and bypassed
1995 ! 4. PLL Reset is cleared
1996 ! 5. Wait 100us for PLL to lock
1997 ! 6. A core reset is performed
1998 ! Input: r3 = Value to write to CPC0_PLLMR0
1999 ! Input: r4 = Value to write to CPC0_PLLMR1
2001 !-----------------------------------------------------------------------------
2007 ori r5,r5,0x0101 /* Stop the UART clocks */
2008 mtdcr CPC0_UCR,r5 /* Before changing PLL */
2010 mfdcr r5, CPC0_PLLMR1
2011 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
2012 mtdcr CPC0_PLLMR1,r5
2013 oris r5,r5,0x4000 /* Set PLL Reset */
2014 mtdcr CPC0_PLLMR1,r5
2016 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
2017 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
2018 oris r5,r5,0x4000 /* Set PLL Reset */
2019 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
2020 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
2021 mtdcr CPC0_PLLMR1,r5
2024 ! Wait min of 100us for PLL to lock.
2025 ! See CMOS 27E databook for more info.
2026 ! At 200MHz, that means waiting 20,000 instructions
2028 addi r3,0,20000 /* 2000 = 0x4e20 */
2033 oris r5,r5,0x8000 /* Enable PLL */
2034 mtdcr CPC0_PLLMR1,r5 /* Engage */
2037 * Reset CPU to guarantee timings are OK
2038 * Not sure if this is needed...
2041 mtspr SPRN_DBCR0,r3 /* This will cause a CPU core reset, and */
2042 /* execution will continue from the poweron */
2043 /* vector of 0xfffffffc */
2044 #endif /* CONFIG_405EP */
2046 #if defined(CONFIG_440)
2047 /*----------------------------------------------------------------------------+
2049 +----------------------------------------------------------------------------*/
2050 function_prolog(mttlb3)
2053 function_epilog(mttlb3)
2055 /*----------------------------------------------------------------------------+
2057 +----------------------------------------------------------------------------*/
2058 function_prolog(mftlb3)
2061 function_epilog(mftlb3)
2063 /*----------------------------------------------------------------------------+
2065 +----------------------------------------------------------------------------*/
2066 function_prolog(mttlb2)
2069 function_epilog(mttlb2)
2071 /*----------------------------------------------------------------------------+
2073 +----------------------------------------------------------------------------*/
2074 function_prolog(mftlb2)
2077 function_epilog(mftlb2)
2079 /*----------------------------------------------------------------------------+
2081 +----------------------------------------------------------------------------*/
2082 function_prolog(mttlb1)
2085 function_epilog(mttlb1)
2087 /*----------------------------------------------------------------------------+
2089 +----------------------------------------------------------------------------*/
2090 function_prolog(mftlb1)
2093 function_epilog(mftlb1)
2094 #endif /* CONFIG_440 */
2096 #if defined(CONFIG_NAND_SPL)
2098 * void nand_boot_relocate(dst, src, bytes)
2100 * r3 = Destination address to copy code to (in SDRAM)
2101 * r4 = Source address to copy code from
2102 * r5 = size to copy in bytes
2110 * Copy SPL from icache into SDRAM
2122 * Calculate "corrected" link register, so that we "continue"
2123 * in execution in destination range
2125 sub r3,r7,r6 /* r3 = src - dst */
2126 sub r8,r8,r3 /* r8 = link-reg - (src - dst) */
2132 * First initialize SDRAM. It has to be available *before* calling
2135 lis r3,CONFIG_SYS_SDRAM_BASE@h
2136 ori r3,r3,CONFIG_SYS_SDRAM_BASE@l
2140 * Now copy the 4k SPL code into SDRAM and continue execution
2143 lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h
2144 ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l
2145 lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h
2146 ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l
2147 lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h
2148 ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l
2149 bl nand_boot_relocate
2152 * We're running from SDRAM now!!!
2154 * It is necessary for 4xx systems to relocate from running at
2155 * the original location (0xfffffxxx) to somewhere else (SDRAM
2156 * preferably). This is because CS0 needs to be reconfigured for
2157 * NAND access. And we can't reconfigure this CS when currently
2158 * "running" from it.
2162 * Finally call nand_boot() to load main NAND U-Boot image from
2163 * NAND and jump to it.
2165 bl nand_boot /* will not return */
2166 #endif /* CONFIG_NAND_SPL */