arch/powerpc/include/asm/opal.h

   1 /*
   2  * PowerNV OPAL definitions.
   3  *
   4  * Copyright 2011 IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #ifndef __OPAL_H
  13 #define __OPAL_H
  14
  15 /****** Takeover interface ********/
  16
  17 /* PAPR H-Call used to querty the HAL existence and/or instanciate
  18  * it from within pHyp (tech preview only).
  19  *
  20  * This is exclusively used in prom_init.c
  21  */
  22
  23 #ifndef __ASSEMBLY__
  24
  25 struct opal_takeover_args {
  26         u64     k_image;                /* r4 */
  27         u64     k_size;                 /* r5 */
  28         u64     k_entry;                /* r6 */
  29         u64     k_entry2;               /* r7 */
  30         u64     hal_addr;               /* r8 */
  31         u64     rd_image;               /* r9 */
  32         u64     rd_size;                /* r10 */
  33         u64     rd_loc;                 /* r11 */
  34 };
  35
  36 extern long opal_query_takeover(u64 *hal_size, u64 *hal_align);
  37
  38 extern long opal_do_takeover(struct opal_takeover_args *args);
  39
  40 struct rtas_args;
  41 extern int opal_enter_rtas(struct rtas_args *args,
  42                            unsigned long data,
  43                            unsigned long entry);
  44
  45 #endif /* __ASSEMBLY__ */
  46
  47 /****** OPAL APIs ******/
  48
  49 /* Return codes */
  50 #define OPAL_SUCCESS            0
  51 #define OPAL_PARAMETER          -1
  52 #define OPAL_BUSY               -2
  53 #define OPAL_PARTIAL            -3
  54 #define OPAL_CONSTRAINED        -4
  55 #define OPAL_CLOSED             -5
  56 #define OPAL_HARDWARE           -6
  57 #define OPAL_UNSUPPORTED        -7
  58 #define OPAL_PERMISSION         -8
  59 #define OPAL_NO_MEM             -9
  60 #define OPAL_RESOURCE           -10
  61 #define OPAL_INTERNAL_ERROR     -11
  62 #define OPAL_BUSY_EVENT         -12
  63 #define OPAL_HARDWARE_FROZEN    -13
  64
  65 /* API Tokens (in r0) */
  66 #define OPAL_CONSOLE_WRITE                      1
  67 #define OPAL_CONSOLE_READ                       2
  68 #define OPAL_RTC_READ                           3
  69 #define OPAL_RTC_WRITE                          4
  70 #define OPAL_CEC_POWER_DOWN                     5
  71 #define OPAL_CEC_REBOOT                         6
  72 #define OPAL_READ_NVRAM                         7
  73 #define OPAL_WRITE_NVRAM                        8
  74 #define OPAL_HANDLE_INTERRUPT                   9
  75 #define OPAL_POLL_EVENTS                        10
  76 #define OPAL_PCI_SET_HUB_TCE_MEMORY             11
  77 #define OPAL_PCI_SET_PHB_TCE_MEMORY             12
  78 #define OPAL_PCI_CONFIG_READ_BYTE               13
  79 #define OPAL_PCI_CONFIG_READ_HALF_WORD          14
  80 #define OPAL_PCI_CONFIG_READ_WORD               15
  81 #define OPAL_PCI_CONFIG_WRITE_BYTE              16
  82 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD         17
  83 #define OPAL_PCI_CONFIG_WRITE_WORD              18
  84 #define OPAL_SET_XIVE                           19
  85 #define OPAL_GET_XIVE                           20
  86 #define OPAL_GET_COMPLETION_TOKEN_STATUS        21 /* obsolete */
  87 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER    22
  88 #define OPAL_PCI_EEH_FREEZE_STATUS              23
  89 #define OPAL_PCI_SHPC                           24
  90 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE         25
  91 #define OPAL_PCI_EEH_FREEZE_CLEAR               26
  92 #define OPAL_PCI_PHB_MMIO_ENABLE                27
  93 #define OPAL_PCI_SET_PHB_MEM_WINDOW             28
  94 #define OPAL_PCI_MAP_PE_MMIO_WINDOW             29
  95 #define OPAL_PCI_SET_PHB_TABLE_MEMORY           30
  96 #define OPAL_PCI_SET_PE                         31
  97 #define OPAL_PCI_SET_PELTV                      32
  98 #define OPAL_PCI_SET_MVE                        33
  99 #define OPAL_PCI_SET_MVE_ENABLE                 34
 100 #define OPAL_PCI_GET_XIVE_REISSUE               35
 101 #define OPAL_PCI_SET_XIVE_REISSUE               36
 102 #define OPAL_PCI_SET_XIVE_PE                    37
 103 #define OPAL_GET_XIVE_SOURCE                    38
 104 #define OPAL_GET_MSI_32                         39
 105 #define OPAL_GET_MSI_64                         40
 106 #define OPAL_START_CPU                          41
 107 #define OPAL_QUERY_CPU_STATUS                   42
 108 #define OPAL_WRITE_OPPANEL                      43
 109 #define OPAL_PCI_MAP_PE_DMA_WINDOW              44
 110 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL         45
 111 #define OPAL_PCI_RESET                          49
 112 #define OPAL_PCI_GET_HUB_DIAG_DATA              50
 113 #define OPAL_PCI_GET_PHB_DIAG_DATA              51
 114 #define OPAL_PCI_FENCE_PHB                      52
 115 #define OPAL_PCI_REINIT                         53
 116 #define OPAL_PCI_MASK_PE_ERROR                  54
 117 #define OPAL_SET_SLOT_LED_STATUS                55
 118 #define OPAL_GET_EPOW_STATUS                    56
 119 #define OPAL_SET_SYSTEM_ATTENTION_LED           57
 120 #define OPAL_RESERVED1                          58
 121 #define OPAL_RESERVED2                          59
 122 #define OPAL_PCI_NEXT_ERROR                     60
 123 #define OPAL_PCI_EEH_FREEZE_STATUS2             61
 124 #define OPAL_PCI_POLL                           62
 125 #define OPAL_PCI_MSI_EOI                        63
 126 #define OPAL_PCI_GET_PHB_DIAG_DATA2             64
 127 #define OPAL_XSCOM_READ                         65
 128 #define OPAL_XSCOM_WRITE                        66
 129 #define OPAL_LPC_READ                           67
 130 #define OPAL_LPC_WRITE                          68
 131 #define OPAL_RETURN_CPU                         69
 132
 133 #ifndef __ASSEMBLY__
 134
 135 /* Other enums */
 136 enum OpalVendorApiTokens {
 137         OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999
 138 };
 139
 140 enum OpalFreezeState {
 141         OPAL_EEH_STOPPED_NOT_FROZEN = 0,
 142         OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
 143         OPAL_EEH_STOPPED_DMA_FREEZE = 2,
 144         OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
 145         OPAL_EEH_STOPPED_RESET = 4,
 146         OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
 147         OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
 148 };
 149
 150 enum OpalEehFreezeActionToken {
 151         OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
 152         OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
 153         OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3
 154 };
 155
 156 enum OpalPciStatusToken {
 157         OPAL_EEH_NO_ERROR       = 0,
 158         OPAL_EEH_IOC_ERROR      = 1,
 159         OPAL_EEH_PHB_ERROR      = 2,
 160         OPAL_EEH_PE_ERROR       = 3,
 161         OPAL_EEH_PE_MMIO_ERROR  = 4,
 162         OPAL_EEH_PE_DMA_ERROR   = 5
 163 };
 164
 165 enum OpalPciErrorSeverity {
 166         OPAL_EEH_SEV_NO_ERROR   = 0,
 167         OPAL_EEH_SEV_IOC_DEAD   = 1,
 168         OPAL_EEH_SEV_PHB_DEAD   = 2,
 169         OPAL_EEH_SEV_PHB_FENCED = 3,
 170         OPAL_EEH_SEV_PE_ER      = 4,
 171         OPAL_EEH_SEV_INF        = 5
 172 };
 173
 174 enum OpalShpcAction {
 175         OPAL_SHPC_GET_LINK_STATE = 0,
 176         OPAL_SHPC_GET_SLOT_STATE = 1
 177 };
 178
 179 enum OpalShpcLinkState {
 180         OPAL_SHPC_LINK_DOWN = 0,
 181         OPAL_SHPC_LINK_UP = 1
 182 };
 183
 184 enum OpalMmioWindowType {
 185         OPAL_M32_WINDOW_TYPE = 1,
 186         OPAL_M64_WINDOW_TYPE = 2,
 187         OPAL_IO_WINDOW_TYPE = 3
 188 };
 189
 190 enum OpalShpcSlotState {
 191         OPAL_SHPC_DEV_NOT_PRESENT = 0,
 192         OPAL_SHPC_DEV_PRESENT = 1
 193 };
 194
 195 enum OpalExceptionHandler {
 196         OPAL_MACHINE_CHECK_HANDLER = 1,
 197         OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
 198         OPAL_SOFTPATCH_HANDLER = 3
 199 };
 200
 201 enum OpalPendingState {
 202         OPAL_EVENT_OPAL_INTERNAL        = 0x1,
 203         OPAL_EVENT_NVRAM                = 0x2,
 204         OPAL_EVENT_RTC                  = 0x4,
 205         OPAL_EVENT_CONSOLE_OUTPUT       = 0x8,
 206         OPAL_EVENT_CONSOLE_INPUT        = 0x10,
 207         OPAL_EVENT_ERROR_LOG_AVAIL      = 0x20,
 208         OPAL_EVENT_ERROR_LOG            = 0x40,
 209         OPAL_EVENT_EPOW                 = 0x80,
 210         OPAL_EVENT_LED_STATUS           = 0x100,
 211         OPAL_EVENT_PCI_ERROR            = 0x200
 212 };
 213
 214 /* Machine check related definitions */
 215 enum OpalMCE_Version {
 216         OpalMCE_V1 = 1,
 217 };
 218
 219 enum OpalMCE_Severity {
 220         OpalMCE_SEV_NO_ERROR = 0,
 221         OpalMCE_SEV_WARNING = 1,
 222         OpalMCE_SEV_ERROR_SYNC = 2,
 223         OpalMCE_SEV_FATAL = 3,
 224 };
 225
 226 enum OpalMCE_Disposition {
 227         OpalMCE_DISPOSITION_RECOVERED = 0,
 228         OpalMCE_DISPOSITION_NOT_RECOVERED = 1,
 229 };
 230
 231 enum OpalMCE_Initiator {
 232         OpalMCE_INITIATOR_UNKNOWN = 0,
 233         OpalMCE_INITIATOR_CPU = 1,
 234 };
 235
 236 enum OpalMCE_ErrorType {
 237         OpalMCE_ERROR_TYPE_UNKNOWN = 0,
 238         OpalMCE_ERROR_TYPE_UE = 1,
 239         OpalMCE_ERROR_TYPE_SLB = 2,
 240         OpalMCE_ERROR_TYPE_ERAT = 3,
 241         OpalMCE_ERROR_TYPE_TLB = 4,
 242 };
 243
 244 enum OpalMCE_UeErrorType {
 245         OpalMCE_UE_ERROR_INDETERMINATE = 0,
 246         OpalMCE_UE_ERROR_IFETCH = 1,
 247         OpalMCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
 248         OpalMCE_UE_ERROR_LOAD_STORE = 3,
 249         OpalMCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4,
 250 };
 251
 252 enum OpalMCE_SlbErrorType {
 253         OpalMCE_SLB_ERROR_INDETERMINATE = 0,
 254         OpalMCE_SLB_ERROR_PARITY = 1,
 255         OpalMCE_SLB_ERROR_MULTIHIT = 2,
 256 };
 257
 258 enum OpalMCE_EratErrorType {
 259         OpalMCE_ERAT_ERROR_INDETERMINATE = 0,
 260         OpalMCE_ERAT_ERROR_PARITY = 1,
 261         OpalMCE_ERAT_ERROR_MULTIHIT = 2,
 262 };
 263
 264 enum OpalMCE_TlbErrorType {
 265         OpalMCE_TLB_ERROR_INDETERMINATE = 0,
 266         OpalMCE_TLB_ERROR_PARITY = 1,
 267         OpalMCE_TLB_ERROR_MULTIHIT = 2,
 268 };
 269
 270 enum OpalThreadStatus {
 271         OPAL_THREAD_INACTIVE = 0x0,
 272         OPAL_THREAD_STARTED = 0x1,
 273         OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
 274 };
 275
 276 enum OpalPciBusCompare {
 277         OpalPciBusAny   = 0,    /* Any bus number match */
 278         OpalPciBus3Bits = 2,    /* Match top 3 bits of bus number */
 279         OpalPciBus4Bits = 3,    /* Match top 4 bits of bus number */
 280         OpalPciBus5Bits = 4,    /* Match top 5 bits of bus number */
 281         OpalPciBus6Bits = 5,    /* Match top 6 bits of bus number */
 282         OpalPciBus7Bits = 6,    /* Match top 7 bits of bus number */
 283         OpalPciBusAll   = 7,    /* Match bus number exactly */
 284 };
 285
 286 enum OpalDeviceCompare {
 287         OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
 288         OPAL_COMPARE_RID_DEVICE_NUMBER = 1
 289 };
 290
 291 enum OpalFuncCompare {
 292         OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
 293         OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
 294 };
 295
 296 enum OpalPeAction {
 297         OPAL_UNMAP_PE = 0,
 298         OPAL_MAP_PE = 1
 299 };
 300
 301 enum OpalPeltvAction {
 302         OPAL_REMOVE_PE_FROM_DOMAIN = 0,
 303         OPAL_ADD_PE_TO_DOMAIN = 1
 304 };
 305
 306 enum OpalMveEnableAction {
 307         OPAL_DISABLE_MVE = 0,
 308         OPAL_ENABLE_MVE = 1
 309 };
 310
 311 enum OpalPciResetAndReinitScope {
 312         OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
 313         OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
 314         OPAL_PCI_IODA_TABLE_RESET = 6,
 315 };
 316
 317 enum OpalPciResetState {
 318         OPAL_DEASSERT_RESET = 0,
 319         OPAL_ASSERT_RESET = 1
 320 };
 321
 322 enum OpalPciMaskAction {
 323         OPAL_UNMASK_ERROR_TYPE = 0,
 324         OPAL_MASK_ERROR_TYPE = 1
 325 };
 326
 327 enum OpalSlotLedType {
 328         OPAL_SLOT_LED_ID_TYPE = 0,
 329         OPAL_SLOT_LED_FAULT_TYPE = 1
 330 };
 331
 332 enum OpalLedAction {
 333         OPAL_TURN_OFF_LED = 0,
 334         OPAL_TURN_ON_LED = 1,
 335         OPAL_QUERY_LED_STATE_AFTER_BUSY = 2
 336 };
 337
 338 enum OpalEpowStatus {
 339         OPAL_EPOW_NONE = 0,
 340         OPAL_EPOW_UPS = 1,
 341         OPAL_EPOW_OVER_AMBIENT_TEMP = 2,
 342         OPAL_EPOW_OVER_INTERNAL_TEMP = 3
 343 };
 344
 345 /*
 346  * Address cycle types for LPC accesses. These also correspond
 347  * to the content of the first cell of the "reg" property for
 348  * device nodes on the LPC bus
 349  */
 350 enum OpalLPCAddressType {
 351         OPAL_LPC_MEM    = 0,
 352         OPAL_LPC_IO     = 1,
 353         OPAL_LPC_FW     = 2,
 354 };
 355
 356 struct opal_machine_check_event {
 357         enum OpalMCE_Version    version:8;      /* 0x00 */
 358         uint8_t                 in_use;         /* 0x01 */
 359         enum OpalMCE_Severity   severity:8;     /* 0x02 */
 360         enum OpalMCE_Initiator  initiator:8;    /* 0x03 */
 361         enum OpalMCE_ErrorType  error_type:8;   /* 0x04 */
 362         enum OpalMCE_Disposition disposition:8; /* 0x05 */
 363         uint8_t                 reserved_1[2];  /* 0x06 */
 364         uint64_t                gpr3;           /* 0x08 */
 365         uint64_t                srr0;           /* 0x10 */
 366         uint64_t                srr1;           /* 0x18 */
 367         union {                                 /* 0x20 */
 368                 struct {
 369                         enum OpalMCE_UeErrorType ue_error_type:8;
 370                         uint8_t         effective_address_provided;
 371                         uint8_t         physical_address_provided;
 372                         uint8_t         reserved_1[5];
 373                         uint64_t        effective_address;
 374                         uint64_t        physical_address;
 375                         uint8_t         reserved_2[8];
 376                 } ue_error;
 377
 378                 struct {
 379                         enum OpalMCE_SlbErrorType slb_error_type:8;
 380                         uint8_t         effective_address_provided;
 381                         uint8_t         reserved_1[6];
 382                         uint64_t        effective_address;
 383                         uint8_t         reserved_2[16];
 384                 } slb_error;
 385
 386                 struct {
 387                         enum OpalMCE_EratErrorType erat_error_type:8;
 388                         uint8_t         effective_address_provided;
 389                         uint8_t         reserved_1[6];
 390                         uint64_t        effective_address;
 391                         uint8_t         reserved_2[16];
 392                 } erat_error;
 393
 394                 struct {
 395                         enum OpalMCE_TlbErrorType tlb_error_type:8;
 396                         uint8_t         effective_address_provided;
 397                         uint8_t         reserved_1[6];
 398                         uint64_t        effective_address;
 399                         uint8_t         reserved_2[16];
 400                 } tlb_error;
 401         } u;
 402 };
 403
 404 enum {
 405         OPAL_P7IOC_DIAG_TYPE_NONE       = 0,
 406         OPAL_P7IOC_DIAG_TYPE_RGC        = 1,
 407         OPAL_P7IOC_DIAG_TYPE_BI         = 2,
 408         OPAL_P7IOC_DIAG_TYPE_CI         = 3,
 409         OPAL_P7IOC_DIAG_TYPE_MISC       = 4,
 410         OPAL_P7IOC_DIAG_TYPE_I2C        = 5,
 411         OPAL_P7IOC_DIAG_TYPE_LAST       = 6
 412 };
 413
 414 struct OpalIoP7IOCErrorData {
 415         uint16_t type;
 416
 417         /* GEM */
 418         uint64_t gemXfir;
 419         uint64_t gemRfir;
 420         uint64_t gemRirqfir;
 421         uint64_t gemMask;
 422         uint64_t gemRwof;
 423
 424         /* LEM */
 425         uint64_t lemFir;
 426         uint64_t lemErrMask;
 427         uint64_t lemAction0;
 428         uint64_t lemAction1;
 429         uint64_t lemWof;
 430
 431         union {
 432                 struct OpalIoP7IOCRgcErrorData {
 433                         uint64_t rgcStatus;             /* 3E1C10 */
 434                         uint64_t rgcLdcp;               /* 3E1C18 */
 435                 }rgc;
 436                 struct OpalIoP7IOCBiErrorData {
 437                         uint64_t biLdcp0;               /* 3C0100, 3C0118 */
 438                         uint64_t biLdcp1;               /* 3C0108, 3C0120 */
 439                         uint64_t biLdcp2;               /* 3C0110, 3C0128 */
 440                         uint64_t biFenceStatus;         /* 3C0130, 3C0130 */
 441
 442                         uint8_t  biDownbound;           /* BI Downbound or Upbound */
 443                 }bi;
 444                 struct OpalIoP7IOCCiErrorData {
 445                         uint64_t ciPortStatus;          /* 3Dn008 */
 446                         uint64_t ciPortLdcp;            /* 3Dn010 */
 447
 448                         uint8_t  ciPort;                /* Index of CI port: 0/1 */
 449                 }ci;
 450         };
 451 };
 452
 453 /**
 454  * This structure defines the overlay which will be used to store PHB error
 455  * data upon request.
 456  */
 457 enum {
 458         OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
 459 };
 460
 461 enum {
 462         OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
 463         OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2
 464 };
 465
 466 enum {
 467         OPAL_P7IOC_NUM_PEST_REGS = 128,
 468         OPAL_PHB3_NUM_PEST_REGS = 256
 469 };
 470
 471 struct OpalIoPhbErrorCommon {
 472         uint32_t version;
 473         uint32_t ioType;
 474         uint32_t len;
 475 };
 476
 477 struct OpalIoP7IOCPhbErrorData {
 478         struct OpalIoPhbErrorCommon common;
 479
 480         uint32_t brdgCtl;
 481
 482         // P7IOC utl regs
 483         uint32_t portStatusReg;
 484         uint32_t rootCmplxStatus;
 485         uint32_t busAgentStatus;
 486
 487         // P7IOC cfg regs
 488         uint32_t deviceStatus;
 489         uint32_t slotStatus;
 490         uint32_t linkStatus;
 491         uint32_t devCmdStatus;
 492         uint32_t devSecStatus;
 493
 494         // cfg AER regs
 495         uint32_t rootErrorStatus;
 496         uint32_t uncorrErrorStatus;
 497         uint32_t corrErrorStatus;
 498         uint32_t tlpHdr1;
 499         uint32_t tlpHdr2;
 500         uint32_t tlpHdr3;
 501         uint32_t tlpHdr4;
 502         uint32_t sourceId;
 503
 504         uint32_t rsv3;
 505
 506         // Record data about the call to allocate a buffer.
 507         uint64_t errorClass;
 508         uint64_t correlator;
 509
 510         //P7IOC MMIO Error Regs
 511         uint64_t p7iocPlssr;                // n120
 512         uint64_t p7iocCsr;                  // n110
 513         uint64_t lemFir;                    // nC00
 514         uint64_t lemErrorMask;              // nC18
 515         uint64_t lemWOF;                    // nC40
 516         uint64_t phbErrorStatus;            // nC80
 517         uint64_t phbFirstErrorStatus;       // nC88
 518         uint64_t phbErrorLog0;              // nCC0
 519         uint64_t phbErrorLog1;              // nCC8
 520         uint64_t mmioErrorStatus;           // nD00
 521         uint64_t mmioFirstErrorStatus;      // nD08
 522         uint64_t mmioErrorLog0;             // nD40
 523         uint64_t mmioErrorLog1;             // nD48
 524         uint64_t dma0ErrorStatus;           // nD80
 525         uint64_t dma0FirstErrorStatus;      // nD88
 526         uint64_t dma0ErrorLog0;             // nDC0
 527         uint64_t dma0ErrorLog1;             // nDC8
 528         uint64_t dma1ErrorStatus;           // nE00
 529         uint64_t dma1FirstErrorStatus;      // nE08
 530         uint64_t dma1ErrorLog0;             // nE40
 531         uint64_t dma1ErrorLog1;             // nE48
 532         uint64_t pestA[OPAL_P7IOC_NUM_PEST_REGS];
 533         uint64_t pestB[OPAL_P7IOC_NUM_PEST_REGS];
 534 };
 535
 536 struct OpalIoPhb3ErrorData {
 537         struct OpalIoPhbErrorCommon common;
 538
 539         uint32_t brdgCtl;
 540
 541         /* PHB3 UTL regs */
 542         uint32_t portStatusReg;
 543         uint32_t rootCmplxStatus;
 544         uint32_t busAgentStatus;
 545
 546         /* PHB3 cfg regs */
 547         uint32_t deviceStatus;
 548         uint32_t slotStatus;
 549         uint32_t linkStatus;
 550         uint32_t devCmdStatus;
 551         uint32_t devSecStatus;
 552
 553         /* cfg AER regs */
 554         uint32_t rootErrorStatus;
 555         uint32_t uncorrErrorStatus;
 556         uint32_t corrErrorStatus;
 557         uint32_t tlpHdr1;
 558         uint32_t tlpHdr2;
 559         uint32_t tlpHdr3;
 560         uint32_t tlpHdr4;
 561         uint32_t sourceId;
 562
 563         uint32_t rsv3;
 564
 565         /* Record data about the call to allocate a buffer */
 566         uint64_t errorClass;
 567         uint64_t correlator;
 568
 569         uint64_t nFir;                  /* 000 */
 570         uint64_t nFirMask;              /* 003 */
 571         uint64_t nFirWOF;               /* 008 */
 572
 573         /* PHB3 MMIO Error Regs */
 574         uint64_t phbPlssr;              /* 120 */
 575         uint64_t phbCsr;                /* 110 */
 576         uint64_t lemFir;                /* C00 */
 577         uint64_t lemErrorMask;          /* C18 */
 578         uint64_t lemWOF;                /* C40 */
 579         uint64_t phbErrorStatus;        /* C80 */
 580         uint64_t phbFirstErrorStatus;   /* C88 */
 581         uint64_t phbErrorLog0;          /* CC0 */
 582         uint64_t phbErrorLog1;          /* CC8 */
 583         uint64_t mmioErrorStatus;       /* D00 */
 584         uint64_t mmioFirstErrorStatus;  /* D08 */
 585         uint64_t mmioErrorLog0;         /* D40 */
 586         uint64_t mmioErrorLog1;         /* D48 */
 587         uint64_t dma0ErrorStatus;       /* D80 */
 588         uint64_t dma0FirstErrorStatus;  /* D88 */
 589         uint64_t dma0ErrorLog0;         /* DC0 */
 590         uint64_t dma0ErrorLog1;         /* DC8 */
 591         uint64_t dma1ErrorStatus;       /* E00 */
 592         uint64_t dma1FirstErrorStatus;  /* E08 */
 593         uint64_t dma1ErrorLog0;         /* E40 */
 594         uint64_t dma1ErrorLog1;         /* E48 */
 595         uint64_t pestA[OPAL_PHB3_NUM_PEST_REGS];
 596         uint64_t pestB[OPAL_PHB3_NUM_PEST_REGS];
 597 };
 598
 599 typedef struct oppanel_line {
 600         const char *    line;
 601         uint64_t        line_len;
 602 } oppanel_line_t;
 603
 604 /* API functions */
 605 int64_t opal_console_write(int64_t term_number, __be64 *length,
 606                            const uint8_t *buffer);
 607 int64_t opal_console_read(int64_t term_number, __be64 *length,
 608                           uint8_t *buffer);
 609 int64_t opal_console_write_buffer_space(int64_t term_number,
 610                                         __be64 *length);
 611 int64_t opal_rtc_read(__be32 *year_month_day,
 612                       __be64 *hour_minute_second_millisecond);
 613 int64_t opal_rtc_write(uint32_t year_month_day,
 614                        uint64_t hour_minute_second_millisecond);
 615 int64_t opal_cec_power_down(uint64_t request);
 616 int64_t opal_cec_reboot(void);
 617 int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
 618 int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
 619 int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask);
 620 int64_t opal_poll_events(__be64 *outstanding_event_mask);
 621 int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
 622                                     uint64_t tce_mem_size);
 623 int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
 624                                     uint64_t tce_mem_size);
 625 int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
 626                                   uint64_t offset, uint8_t *data);
 627 int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
 628                                        uint64_t offset, __be16 *data);
 629 int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
 630                                   uint64_t offset, __be32 *data);
 631 int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
 632                                    uint64_t offset, uint8_t data);
 633 int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
 634                                         uint64_t offset, uint16_t data);
 635 int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
 636                                    uint64_t offset, uint32_t data);
 637 int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
 638 int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority);
 639 int64_t opal_register_exception_handler(uint64_t opal_exception,
 640                                         uint64_t handler_address,
 641                                         uint64_t glue_cache_line);
 642 int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
 643                                    uint8_t *freeze_state,
 644                                    __be16 *pci_error_type,
 645                                    __be64 *phb_status);
 646 int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
 647                                   uint64_t eeh_action_token);
 648 int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
 649
 650
 651
 652 int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
 653                                  uint16_t window_num, uint16_t enable);
 654 int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
 655                                     uint16_t window_num,
 656                                     uint64_t starting_real_address,
 657                                     uint64_t starting_pci_address,
 658                                     uint16_t segment_size);
 659 int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
 660                                     uint16_t window_type, uint16_t window_num,
 661                                     uint16_t segment_num);
 662 int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
 663                                       uint64_t ivt_addr, uint64_t ivt_len,
 664                                       uint64_t reject_array_addr,
 665                                       uint64_t peltv_addr);
 666 int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
 667                         uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
 668                         uint8_t pe_action);
 669 int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
 670                            uint8_t state);
 671 int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
 672 int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
 673                                 uint32_t state);
 674 int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
 675                                   uint8_t *p_bit, uint8_t *q_bit);
 676 int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
 677                                   uint8_t p_bit, uint8_t q_bit);
 678 int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
 679 int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
 680                              uint32_t xive_num);
 681 int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
 682                              __be32 *interrupt_source_number);
 683 int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
 684                         uint8_t msi_range, __be32 *msi_address,
 685                         __be32 *message_data);
 686 int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
 687                         uint32_t xive_num, uint8_t msi_range,
 688                         __be64 *msi_address, __be32 *message_data);
 689 int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
 690 int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
 691 int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
 692 int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
 693                                    uint16_t tce_levels, uint64_t tce_table_addr,
 694                                    uint64_t tce_table_size, uint64_t tce_page_size);
 695 int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
 696                                         uint16_t dma_window_number, uint64_t pci_start_addr,
 697                                         uint64_t pci_mem_size);
 698 int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
 699
 700 int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
 701                                    uint64_t diag_buffer_len);
 702 int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
 703                                    uint64_t diag_buffer_len);
 704 int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
 705                                     uint64_t diag_buffer_len);
 706 int64_t opal_pci_fence_phb(uint64_t phb_id);
 707 int64_t opal_pci_reinit(uint64_t phb_id, uint8_t reinit_scope);
 708 int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
 709 int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
 710 int64_t opal_get_epow_status(__be64 *status);
 711 int64_t opal_set_system_attention_led(uint8_t led_action);
 712 int64_t opal_pci_next_error(uint64_t phb_id, uint64_t *first_frozen_pe,
 713                             uint16_t *pci_error_type, uint16_t *severity);
 714 int64_t opal_pci_poll(uint64_t phb_id);
 715 int64_t opal_return_cpu(void);
 716
 717 int64_t opal_xscom_read(uint32_t gcid, uint32_t pcb_addr, uint64_t *val);
 718 int64_t opal_xscom_write(uint32_t gcid, uint32_t pcb_addr, uint64_t val);
 719
 720 int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
 721                        uint32_t addr, uint32_t data, uint32_t sz);
 722 int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type,
 723                       uint32_t addr, uint32_t *data, uint32_t sz);
 724
 725 /* Internal functions */
 726 extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data);
 727
 728 extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
 729 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
 730
 731 extern void hvc_opal_init_early(void);
 732
 733 /* Internal functions */
 734 extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
 735                                    int depth, void *data);
 736
 737 extern int opal_notifier_register(struct notifier_block *nb);
 738 extern void opal_notifier_enable(void);
 739 extern void opal_notifier_disable(void);
 740 extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
 741
 742 extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
 743 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
 744
 745 extern void hvc_opal_init_early(void);
 746
 747 struct rtc_time;
 748 extern int opal_set_rtc_time(struct rtc_time *tm);
 749 extern void opal_get_rtc_time(struct rtc_time *tm);
 750 extern unsigned long opal_get_boot_time(void);
 751 extern void opal_nvram_init(void);
 752
 753 extern int opal_machine_check(struct pt_regs *regs);
 754
 755 extern void opal_shutdown(void);
 756
 757 extern void opal_lpc_init(void);
 758
 759 #endif /* __ASSEMBLY__ */
 760
 761 #endif /* __OPAL_H */