arch/powerpc/include/asm/opal.h

   1 /*
   2  * PowerNV OPAL definitions.
   3  *
   4  * Copyright 2011 IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #ifndef __OPAL_H
  13 #define __OPAL_H
  14
  15 /****** Takeover interface ********/
  16
  17 /* PAPR H-Call used to querty the HAL existence and/or instanciate
  18  * it from within pHyp (tech preview only).
  19  *
  20  * This is exclusively used in prom_init.c
  21  */
  22
  23 #ifndef __ASSEMBLY__
  24
  25 struct opal_takeover_args {
  26         u64     k_image;                /* r4 */
  27         u64     k_size;                 /* r5 */
  28         u64     k_entry;                /* r6 */
  29         u64     k_entry2;               /* r7 */
  30         u64     hal_addr;               /* r8 */
  31         u64     rd_image;               /* r9 */
  32         u64     rd_size;                /* r10 */
  33         u64     rd_loc;                 /* r11 */
  34 };
  35
  36 /*
  37  * SG entry
  38  *
  39  * WARNING: The current implementation requires each entry
  40  * to represent a block that is 4k aligned *and* each block
  41  * size except the last one in the list to be as well.
  42  */
  43 struct opal_sg_entry {
  44         void    *data;
  45         long    length;
  46 };
  47
  48 /* sg list */
  49 struct opal_sg_list {
  50         unsigned long num_entries;
  51         struct opal_sg_list *next;
  52         struct opal_sg_entry entry[];
  53 };
  54
  55 /* We calculate number of sg entries based on PAGE_SIZE */
  56 #define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry))
  57
  58 extern long opal_query_takeover(u64 *hal_size, u64 *hal_align);
  59
  60 extern long opal_do_takeover(struct opal_takeover_args *args);
  61
  62 struct rtas_args;
  63 extern int opal_enter_rtas(struct rtas_args *args,
  64                            unsigned long data,
  65                            unsigned long entry);
  66
  67 #endif /* __ASSEMBLY__ */
  68
  69 /****** OPAL APIs ******/
  70
  71 /* Return codes */
  72 #define OPAL_SUCCESS            0
  73 #define OPAL_PARAMETER          -1
  74 #define OPAL_BUSY               -2
  75 #define OPAL_PARTIAL            -3
  76 #define OPAL_CONSTRAINED        -4
  77 #define OPAL_CLOSED             -5
  78 #define OPAL_HARDWARE           -6
  79 #define OPAL_UNSUPPORTED        -7
  80 #define OPAL_PERMISSION         -8
  81 #define OPAL_NO_MEM             -9
  82 #define OPAL_RESOURCE           -10
  83 #define OPAL_INTERNAL_ERROR     -11
  84 #define OPAL_BUSY_EVENT         -12
  85 #define OPAL_HARDWARE_FROZEN    -13
  86 #define OPAL_WRONG_STATE        -14
  87 #define OPAL_ASYNC_COMPLETION   -15
  88
  89 /* API Tokens (in r0) */
  90 #define OPAL_INVALID_CALL                       -1
  91 #define OPAL_CONSOLE_WRITE                      1
  92 #define OPAL_CONSOLE_READ                       2
  93 #define OPAL_RTC_READ                           3
  94 #define OPAL_RTC_WRITE                          4
  95 #define OPAL_CEC_POWER_DOWN                     5
  96 #define OPAL_CEC_REBOOT                         6
  97 #define OPAL_READ_NVRAM                         7
  98 #define OPAL_WRITE_NVRAM                        8
  99 #define OPAL_HANDLE_INTERRUPT                   9
 100 #define OPAL_POLL_EVENTS                        10
 101 #define OPAL_PCI_SET_HUB_TCE_MEMORY             11
 102 #define OPAL_PCI_SET_PHB_TCE_MEMORY             12
 103 #define OPAL_PCI_CONFIG_READ_BYTE               13
 104 #define OPAL_PCI_CONFIG_READ_HALF_WORD          14
 105 #define OPAL_PCI_CONFIG_READ_WORD               15
 106 #define OPAL_PCI_CONFIG_WRITE_BYTE              16
 107 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD         17
 108 #define OPAL_PCI_CONFIG_WRITE_WORD              18
 109 #define OPAL_SET_XIVE                           19
 110 #define OPAL_GET_XIVE                           20
 111 #define OPAL_GET_COMPLETION_TOKEN_STATUS        21 /* obsolete */
 112 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER    22
 113 #define OPAL_PCI_EEH_FREEZE_STATUS              23
 114 #define OPAL_PCI_SHPC                           24
 115 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE         25
 116 #define OPAL_PCI_EEH_FREEZE_CLEAR               26
 117 #define OPAL_PCI_PHB_MMIO_ENABLE                27
 118 #define OPAL_PCI_SET_PHB_MEM_WINDOW             28
 119 #define OPAL_PCI_MAP_PE_MMIO_WINDOW             29
 120 #define OPAL_PCI_SET_PHB_TABLE_MEMORY           30
 121 #define OPAL_PCI_SET_PE                         31
 122 #define OPAL_PCI_SET_PELTV                      32
 123 #define OPAL_PCI_SET_MVE                        33
 124 #define OPAL_PCI_SET_MVE_ENABLE                 34
 125 #define OPAL_PCI_GET_XIVE_REISSUE               35
 126 #define OPAL_PCI_SET_XIVE_REISSUE               36
 127 #define OPAL_PCI_SET_XIVE_PE                    37
 128 #define OPAL_GET_XIVE_SOURCE                    38
 129 #define OPAL_GET_MSI_32                         39
 130 #define OPAL_GET_MSI_64                         40
 131 #define OPAL_START_CPU                          41
 132 #define OPAL_QUERY_CPU_STATUS                   42
 133 #define OPAL_WRITE_OPPANEL                      43
 134 #define OPAL_PCI_MAP_PE_DMA_WINDOW              44
 135 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL         45
 136 #define OPAL_PCI_RESET                          49
 137 #define OPAL_PCI_GET_HUB_DIAG_DATA              50
 138 #define OPAL_PCI_GET_PHB_DIAG_DATA              51
 139 #define OPAL_PCI_FENCE_PHB                      52
 140 #define OPAL_PCI_REINIT                         53
 141 #define OPAL_PCI_MASK_PE_ERROR                  54
 142 #define OPAL_SET_SLOT_LED_STATUS                55
 143 #define OPAL_GET_EPOW_STATUS                    56
 144 #define OPAL_SET_SYSTEM_ATTENTION_LED           57
 145 #define OPAL_RESERVED1                          58
 146 #define OPAL_RESERVED2                          59
 147 #define OPAL_PCI_NEXT_ERROR                     60
 148 #define OPAL_PCI_EEH_FREEZE_STATUS2             61
 149 #define OPAL_PCI_POLL                           62
 150 #define OPAL_PCI_MSI_EOI                        63
 151 #define OPAL_PCI_GET_PHB_DIAG_DATA2             64
 152 #define OPAL_XSCOM_READ                         65
 153 #define OPAL_XSCOM_WRITE                        66
 154 #define OPAL_LPC_READ                           67
 155 #define OPAL_LPC_WRITE                          68
 156 #define OPAL_RETURN_CPU                         69
 157 #define OPAL_ELOG_READ                          71
 158 #define OPAL_ELOG_WRITE                         72
 159 #define OPAL_ELOG_ACK                           73
 160 #define OPAL_ELOG_RESEND                        74
 161 #define OPAL_ELOG_SIZE                          75
 162 #define OPAL_FLASH_VALIDATE                     76
 163 #define OPAL_FLASH_MANAGE                       77
 164 #define OPAL_FLASH_UPDATE                       78
 165 #define OPAL_RESYNC_TIMEBASE                    79
 166 #define OPAL_DUMP_INIT                          81
 167 #define OPAL_DUMP_INFO                          82
 168 #define OPAL_DUMP_READ                          83
 169 #define OPAL_DUMP_ACK                           84
 170 #define OPAL_GET_MSG                            85
 171 #define OPAL_CHECK_ASYNC_COMPLETION             86
 172 #define OPAL_SYNC_HOST_REBOOT                   87
 173 #define OPAL_SENSOR_READ                        88
 174 #define OPAL_GET_PARAM                          89
 175 #define OPAL_SET_PARAM                          90
 176 #define OPAL_DUMP_RESEND                        91
 177 #define OPAL_DUMP_INFO2                         94
 178
 179 #ifndef __ASSEMBLY__
 180
 181 /* Other enums */
 182 enum OpalVendorApiTokens {
 183         OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999
 184 };
 185
 186 enum OpalFreezeState {
 187         OPAL_EEH_STOPPED_NOT_FROZEN = 0,
 188         OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
 189         OPAL_EEH_STOPPED_DMA_FREEZE = 2,
 190         OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
 191         OPAL_EEH_STOPPED_RESET = 4,
 192         OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
 193         OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
 194 };
 195
 196 enum OpalEehFreezeActionToken {
 197         OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
 198         OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
 199         OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3
 200 };
 201
 202 enum OpalPciStatusToken {
 203         OPAL_EEH_NO_ERROR       = 0,
 204         OPAL_EEH_IOC_ERROR      = 1,
 205         OPAL_EEH_PHB_ERROR      = 2,
 206         OPAL_EEH_PE_ERROR       = 3,
 207         OPAL_EEH_PE_MMIO_ERROR  = 4,
 208         OPAL_EEH_PE_DMA_ERROR   = 5
 209 };
 210
 211 enum OpalPciErrorSeverity {
 212         OPAL_EEH_SEV_NO_ERROR   = 0,
 213         OPAL_EEH_SEV_IOC_DEAD   = 1,
 214         OPAL_EEH_SEV_PHB_DEAD   = 2,
 215         OPAL_EEH_SEV_PHB_FENCED = 3,
 216         OPAL_EEH_SEV_PE_ER      = 4,
 217         OPAL_EEH_SEV_INF        = 5
 218 };
 219
 220 enum OpalShpcAction {
 221         OPAL_SHPC_GET_LINK_STATE = 0,
 222         OPAL_SHPC_GET_SLOT_STATE = 1
 223 };
 224
 225 enum OpalShpcLinkState {
 226         OPAL_SHPC_LINK_DOWN = 0,
 227         OPAL_SHPC_LINK_UP = 1
 228 };
 229
 230 enum OpalMmioWindowType {
 231         OPAL_M32_WINDOW_TYPE = 1,
 232         OPAL_M64_WINDOW_TYPE = 2,
 233         OPAL_IO_WINDOW_TYPE = 3
 234 };
 235
 236 enum OpalShpcSlotState {
 237         OPAL_SHPC_DEV_NOT_PRESENT = 0,
 238         OPAL_SHPC_DEV_PRESENT = 1
 239 };
 240
 241 enum OpalExceptionHandler {
 242         OPAL_MACHINE_CHECK_HANDLER = 1,
 243         OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
 244         OPAL_SOFTPATCH_HANDLER = 3
 245 };
 246
 247 enum OpalPendingState {
 248         OPAL_EVENT_OPAL_INTERNAL        = 0x1,
 249         OPAL_EVENT_NVRAM                = 0x2,
 250         OPAL_EVENT_RTC                  = 0x4,
 251         OPAL_EVENT_CONSOLE_OUTPUT       = 0x8,
 252         OPAL_EVENT_CONSOLE_INPUT        = 0x10,
 253         OPAL_EVENT_ERROR_LOG_AVAIL      = 0x20,
 254         OPAL_EVENT_ERROR_LOG            = 0x40,
 255         OPAL_EVENT_EPOW                 = 0x80,
 256         OPAL_EVENT_LED_STATUS           = 0x100,
 257         OPAL_EVENT_PCI_ERROR            = 0x200,
 258         OPAL_EVENT_DUMP_AVAIL           = 0x400,
 259         OPAL_EVENT_MSG_PENDING          = 0x800,
 260 };
 261
 262 enum OpalMessageType {
 263         OPAL_MSG_ASYNC_COMP = 0,        /* params[0] = token, params[1] = rc,
 264                                          * additional params function-specific
 265                                          */
 266         OPAL_MSG_MEM_ERR,
 267         OPAL_MSG_EPOW,
 268         OPAL_MSG_SHUTDOWN,
 269         OPAL_MSG_TYPE_MAX,
 270 };
 271
 272 /* Machine check related definitions */
 273 enum OpalMCE_Version {
 274         OpalMCE_V1 = 1,
 275 };
 276
 277 enum OpalMCE_Severity {
 278         OpalMCE_SEV_NO_ERROR = 0,
 279         OpalMCE_SEV_WARNING = 1,
 280         OpalMCE_SEV_ERROR_SYNC = 2,
 281         OpalMCE_SEV_FATAL = 3,
 282 };
 283
 284 enum OpalMCE_Disposition {
 285         OpalMCE_DISPOSITION_RECOVERED = 0,
 286         OpalMCE_DISPOSITION_NOT_RECOVERED = 1,
 287 };
 288
 289 enum OpalMCE_Initiator {
 290         OpalMCE_INITIATOR_UNKNOWN = 0,
 291         OpalMCE_INITIATOR_CPU = 1,
 292 };
 293
 294 enum OpalMCE_ErrorType {
 295         OpalMCE_ERROR_TYPE_UNKNOWN = 0,
 296         OpalMCE_ERROR_TYPE_UE = 1,
 297         OpalMCE_ERROR_TYPE_SLB = 2,
 298         OpalMCE_ERROR_TYPE_ERAT = 3,
 299         OpalMCE_ERROR_TYPE_TLB = 4,
 300 };
 301
 302 enum OpalMCE_UeErrorType {
 303         OpalMCE_UE_ERROR_INDETERMINATE = 0,
 304         OpalMCE_UE_ERROR_IFETCH = 1,
 305         OpalMCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
 306         OpalMCE_UE_ERROR_LOAD_STORE = 3,
 307         OpalMCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4,
 308 };
 309
 310 enum OpalMCE_SlbErrorType {
 311         OpalMCE_SLB_ERROR_INDETERMINATE = 0,
 312         OpalMCE_SLB_ERROR_PARITY = 1,
 313         OpalMCE_SLB_ERROR_MULTIHIT = 2,
 314 };
 315
 316 enum OpalMCE_EratErrorType {
 317         OpalMCE_ERAT_ERROR_INDETERMINATE = 0,
 318         OpalMCE_ERAT_ERROR_PARITY = 1,
 319         OpalMCE_ERAT_ERROR_MULTIHIT = 2,
 320 };
 321
 322 enum OpalMCE_TlbErrorType {
 323         OpalMCE_TLB_ERROR_INDETERMINATE = 0,
 324         OpalMCE_TLB_ERROR_PARITY = 1,
 325         OpalMCE_TLB_ERROR_MULTIHIT = 2,
 326 };
 327
 328 enum OpalThreadStatus {
 329         OPAL_THREAD_INACTIVE = 0x0,
 330         OPAL_THREAD_STARTED = 0x1,
 331         OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
 332 };
 333
 334 enum OpalPciBusCompare {
 335         OpalPciBusAny   = 0,    /* Any bus number match */
 336         OpalPciBus3Bits = 2,    /* Match top 3 bits of bus number */
 337         OpalPciBus4Bits = 3,    /* Match top 4 bits of bus number */
 338         OpalPciBus5Bits = 4,    /* Match top 5 bits of bus number */
 339         OpalPciBus6Bits = 5,    /* Match top 6 bits of bus number */
 340         OpalPciBus7Bits = 6,    /* Match top 7 bits of bus number */
 341         OpalPciBusAll   = 7,    /* Match bus number exactly */
 342 };
 343
 344 enum OpalDeviceCompare {
 345         OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
 346         OPAL_COMPARE_RID_DEVICE_NUMBER = 1
 347 };
 348
 349 enum OpalFuncCompare {
 350         OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
 351         OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
 352 };
 353
 354 enum OpalPeAction {
 355         OPAL_UNMAP_PE = 0,
 356         OPAL_MAP_PE = 1
 357 };
 358
 359 enum OpalPeltvAction {
 360         OPAL_REMOVE_PE_FROM_DOMAIN = 0,
 361         OPAL_ADD_PE_TO_DOMAIN = 1
 362 };
 363
 364 enum OpalMveEnableAction {
 365         OPAL_DISABLE_MVE = 0,
 366         OPAL_ENABLE_MVE = 1
 367 };
 368
 369 enum OpalPciResetScope {
 370         OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
 371         OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
 372         OPAL_PCI_IODA_TABLE_RESET = 6,
 373 };
 374
 375 enum OpalPciReinitScope {
 376         OPAL_REINIT_PCI_DEV = 1000
 377 };
 378
 379 enum OpalPciResetState {
 380         OPAL_DEASSERT_RESET = 0,
 381         OPAL_ASSERT_RESET = 1
 382 };
 383
 384 enum OpalPciMaskAction {
 385         OPAL_UNMASK_ERROR_TYPE = 0,
 386         OPAL_MASK_ERROR_TYPE = 1
 387 };
 388
 389 enum OpalSlotLedType {
 390         OPAL_SLOT_LED_ID_TYPE = 0,
 391         OPAL_SLOT_LED_FAULT_TYPE = 1
 392 };
 393
 394 enum OpalLedAction {
 395         OPAL_TURN_OFF_LED = 0,
 396         OPAL_TURN_ON_LED = 1,
 397         OPAL_QUERY_LED_STATE_AFTER_BUSY = 2
 398 };
 399
 400 enum OpalEpowStatus {
 401         OPAL_EPOW_NONE = 0,
 402         OPAL_EPOW_UPS = 1,
 403         OPAL_EPOW_OVER_AMBIENT_TEMP = 2,
 404         OPAL_EPOW_OVER_INTERNAL_TEMP = 3
 405 };
 406
 407 /*
 408  * Address cycle types for LPC accesses. These also correspond
 409  * to the content of the first cell of the "reg" property for
 410  * device nodes on the LPC bus
 411  */
 412 enum OpalLPCAddressType {
 413         OPAL_LPC_MEM    = 0,
 414         OPAL_LPC_IO     = 1,
 415         OPAL_LPC_FW     = 2,
 416 };
 417
 418 /* System parameter permission */
 419 enum OpalSysparamPerm {
 420         OPAL_SYSPARAM_READ      = 0x1,
 421         OPAL_SYSPARAM_WRITE     = 0x2,
 422         OPAL_SYSPARAM_RW        = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE),
 423 };
 424
 425 struct opal_msg {
 426         __be32 msg_type;
 427         __be32 reserved;
 428         __be64 params[8];
 429 };
 430
 431 struct opal_machine_check_event {
 432         enum OpalMCE_Version    version:8;      /* 0x00 */
 433         uint8_t                 in_use;         /* 0x01 */
 434         enum OpalMCE_Severity   severity:8;     /* 0x02 */
 435         enum OpalMCE_Initiator  initiator:8;    /* 0x03 */
 436         enum OpalMCE_ErrorType  error_type:8;   /* 0x04 */
 437         enum OpalMCE_Disposition disposition:8; /* 0x05 */
 438         uint8_t                 reserved_1[2];  /* 0x06 */
 439         uint64_t                gpr3;           /* 0x08 */
 440         uint64_t                srr0;           /* 0x10 */
 441         uint64_t                srr1;           /* 0x18 */
 442         union {                                 /* 0x20 */
 443                 struct {
 444                         enum OpalMCE_UeErrorType ue_error_type:8;
 445                         uint8_t         effective_address_provided;
 446                         uint8_t         physical_address_provided;
 447                         uint8_t         reserved_1[5];
 448                         uint64_t        effective_address;
 449                         uint64_t        physical_address;
 450                         uint8_t         reserved_2[8];
 451                 } ue_error;
 452
 453                 struct {
 454                         enum OpalMCE_SlbErrorType slb_error_type:8;
 455                         uint8_t         effective_address_provided;
 456                         uint8_t         reserved_1[6];
 457                         uint64_t        effective_address;
 458                         uint8_t         reserved_2[16];
 459                 } slb_error;
 460
 461                 struct {
 462                         enum OpalMCE_EratErrorType erat_error_type:8;
 463                         uint8_t         effective_address_provided;
 464                         uint8_t         reserved_1[6];
 465                         uint64_t        effective_address;
 466                         uint8_t         reserved_2[16];
 467                 } erat_error;
 468
 469                 struct {
 470                         enum OpalMCE_TlbErrorType tlb_error_type:8;
 471                         uint8_t         effective_address_provided;
 472                         uint8_t         reserved_1[6];
 473                         uint64_t        effective_address;
 474                         uint8_t         reserved_2[16];
 475                 } tlb_error;
 476         } u;
 477 };
 478
 479 /* FSP memory errors handling */
 480 enum OpalMemErr_Version {
 481         OpalMemErr_V1 = 1,
 482 };
 483
 484 enum OpalMemErrType {
 485         OPAL_MEM_ERR_TYPE_RESILIENCE    = 0,
 486         OPAL_MEM_ERR_TYPE_DYN_DALLOC,
 487         OPAL_MEM_ERR_TYPE_SCRUB,
 488 };
 489
 490 /* Memory Reilience error type */
 491 enum OpalMemErr_ResilErrType {
 492         OPAL_MEM_RESILIENCE_CE          = 0,
 493         OPAL_MEM_RESILIENCE_UE,
 494         OPAL_MEM_RESILIENCE_UE_SCRUB,
 495 };
 496
 497 /* Dynamic Memory Deallocation type */
 498 enum OpalMemErr_DynErrType {
 499         OPAL_MEM_DYNAMIC_DEALLOC        = 0,
 500 };
 501
 502 /* OpalMemoryErrorData->flags */
 503 #define OPAL_MEM_CORRECTED_ERROR        0x0001
 504 #define OPAL_MEM_THRESHOLD_EXCEEDED     0x0002
 505 #define OPAL_MEM_ACK_REQUIRED           0x8000
 506
 507 struct OpalMemoryErrorData {
 508         enum OpalMemErr_Version version:8;      /* 0x00 */
 509         enum OpalMemErrType     type:8;         /* 0x01 */
 510         uint16_t                flags;          /* 0x02 */
 511         uint8_t                 reserved_1[4];  /* 0x04 */
 512
 513         union {
 514                 /* Memory Resilience corrected/uncorrected error info */
 515                 struct {
 516                         enum OpalMemErr_ResilErrType resil_err_type:8;
 517                         uint8_t         reserved_1[7];
 518                         uint64_t        physical_address_start;
 519                         uint64_t        physical_address_end;
 520                 } resilience;
 521                 /* Dynamic memory deallocation error info */
 522                 struct {
 523                         enum OpalMemErr_DynErrType dyn_err_type:8;
 524                         uint8_t         reserved_1[7];
 525                         uint64_t        physical_address_start;
 526                         uint64_t        physical_address_end;
 527                 } dyn_dealloc;
 528         } u;
 529 };
 530
 531 enum {
 532         OPAL_P7IOC_DIAG_TYPE_NONE       = 0,
 533         OPAL_P7IOC_DIAG_TYPE_RGC        = 1,
 534         OPAL_P7IOC_DIAG_TYPE_BI         = 2,
 535         OPAL_P7IOC_DIAG_TYPE_CI         = 3,
 536         OPAL_P7IOC_DIAG_TYPE_MISC       = 4,
 537         OPAL_P7IOC_DIAG_TYPE_I2C        = 5,
 538         OPAL_P7IOC_DIAG_TYPE_LAST       = 6
 539 };
 540
 541 struct OpalIoP7IOCErrorData {
 542         uint16_t type;
 543
 544         /* GEM */
 545         uint64_t gemXfir;
 546         uint64_t gemRfir;
 547         uint64_t gemRirqfir;
 548         uint64_t gemMask;
 549         uint64_t gemRwof;
 550
 551         /* LEM */
 552         uint64_t lemFir;
 553         uint64_t lemErrMask;
 554         uint64_t lemAction0;
 555         uint64_t lemAction1;
 556         uint64_t lemWof;
 557
 558         union {
 559                 struct OpalIoP7IOCRgcErrorData {
 560                         uint64_t rgcStatus;             /* 3E1C10 */
 561                         uint64_t rgcLdcp;               /* 3E1C18 */
 562                 }rgc;
 563                 struct OpalIoP7IOCBiErrorData {
 564                         uint64_t biLdcp0;               /* 3C0100, 3C0118 */
 565                         uint64_t biLdcp1;               /* 3C0108, 3C0120 */
 566                         uint64_t biLdcp2;               /* 3C0110, 3C0128 */
 567                         uint64_t biFenceStatus;         /* 3C0130, 3C0130 */
 568
 569                         uint8_t  biDownbound;           /* BI Downbound or Upbound */
 570                 }bi;
 571                 struct OpalIoP7IOCCiErrorData {
 572                         uint64_t ciPortStatus;          /* 3Dn008 */
 573                         uint64_t ciPortLdcp;            /* 3Dn010 */
 574
 575                         uint8_t  ciPort;                /* Index of CI port: 0/1 */
 576                 }ci;
 577         };
 578 };
 579
 580 /**
 581  * This structure defines the overlay which will be used to store PHB error
 582  * data upon request.
 583  */
 584 enum {
 585         OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
 586 };
 587
 588 enum {
 589         OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
 590         OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2
 591 };
 592
 593 enum {
 594         OPAL_P7IOC_NUM_PEST_REGS = 128,
 595         OPAL_PHB3_NUM_PEST_REGS = 256
 596 };
 597
 598 struct OpalIoPhbErrorCommon {
 599         uint32_t version;
 600         uint32_t ioType;
 601         uint32_t len;
 602 };
 603
 604 struct OpalIoP7IOCPhbErrorData {
 605         struct OpalIoPhbErrorCommon common;
 606
 607         uint32_t brdgCtl;
 608
 609         // P7IOC utl regs
 610         uint32_t portStatusReg;
 611         uint32_t rootCmplxStatus;
 612         uint32_t busAgentStatus;
 613
 614         // P7IOC cfg regs
 615         uint32_t deviceStatus;
 616         uint32_t slotStatus;
 617         uint32_t linkStatus;
 618         uint32_t devCmdStatus;
 619         uint32_t devSecStatus;
 620
 621         // cfg AER regs
 622         uint32_t rootErrorStatus;
 623         uint32_t uncorrErrorStatus;
 624         uint32_t corrErrorStatus;
 625         uint32_t tlpHdr1;
 626         uint32_t tlpHdr2;
 627         uint32_t tlpHdr3;
 628         uint32_t tlpHdr4;
 629         uint32_t sourceId;
 630
 631         uint32_t rsv3;
 632
 633         // Record data about the call to allocate a buffer.
 634         uint64_t errorClass;
 635         uint64_t correlator;
 636
 637         //P7IOC MMIO Error Regs
 638         uint64_t p7iocPlssr;                // n120
 639         uint64_t p7iocCsr;                  // n110
 640         uint64_t lemFir;                    // nC00
 641         uint64_t lemErrorMask;              // nC18
 642         uint64_t lemWOF;                    // nC40
 643         uint64_t phbErrorStatus;            // nC80
 644         uint64_t phbFirstErrorStatus;       // nC88
 645         uint64_t phbErrorLog0;              // nCC0
 646         uint64_t phbErrorLog1;              // nCC8
 647         uint64_t mmioErrorStatus;           // nD00
 648         uint64_t mmioFirstErrorStatus;      // nD08
 649         uint64_t mmioErrorLog0;             // nD40
 650         uint64_t mmioErrorLog1;             // nD48
 651         uint64_t dma0ErrorStatus;           // nD80
 652         uint64_t dma0FirstErrorStatus;      // nD88
 653         uint64_t dma0ErrorLog0;             // nDC0
 654         uint64_t dma0ErrorLog1;             // nDC8
 655         uint64_t dma1ErrorStatus;           // nE00
 656         uint64_t dma1FirstErrorStatus;      // nE08
 657         uint64_t dma1ErrorLog0;             // nE40
 658         uint64_t dma1ErrorLog1;             // nE48
 659         uint64_t pestA[OPAL_P7IOC_NUM_PEST_REGS];
 660         uint64_t pestB[OPAL_P7IOC_NUM_PEST_REGS];
 661 };
 662
 663 struct OpalIoPhb3ErrorData {
 664         struct OpalIoPhbErrorCommon common;
 665
 666         uint32_t brdgCtl;
 667
 668         /* PHB3 UTL regs */
 669         uint32_t portStatusReg;
 670         uint32_t rootCmplxStatus;
 671         uint32_t busAgentStatus;
 672
 673         /* PHB3 cfg regs */
 674         uint32_t deviceStatus;
 675         uint32_t slotStatus;
 676         uint32_t linkStatus;
 677         uint32_t devCmdStatus;
 678         uint32_t devSecStatus;
 679
 680         /* cfg AER regs */
 681         uint32_t rootErrorStatus;
 682         uint32_t uncorrErrorStatus;
 683         uint32_t corrErrorStatus;
 684         uint32_t tlpHdr1;
 685         uint32_t tlpHdr2;
 686         uint32_t tlpHdr3;
 687         uint32_t tlpHdr4;
 688         uint32_t sourceId;
 689
 690         uint32_t rsv3;
 691
 692         /* Record data about the call to allocate a buffer */
 693         uint64_t errorClass;
 694         uint64_t correlator;
 695
 696         uint64_t nFir;                  /* 000 */
 697         uint64_t nFirMask;              /* 003 */
 698         uint64_t nFirWOF;               /* 008 */
 699
 700         /* PHB3 MMIO Error Regs */
 701         uint64_t phbPlssr;              /* 120 */
 702         uint64_t phbCsr;                /* 110 */
 703         uint64_t lemFir;                /* C00 */
 704         uint64_t lemErrorMask;          /* C18 */
 705         uint64_t lemWOF;                /* C40 */
 706         uint64_t phbErrorStatus;        /* C80 */
 707         uint64_t phbFirstErrorStatus;   /* C88 */
 708         uint64_t phbErrorLog0;          /* CC0 */
 709         uint64_t phbErrorLog1;          /* CC8 */
 710         uint64_t mmioErrorStatus;       /* D00 */
 711         uint64_t mmioFirstErrorStatus;  /* D08 */
 712         uint64_t mmioErrorLog0;         /* D40 */
 713         uint64_t mmioErrorLog1;         /* D48 */
 714         uint64_t dma0ErrorStatus;       /* D80 */
 715         uint64_t dma0FirstErrorStatus;  /* D88 */
 716         uint64_t dma0ErrorLog0;         /* DC0 */
 717         uint64_t dma0ErrorLog1;         /* DC8 */
 718         uint64_t dma1ErrorStatus;       /* E00 */
 719         uint64_t dma1FirstErrorStatus;  /* E08 */
 720         uint64_t dma1ErrorLog0;         /* E40 */
 721         uint64_t dma1ErrorLog1;         /* E48 */
 722         uint64_t pestA[OPAL_PHB3_NUM_PEST_REGS];
 723         uint64_t pestB[OPAL_PHB3_NUM_PEST_REGS];
 724 };
 725
 726 typedef struct oppanel_line {
 727         const char *    line;
 728         uint64_t        line_len;
 729 } oppanel_line_t;
 730
 731 /* /sys/firmware/opal */
 732 extern struct kobject *opal_kobj;
 733
 734 /* /ibm,opal */
 735 extern struct device_node *opal_node;
 736
 737 /* API functions */
 738 int64_t opal_invalid_call(void);
 739 int64_t opal_console_write(int64_t term_number, __be64 *length,
 740                            const uint8_t *buffer);
 741 int64_t opal_console_read(int64_t term_number, __be64 *length,
 742                           uint8_t *buffer);
 743 int64_t opal_console_write_buffer_space(int64_t term_number,
 744                                         __be64 *length);
 745 int64_t opal_rtc_read(__be32 *year_month_day,
 746                       __be64 *hour_minute_second_millisecond);
 747 int64_t opal_rtc_write(uint32_t year_month_day,
 748                        uint64_t hour_minute_second_millisecond);
 749 int64_t opal_cec_power_down(uint64_t request);
 750 int64_t opal_cec_reboot(void);
 751 int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
 752 int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
 753 int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask);
 754 int64_t opal_poll_events(__be64 *outstanding_event_mask);
 755 int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
 756                                     uint64_t tce_mem_size);
 757 int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
 758                                     uint64_t tce_mem_size);
 759 int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
 760                                   uint64_t offset, uint8_t *data);
 761 int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
 762                                        uint64_t offset, __be16 *data);
 763 int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
 764                                   uint64_t offset, __be32 *data);
 765 int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
 766                                    uint64_t offset, uint8_t data);
 767 int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
 768                                         uint64_t offset, uint16_t data);
 769 int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
 770                                    uint64_t offset, uint32_t data);
 771 int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
 772 int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority);
 773 int64_t opal_register_exception_handler(uint64_t opal_exception,
 774                                         uint64_t handler_address,
 775                                         uint64_t glue_cache_line);
 776 int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
 777                                    uint8_t *freeze_state,
 778                                    __be16 *pci_error_type,
 779                                    __be64 *phb_status);
 780 int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
 781                                   uint64_t eeh_action_token);
 782 int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
 783
 784
 785
 786 int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
 787                                  uint16_t window_num, uint16_t enable);
 788 int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
 789                                     uint16_t window_num,
 790                                     uint64_t starting_real_address,
 791                                     uint64_t starting_pci_address,
 792                                     uint16_t segment_size);
 793 int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
 794                                     uint16_t window_type, uint16_t window_num,
 795                                     uint16_t segment_num);
 796 int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
 797                                       uint64_t ivt_addr, uint64_t ivt_len,
 798                                       uint64_t reject_array_addr,
 799                                       uint64_t peltv_addr);
 800 int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
 801                         uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
 802                         uint8_t pe_action);
 803 int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
 804                            uint8_t state);
 805 int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
 806 int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
 807                                 uint32_t state);
 808 int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
 809                                   uint8_t *p_bit, uint8_t *q_bit);
 810 int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
 811                                   uint8_t p_bit, uint8_t q_bit);
 812 int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
 813 int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
 814                              uint32_t xive_num);
 815 int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
 816                              __be32 *interrupt_source_number);
 817 int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
 818                         uint8_t msi_range, __be32 *msi_address,
 819                         __be32 *message_data);
 820 int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
 821                         uint32_t xive_num, uint8_t msi_range,
 822                         __be64 *msi_address, __be32 *message_data);
 823 int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
 824 int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
 825 int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
 826 int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
 827                                    uint16_t tce_levels, uint64_t tce_table_addr,
 828                                    uint64_t tce_table_size, uint64_t tce_page_size);
 829 int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
 830                                         uint16_t dma_window_number, uint64_t pci_start_addr,
 831                                         uint64_t pci_mem_size);
 832 int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
 833
 834 int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
 835                                    uint64_t diag_buffer_len);
 836 int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
 837                                    uint64_t diag_buffer_len);
 838 int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
 839                                     uint64_t diag_buffer_len);
 840 int64_t opal_pci_fence_phb(uint64_t phb_id);
 841 int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data);
 842 int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
 843 int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
 844 int64_t opal_get_epow_status(__be64 *status);
 845 int64_t opal_set_system_attention_led(uint8_t led_action);
 846 int64_t opal_pci_next_error(uint64_t phb_id, uint64_t *first_frozen_pe,
 847                             uint16_t *pci_error_type, uint16_t *severity);
 848 int64_t opal_pci_poll(uint64_t phb_id);
 849 int64_t opal_return_cpu(void);
 850
 851 int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val);
 852 int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val);
 853
 854 int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
 855                        uint32_t addr, uint32_t data, uint32_t sz);
 856 int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type,
 857                       uint32_t addr, __be32 *data, uint32_t sz);
 858
 859 int64_t opal_read_elog(uint64_t buffer, size_t size, uint64_t log_id);
 860 int64_t opal_get_elog_size(uint64_t *log_id, size_t *size, uint64_t *elog_type);
 861 int64_t opal_write_elog(uint64_t buffer, uint64_t size, uint64_t offset);
 862 int64_t opal_send_ack_elog(uint64_t log_id);
 863 void opal_resend_pending_logs(void);
 864
 865 int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result);
 866 int64_t opal_manage_flash(uint8_t op);
 867 int64_t opal_update_flash(uint64_t blk_list);
 868 int64_t opal_dump_init(uint8_t dump_type);
 869 int64_t opal_dump_info(uint32_t *dump_id, uint32_t *dump_size);
 870 int64_t opal_dump_info2(uint32_t *dump_id, uint32_t *dump_size, uint32_t *dump_type);
 871 int64_t opal_dump_read(uint32_t dump_id, uint64_t buffer);
 872 int64_t opal_dump_ack(uint32_t dump_id);
 873 int64_t opal_dump_resend_notification(void);
 874
 875 int64_t opal_get_msg(uint64_t buffer, size_t size);
 876 int64_t opal_check_completion(uint64_t buffer, size_t size, uint64_t token);
 877 int64_t opal_sync_host_reboot(void);
 878 int64_t opal_get_param(uint64_t token, uint32_t param_id, uint64_t buffer,
 879                 size_t length);
 880 int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer,
 881                 size_t length);
 882 int64_t opal_sensor_read(uint32_t sensor_hndl, int token, __be32 *sensor_data);
 883
 884 /* Internal functions */
 885 extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data);
 886 extern int early_init_dt_scan_recoverable_ranges(unsigned long node,
 887                                  const char *uname, int depth, void *data);
 888
 889 extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
 890 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
 891
 892 extern void hvc_opal_init_early(void);
 893
 894 /* Internal functions */
 895 extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
 896                                    int depth, void *data);
 897
 898 extern int opal_notifier_register(struct notifier_block *nb);
 899 extern int opal_notifier_unregister(struct notifier_block *nb);
 900
 901 extern int opal_message_notifier_register(enum OpalMessageType msg_type,
 902                                                 struct notifier_block *nb);
 903 extern void opal_notifier_enable(void);
 904 extern void opal_notifier_disable(void);
 905 extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
 906
 907 extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
 908 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
 909
 910 extern int __opal_async_get_token(void);
 911 extern int opal_async_get_token_interruptible(void);
 912 extern int __opal_async_release_token(int token);
 913 extern int opal_async_release_token(int token);
 914 extern int opal_async_wait_response(uint64_t token, struct opal_msg *msg);
 915 extern int opal_get_sensor_data(u32 sensor_hndl, u32 *sensor_data);
 916
 917 extern void hvc_opal_init_early(void);
 918
 919 struct rtc_time;
 920 extern int opal_set_rtc_time(struct rtc_time *tm);
 921 extern void opal_get_rtc_time(struct rtc_time *tm);
 922 extern unsigned long opal_get_boot_time(void);
 923 extern void opal_nvram_init(void);
 924 extern void opal_flash_init(void);
 925 extern int opal_elog_init(void);
 926 extern void opal_platform_dump_init(void);
 927 extern void opal_sys_param_init(void);
 928 extern void opal_msglog_init(void);
 929
 930 extern int opal_machine_check(struct pt_regs *regs);
 931 extern bool opal_mce_check_early_recovery(struct pt_regs *regs);
 932
 933 extern void opal_shutdown(void);
 934 extern int opal_resync_timebase(void);
 935
 936 extern void opal_lpc_init(void);
 937
 938 #endif /* __ASSEMBLY__ */
 939
 940 #endif /* __OPAL_H */