2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
4 #ifndef _ASM_POWERPC_PPC_ASM_H
5 #define _ASM_POWERPC_PPC_ASM_H
7 #include <linux/init.h>
8 #include <linux/stringify.h>
9 #include <asm/asm-compat.h>
10 #include <asm/processor.h>
11 #include <asm/ppc-opcode.h>
12 #include <asm/firmware.h>
15 #error __FILE__ should only be used in assembler files
18 #define SZL (BITS_PER_LONG/8)
21 * Stuff for accurate CPU time accounting.
22 * These macros handle transitions between user and system state
23 * in exception entry and exit and accumulate time to the
24 * user_time and system_time fields in the paca.
27 #ifndef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
28 #define ACCOUNT_CPU_USER_ENTRY(ra, rb)
29 #define ACCOUNT_CPU_USER_EXIT(ra, rb)
30 #define ACCOUNT_STOLEN_TIME
32 #define ACCOUNT_CPU_USER_ENTRY(ra, rb) \
33 MFTB(ra); /* get timebase */ \
34 ld rb,PACA_STARTTIME_USER(r13); \
35 std ra,PACA_STARTTIME(r13); \
36 subf rb,rb,ra; /* subtract start value */ \
37 ld ra,PACA_USER_TIME(r13); \
38 add ra,ra,rb; /* add on to user time */ \
39 std ra,PACA_USER_TIME(r13); \
41 #define ACCOUNT_CPU_USER_EXIT(ra, rb) \
42 MFTB(ra); /* get timebase */ \
43 ld rb,PACA_STARTTIME(r13); \
44 std ra,PACA_STARTTIME_USER(r13); \
45 subf rb,rb,ra; /* subtract start value */ \
46 ld ra,PACA_SYSTEM_TIME(r13); \
47 add ra,ra,rb; /* add on to system time */ \
48 std ra,PACA_SYSTEM_TIME(r13)
50 #ifdef CONFIG_PPC_SPLPAR
51 #define ACCOUNT_STOLEN_TIME \
52 BEGIN_FW_FTR_SECTION; \
54 /* from user - see if there are any DTL entries to process */ \
55 ld r10,PACALPPACAPTR(r13); /* get ptr to VPA */ \
56 ld r11,PACA_DTL_RIDX(r13); /* get log read index */ \
57 addi r10,r10,LPPACA_DTLIDX; \
58 LDX_BE r10,0,r10; /* get log write index */ \
61 bl .accumulate_stolen_time; \
63 andi. r10,r12,MSR_PR; /* Restore cr0 (coming from user) */ \
65 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
67 #else /* CONFIG_PPC_SPLPAR */
68 #define ACCOUNT_STOLEN_TIME
70 #endif /* CONFIG_PPC_SPLPAR */
72 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */
75 * Macros for storing registers into and loading registers from
79 #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
80 #define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
81 #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
82 #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
84 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
85 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
86 #define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
88 #define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \
92 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
93 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
94 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
95 #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
96 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
97 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
98 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
99 #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
101 #define SAVE_FPR(n, base) stfd n,8*TS_FPRWIDTH*(n)(base)
102 #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
103 #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
104 #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
105 #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
106 #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
107 #define REST_FPR(n, base) lfd n,8*TS_FPRWIDTH*(n)(base)
108 #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
109 #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
110 #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
111 #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
112 #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
114 #define SAVE_VR(n,b,base) li b,16*(n); stvx n,base,b
115 #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
116 #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
117 #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
118 #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
119 #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
120 #define REST_VR(n,b,base) li b,16*(n); lvx n,base,b
121 #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
122 #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
123 #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
124 #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
125 #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
127 /* Save the lower 32 VSRs in the thread VSR region */
128 #define SAVE_VSR(n,b,base) li b,16*(n); STXVD2X(n,R##base,R##b)
129 #define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
130 #define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
131 #define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
132 #define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
133 #define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
134 #define REST_VSR(n,b,base) li b,16*(n); LXVD2X(n,R##base,R##b)
135 #define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base)
136 #define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
137 #define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
138 #define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
139 #define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
142 * b = base register for addressing, o = base offset from register of 1st EVR
143 * n = first EVR, s = scratch
145 #define SAVE_EVR(n,s,b,o) evmergehi s,s,n; stw s,o+4*(n)(b)
146 #define SAVE_2EVRS(n,s,b,o) SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o)
147 #define SAVE_4EVRS(n,s,b,o) SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o)
148 #define SAVE_8EVRS(n,s,b,o) SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o)
149 #define SAVE_16EVRS(n,s,b,o) SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o)
150 #define SAVE_32EVRS(n,s,b,o) SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o)
151 #define REST_EVR(n,s,b,o) lwz s,o+4*(n)(b); evmergelo n,s,n
152 #define REST_2EVRS(n,s,b,o) REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o)
153 #define REST_4EVRS(n,s,b,o) REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o)
154 #define REST_8EVRS(n,s,b,o) REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o)
155 #define REST_16EVRS(n,s,b,o) REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o)
156 #define REST_32EVRS(n,s,b,o) REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o)
158 /* Macros to adjust thread priority for hardware multithreading */
159 #define HMT_VERY_LOW or 31,31,31 # very low priority
160 #define HMT_LOW or 1,1,1
161 #define HMT_MEDIUM_LOW or 6,6,6 # medium low priority
162 #define HMT_MEDIUM or 2,2,2
163 #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
164 #define HMT_HIGH or 3,3,3
165 #define HMT_EXTRA_HIGH or 7,7,7 # power7 only
172 #define __VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE))
173 #define VCPU_GPR(n) __VCPU_GPR(__REG_##n)
178 #define STACKFRAMESIZE 256
179 #define __STK_REG(i) (112 + ((i)-14)*8)
180 #define STK_REG(i) __STK_REG(__REG_##i)
182 #define __STK_PARAM(i) (48 + ((i)-3)*8)
183 #define STK_PARAM(i) __STK_PARAM(__REG_##i)
185 #define XGLUE(a,b) a##b
186 #define GLUE(a,b) XGLUE(a,b)
188 #define _GLOBAL(name) \
192 .globl GLUE(.,name); \
193 .section ".opd","aw"; \
195 .quad GLUE(.,name); \
196 .quad .TOC.@tocbase; \
199 .type GLUE(.,name),@function; \
202 #define _INIT_GLOBAL(name) \
206 .globl GLUE(.,name); \
207 .section ".opd","aw"; \
209 .quad GLUE(.,name); \
210 .quad .TOC.@tocbase; \
213 .type GLUE(.,name),@function; \
216 #define _KPROBE(name) \
217 .section ".kprobes.text","a"; \
220 .globl GLUE(.,name); \
221 .section ".opd","aw"; \
223 .quad GLUE(.,name); \
224 .quad .TOC.@tocbase; \
227 .type GLUE(.,name),@function; \
230 #define _STATIC(name) \
233 .section ".opd","aw"; \
235 .quad GLUE(.,name); \
236 .quad .TOC.@tocbase; \
239 .type GLUE(.,name),@function; \
242 #define _INIT_STATIC(name) \
245 .section ".opd","aw"; \
247 .quad GLUE(.,name); \
248 .quad .TOC.@tocbase; \
251 .type GLUE(.,name),@function; \
262 .stabs __stringify(n:F-1),N_FUN,0,0,n;\
267 .section ".kprobes.text","a"; \
274 * LOAD_REG_IMMEDIATE(rn, expr)
275 * Loads the value of the constant expression 'expr' into register 'rn'
276 * using immediate instructions only. Use this when it's important not
277 * to reference other data (i.e. on ppc64 when the TOC pointer is not
278 * valid) and when 'expr' is a constant or absolute address.
280 * LOAD_REG_ADDR(rn, name)
281 * Loads the address of label 'name' into register 'rn'. Use this when
282 * you don't particularly need immediate instructions only, but you need
283 * the whole address in one register (e.g. it's a structure address and
284 * you want to access various offsets within it). On ppc32 this is
285 * identical to LOAD_REG_IMMEDIATE.
287 * LOAD_REG_ADDRBASE(rn, name)
289 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into
290 * register 'rn'. ADDROFF(name) returns the remainder of the address as
291 * a constant expression. ADDROFF(name) is a signed expression < 16 bits
292 * in size, so is suitable for use directly as an offset in load and store
293 * instructions. Use this when loading/storing a single word or less as:
294 * LOAD_REG_ADDRBASE(rX, name)
295 * ld rY,ADDROFF(name)(rX)
298 #define LOAD_REG_IMMEDIATE(reg,expr) \
299 lis reg,(expr)@highest; \
300 ori reg,reg,(expr)@higher; \
301 rldicr reg,reg,32,31; \
302 oris reg,reg,(expr)@h; \
303 ori reg,reg,(expr)@l;
305 #define LOAD_REG_ADDR(reg,name) \
308 #define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name)
309 #define ADDROFF(name) 0
311 /* offsets for stack frame layout */
316 #define LOAD_REG_IMMEDIATE(reg,expr) \
318 addi reg,reg,(expr)@l;
320 #define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE(reg, name)
322 #define LOAD_REG_ADDRBASE(reg, name) lis reg,name@ha
323 #define ADDROFF(name) name@l
325 /* offsets for stack frame layout */
330 /* various errata or part fixups */
331 #ifdef CONFIG_PPC601_SYNC_FIX
336 END_FTR_SECTION_IFSET(CPU_FTR_601)
340 END_FTR_SECTION_IFSET(CPU_FTR_601)
344 END_FTR_SECTION_IFSET(CPU_FTR_601)
351 #if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
353 90: mfspr dest, SPRN_TBRL; \
354 BEGIN_FTR_SECTION_NESTED(96); \
357 END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
359 #define MFTB(dest) mfspr dest, SPRN_TBRL
364 #else /* CONFIG_SMP */
365 /* tlbsync is not implemented on 601 */
370 END_FTR_SECTION_IFCLR(CPU_FTR_601)
374 #define MTOCRF(FXM, RS) \
375 BEGIN_FTR_SECTION_NESTED(848); \
377 FTR_SECTION_ELSE_NESTED(848); \
379 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848)
382 * PPR restore macros used in entry_64.S
383 * Used for P7 or later processors
385 #define HMT_MEDIUM_LOW_HAS_PPR \
386 BEGIN_FTR_SECTION_NESTED(944) \
388 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,944)
390 #define SET_DEFAULT_THREAD_PPR(ra, rb) \
391 BEGIN_FTR_SECTION_NESTED(945) \
392 lis ra,INIT_PPR@highest; /* default ppr=3 */ \
393 ld rb,PACACURRENT(r13); \
394 sldi ra,ra,32; /* 11- 13 bits are used for ppr */ \
395 std ra,TASKTHREADPPR(rb); \
396 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,945)
398 #define RESTORE_PPR(ra, rb) \
399 BEGIN_FTR_SECTION_NESTED(946) \
400 ld ra,PACACURRENT(r13); \
401 ld rb,TASKTHREADPPR(ra); \
402 mtspr SPRN_PPR,rb; /* Restore PPR */ \
403 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,946)
408 * This instruction is not implemented on the PPC 603 or 601; however, on
409 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
410 * All of these instructions exist in the 8xx, they have magical powers,
411 * and they must be used.
414 #if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
418 lis r4,KERNELBASE@h; \
425 #ifdef CONFIG_IBM440EP_ERR42
426 #define PPC440EP_ERR42 isync
428 #define PPC440EP_ERR42
431 /* The following stops all load and store data streams associated with stream
432 * ID (ie. streams created explicitly). The embedded and server mnemonics for
433 * dcbt are different so we use machine "power4" here explicitly.
435 #define DCBT_STOP_ALL_STREAM_IDS(scratch) \
437 .machine "power4" ; \
438 lis scratch,0x60000000@h; \
439 dcbt r0,scratch,0b01010; \
443 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them
444 * keep the address intact to be compatible with code shared with
447 * On the other hand, I find it useful to have them behave as expected
448 * by their name (ie always do the addition) on 64-bit BookE
450 #if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64)
455 * We use addis to ensure compatibility with the "classic" ppc versions of
456 * these macros, which use rs = 0 to get the tophys offset in rd, rather than
457 * converting the address in r0, and so this version has to do that too
458 * (i.e. set register rd to 0 when rs == 0).
460 #define tophys(rd,rs) \
463 #define tovirt(rd,rs) \
466 #elif defined(CONFIG_PPC64)
467 #define toreal(rd) /* we can access c000... in real mode */
470 #define tophys(rd,rs) \
473 #define tovirt(rd,rs) \
475 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\
479 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
480 * physical base address of RAM at compile time.
482 #define toreal(rd) tophys(rd,rd)
483 #define fromreal(rd) tovirt(rd,rd)
485 #define tophys(rd,rs) \
486 0: addis rd,rs,-PAGE_OFFSET@h; \
487 .section ".vtop_fixup","aw"; \
492 #define tovirt(rd,rs) \
493 0: addis rd,rs,PAGE_OFFSET@h; \
494 .section ".ptov_fixup","aw"; \
500 #ifdef CONFIG_PPC_BOOK3S_64
502 #define MTMSRD(r) mtmsrd r
503 #define MTMSR_EERI(reg) mtmsrd reg,1
505 #define FIX_SRR1(ra, rb)
509 #define RFI rfi; b . /* Prevent prefetch past rfi */
511 #define MTMSRD(r) mtmsr r
512 #define MTMSR_EERI(reg) mtmsr reg
516 #endif /* __KERNEL__ */
518 /* The boring bits... */
520 /* Condition Register Bit Fields */
533 * General Purpose Registers (GPRs)
535 * The lower case r0-r31 should be used in preference to the upper
536 * case R0-R31 as they provide more error checking in the assembler.
537 * Use R0-31 only when really nessesary.
574 /* Floating Point Registers (FPRs) */
609 /* AltiVec Registers (VPRs) */
644 /* VSX Registers (VSRs) */
711 /* SPE Registers (EVPRs) */
746 /* some stab codes */
752 #endif /* __ASSEMBLY__ */
754 #endif /* _ASM_POWERPC_PPC_ASM_H */