1 #ifndef _ASM_POWERPC_PROCESSOR_H
2 #define _ASM_POWERPC_PROCESSOR_H
5 * Copyright (C) 2001 PPC 64 Team, IBM Corp
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
19 #define TS_FPROFFSET 0
20 #define TS_VSRLOWOFFSET 1
22 #define TS_FPROFFSET 1
23 #define TS_VSRLOWOFFSET 0
28 #define TS_FPROFFSET 0
32 /* Default SMT priority is set to 3. Use 11- 13bits to save priority. */
33 #define PPR_PRIORITY 3
35 #define INIT_PPR (PPR_PRIORITY << 50)
37 #define INIT_PPR ((u64)PPR_PRIORITY << 50)
38 #endif /* __ASSEMBLY__ */
39 #endif /* CONFIG_PPC64 */
42 #include <linux/compiler.h>
43 #include <linux/cache.h>
44 #include <asm/ptrace.h>
45 #include <asm/types.h>
46 #include <asm/hw_breakpoint.h>
48 /* We do _not_ want to define new machine types at all, those must die
49 * in favor of using the device-tree
53 /* PREP sub-platform types. Unused */
54 #define _PREP_Motorola 0x01 /* motorola prep */
55 #define _PREP_Firm 0x02 /* firmworks prep */
56 #define _PREP_IBM 0x00 /* ibm prep */
57 #define _PREP_Bull 0x03 /* bull prep */
59 /* CHRP sub-platform types. These are arbitrary */
60 #define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
61 #define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
62 #define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */
63 #define _CHRP_briq 0x07 /* TotalImpact's briQ */
65 #if defined(__KERNEL__) && defined(CONFIG_PPC32)
67 extern int _chrp_type;
69 #endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
72 * Default implementation of macro that returns current
73 * instruction pointer ("program counter").
75 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
77 /* Macros for adjusting thread priority (hardware multi-threading) */
78 #define HMT_very_low() asm volatile("or 31,31,31 # very low priority")
79 #define HMT_low() asm volatile("or 1,1,1 # low priority")
80 #define HMT_medium_low() asm volatile("or 6,6,6 # medium low priority")
81 #define HMT_medium() asm volatile("or 2,2,2 # medium priority")
82 #define HMT_medium_high() asm volatile("or 5,5,5 # medium high priority")
83 #define HMT_high() asm volatile("or 3,3,3 # high priority")
88 void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
89 void release_thread(struct task_struct *);
93 #if CONFIG_TASK_SIZE > CONFIG_KERNEL_START
94 #error User TASK_SIZE overlaps with KERNEL_START address
96 #define TASK_SIZE (CONFIG_TASK_SIZE)
98 /* This decides where the kernel will search for a free chunk of vm
99 * space during mmap's.
101 #define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3)
106 * 64-bit user address space can have multiple limits
107 * For now supported values are:
109 #define TASK_SIZE_64TB (0x0000400000000000UL)
110 #define TASK_SIZE_128TB (0x0000800000000000UL)
111 #define TASK_SIZE_512TB (0x0002000000000000UL)
113 #ifdef CONFIG_PPC_BOOK3S_64
115 * Max value currently used:
117 #define TASK_SIZE_USER64 TASK_SIZE_512TB
119 #define TASK_SIZE_USER64 TASK_SIZE_64TB
123 * 32-bit user address space is 4GB - 1 page
124 * (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
126 #define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))
128 #define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
129 TASK_SIZE_USER32 : TASK_SIZE_USER64)
130 #define TASK_SIZE TASK_SIZE_OF(current)
131 /* This decides where the kernel will search for a free chunk of vm
132 * space during mmap's.
134 #define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
135 #define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_128TB / 4))
137 #define TASK_UNMAPPED_BASE ((is_32bit_task()) ? \
138 TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
142 * Initial task size value for user applications. For book3s 64 we start
143 * with 128TB and conditionally enable upto 512TB
145 #ifdef CONFIG_PPC_BOOK3S_64
146 #define DEFAULT_MAP_WINDOW ((is_32bit_task()) ? \
147 TASK_SIZE_USER32 : TASK_SIZE_128TB)
149 #define DEFAULT_MAP_WINDOW TASK_SIZE
154 /* Limit stack to 128TB */
155 #define STACK_TOP_USER64 TASK_SIZE_128TB
156 #define STACK_TOP_USER32 TASK_SIZE_USER32
158 #define STACK_TOP (is_32bit_task() ? \
159 STACK_TOP_USER32 : STACK_TOP_USER64)
161 #define STACK_TOP_MAX TASK_SIZE_USER64
163 #else /* __powerpc64__ */
165 #define STACK_TOP TASK_SIZE
166 #define STACK_TOP_MAX STACK_TOP
168 #endif /* __powerpc64__ */
174 #define TS_FPR(i) fp_state.fpr[i][TS_FPROFFSET]
175 #define TS_CKFPR(i) ckfp_state.fpr[i][TS_FPROFFSET]
177 /* FP and VSX 0-31 register set */
178 struct thread_fp_state {
179 u64 fpr[32][TS_FPRWIDTH] __attribute__((aligned(16)));
180 u64 fpscr; /* Floating point status */
183 /* Complete AltiVec register set including VSCR */
184 struct thread_vr_state {
185 vector128 vr[32] __attribute__((aligned(16)));
186 vector128 vscr __attribute__((aligned(16)));
190 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
192 * The following help to manage the use of Debug Control Registers
193 * om the BookE platforms.
201 * The stored value of the DBSR register will be the value at the
202 * last debug interrupt. This register can only be read from the
203 * user (will never be written to) and has value while helping to
204 * describe the reason for the last debug trap. Torez
208 * The following will contain addresses used by debug applications
209 * to help trace and trap on particular address locations.
210 * The bits in the Debug Control Registers above help define which
211 * of the following registers will contain valid data and/or addresses.
215 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
221 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
228 struct thread_struct {
229 unsigned long ksp; /* Kernel stack pointer */
232 unsigned long ksp_vsid;
234 struct pt_regs *regs; /* Pointer to saved register state */
235 mm_segment_t fs; /* for get_fs() validation */
237 /* BookE base exception scratch space; align on cacheline */
238 unsigned long normsave[8] ____cacheline_aligned;
241 void *pgdir; /* root of page-table tree */
242 unsigned long ksp_limit; /* if ksp <= ksp_limit stack overflow */
244 /* Debug Registers */
245 struct debug_reg debug;
246 struct thread_fp_state fp_state;
247 struct thread_fp_state *fp_save_area;
248 int fpexc_mode; /* floating-point exception mode */
249 unsigned int align_ctl; /* alignment handling control */
251 unsigned long start_tb; /* Start purr when proc switched in */
252 unsigned long accum_tb; /* Total accumulated purr for process */
254 #ifdef CONFIG_HAVE_HW_BREAKPOINT
255 struct perf_event *ptrace_bps[HBP_NUM];
257 * Helps identify source of single-step exception and subsequent
258 * hw-breakpoint enablement
260 struct perf_event *last_hit_ubp;
261 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
262 struct arch_hw_breakpoint hw_brk; /* info on the hardware breakpoint */
263 unsigned long trap_nr; /* last trap # on this thread */
265 #ifdef CONFIG_ALTIVEC
267 struct thread_vr_state vr_state;
268 struct thread_vr_state *vr_save_area;
269 unsigned long vrsave;
270 int used_vr; /* set if process has used altivec */
271 #endif /* CONFIG_ALTIVEC */
274 int used_vsr; /* set if process has used VSX */
275 #endif /* CONFIG_VSX */
277 unsigned long evr[32]; /* upper 32-bits of SPE regs */
278 u64 acc; /* Accumulator */
279 unsigned long spefscr; /* SPE & eFP status */
280 unsigned long spefscr_last; /* SPEFSCR value on last prctl
281 call or trap return */
282 int used_spe; /* set if process has used spe */
283 #endif /* CONFIG_SPE */
284 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
286 u64 tm_tfhar; /* Transaction fail handler addr */
287 u64 tm_texasr; /* Transaction exception & summary */
288 u64 tm_tfiar; /* Transaction fail instr address reg */
289 struct pt_regs ckpt_regs; /* Checkpointed registers */
291 unsigned long tm_tar;
292 unsigned long tm_ppr;
293 unsigned long tm_dscr;
296 * Checkpointed FP and VSX 0-31 register set.
298 * When a transaction is active/signalled/scheduled etc., *regs is the
299 * most recent set of/speculated GPRs with ckpt_regs being the older
300 * checkpointed regs to which we roll back if transaction aborts.
302 * These are analogous to how ckpt_regs and pt_regs work
304 struct thread_fp_state ckfp_state; /* Checkpointed FP state */
305 struct thread_vr_state ckvr_state; /* Checkpointed VR state */
306 unsigned long ckvrsave; /* Checkpointed VRSAVE */
307 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
308 #ifdef CONFIG_KVM_BOOK3S_32_HANDLER
309 void* kvm_shadow_vcpu; /* KVM internal data */
310 #endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
311 #if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
312 struct kvm_vcpu *kvm_vcpu;
318 * This member element dscr_inherit indicates that the process
319 * has explicitly attempted and changed the DSCR register value
320 * for itself. Hence kernel wont use the default CPU DSCR value
321 * contained in the PACA structure anymore during process context
322 * switch. Once this variable is set, this behaviour will also be
323 * inherited to all the children of this process from that point
327 unsigned long ppr; /* used to save/restore SMT priority */
329 #ifdef CONFIG_PPC_BOOK3S_64
343 #define ARCH_MIN_TASKALIGN 16
345 #define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
346 #define INIT_SP_LIMIT \
347 (_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack)
350 #define SPEFSCR_INIT \
351 .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, \
352 .spefscr_last = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE,
358 #define INIT_THREAD { \
360 .ksp_limit = INIT_SP_LIMIT, \
362 .pgdir = swapper_pg_dir, \
363 .fpexc_mode = MSR_FE0 | MSR_FE1, \
367 #define INIT_THREAD { \
369 .regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \
373 .fscr = FSCR_TAR | FSCR_EBB \
378 * Return saved PC of a blocked thread. For now, this is the "user" PC
380 #define thread_saved_pc(tsk) \
381 ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
383 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.regs)
385 unsigned long get_wchan(struct task_struct *p);
387 #define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
388 #define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
390 /* Get/set floating-point exception mode */
391 #define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
392 #define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
394 extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
395 extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
397 #define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
398 #define SET_ENDIAN(tsk, val) set_endian((tsk), (val))
400 extern int get_endian(struct task_struct *tsk, unsigned long adr);
401 extern int set_endian(struct task_struct *tsk, unsigned int val);
403 #define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr))
404 #define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
406 extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
407 extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
409 extern void load_fp_state(struct thread_fp_state *fp);
410 extern void store_fp_state(struct thread_fp_state *fp);
411 extern void load_vr_state(struct thread_vr_state *vr);
412 extern void store_vr_state(struct thread_vr_state *vr);
414 static inline unsigned int __unpack_fe01(unsigned long msr_bits)
416 return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
419 static inline unsigned long __pack_fe01(unsigned int fpmode)
421 return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
425 #define cpu_relax() do { HMT_low(); HMT_medium(); barrier(); } while (0)
427 #define cpu_relax() barrier()
430 /* Check that a certain kernel stack pointer is valid in task_struct p */
431 int validate_sp(unsigned long sp, struct task_struct *p,
432 unsigned long nbytes);
437 #define ARCH_HAS_PREFETCH
438 #define ARCH_HAS_PREFETCHW
439 #define ARCH_HAS_SPINLOCK_PREFETCH
441 static inline void prefetch(const void *x)
446 __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
449 static inline void prefetchw(const void *x)
454 __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
457 #define spin_lock_prefetch(x) prefetchw(x)
459 #define HAVE_ARCH_PICK_MMAP_LAYOUT
462 static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
465 return sp & 0x0ffffffffUL;
469 static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
475 extern unsigned long cpuidle_disable;
476 enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
478 extern int powersave_nap; /* set if nap mode can be used in idle loop */
479 extern unsigned long power7_nap(int check_irq);
480 extern unsigned long power7_sleep(void);
481 extern unsigned long power7_winkle(void);
482 extern unsigned long power9_idle_stop(unsigned long stop_psscr_val,
483 unsigned long stop_psscr_mask);
485 extern void flush_instruction_cache(void);
486 extern void hard_reset_now(void);
487 extern void poweroff_now(void);
488 extern int fix_alignment(struct pt_regs *);
489 extern void cvt_fd(float *from, double *to);
490 extern void cvt_df(double *from, float *to);
491 extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
495 * We handle most unaligned accesses in hardware. On the other hand
496 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
497 * powers of 2 writes until it reaches sufficient alignment).
499 * Based on this we disable the IP header alignment in network drivers.
501 #define NET_IP_ALIGN 0
504 #endif /* __KERNEL__ */
505 #endif /* __ASSEMBLY__ */
506 #endif /* _ASM_POWERPC_PROCESSOR_H */