2 * Copyright 2017, Nicholas Piggin, IBM Corporation
3 * Licensed under GPLv2.
6 #define pr_fmt(fmt) "dt-cpu-ftrs: " fmt
8 #include <linux/export.h>
9 #include <linux/init.h>
10 #include <linux/jump_label.h>
11 #include <linux/libfdt.h>
12 #include <linux/memblock.h>
13 #include <linux/printk.h>
14 #include <linux/sched.h>
15 #include <linux/string.h>
16 #include <linux/threads.h>
18 #include <asm/cputable.h>
19 #include <asm/dt_cpu_ftrs.h>
21 #include <asm/oprofile_impl.h>
23 #include <asm/setup.h>
26 /* Device-tree visible constants follow */
27 #define ISA_V2_07B 2070
28 #define ISA_V3_0B 3000
30 #define USABLE_PR (1U << 0)
31 #define USABLE_OS (1U << 1)
32 #define USABLE_HV (1U << 2)
34 #define HV_SUPPORT_HFSCR (1U << 0)
35 #define OS_SUPPORT_FSCR (1U << 0)
37 /* For parsing, we define all bits set as "NONE" case */
38 #define HV_SUPPORT_NONE 0xffffffffU
39 #define OS_SUPPORT_NONE 0xffffffffU
41 struct dt_cpu_feature {
44 uint32_t usable_privilege;
47 uint32_t hfscr_bit_nr;
49 uint32_t hwcap_bit_nr;
56 #define CPU_FTRS_BASE \
59 CPU_FTR_FPU_UNAVAILABLE |\
60 CPU_FTR_NODSISRALIGN |\
62 CPU_FTR_COHERENT_ICACHE | \
63 CPU_FTR_STCX_CHECKS_ADDRESS |\
64 CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
69 #define MMU_FTRS_HASH_BASE (MMU_FTRS_POWER8)
71 #define COMMON_USER_BASE (PPC_FEATURE_32 | PPC_FEATURE_64 | \
72 PPC_FEATURE_ARCH_2_06 |\
73 PPC_FEATURE_ICACHE_SNOOP)
74 #define COMMON_USER2_BASE (PPC_FEATURE2_ARCH_2_07 | \
80 extern void __flush_tlb_power8(unsigned int action);
81 extern void __flush_tlb_power9(unsigned int action);
82 extern long __machine_check_early_realmode_p8(struct pt_regs *regs);
83 extern long __machine_check_early_realmode_p9(struct pt_regs *regs);
93 static void (*init_pmu_registers)(void);
95 static void cpufeatures_flush_tlb(void)
98 unsigned int i, num_sets;
101 * This is a temporary measure to keep equivalent TLB flush as the
102 * cputable based setup code.
104 switch (PVR_VER(mfspr(SPRN_PVR))) {
108 num_sets = POWER8_TLB_SETS;
111 num_sets = POWER9_TLB_SETS_HASH;
115 pr_err("unknown CPU version for boot TLB flush\n");
119 asm volatile("ptesync" : : : "memory");
120 rb = TLBIEL_INVAL_SET;
121 for (i = 0; i < num_sets; i++) {
122 asm volatile("tlbiel %0" : : "r" (rb));
123 rb += 1 << TLBIEL_INVAL_SET_SHIFT;
125 asm volatile("ptesync" : : : "memory");
128 static void __restore_cpu_cpufeatures(void)
131 * LPCR is restored by the power on engine already. It can be changed
132 * after early init e.g., by radix enable, and we have no unified API
133 * for saving and restoring such SPRs.
135 * This ->restore hook should really be removed from idle and register
136 * restore moved directly into the idle restore code, because this code
137 * doesn't know how idle is implemented or what it needs restored here.
139 * The best we can do to accommodate secondary boot and idle restore
140 * for now is "or" LPCR with existing.
143 mtspr(SPRN_LPCR, system_registers.lpcr | mfspr(SPRN_LPCR));
146 mtspr(SPRN_HFSCR, system_registers.hfscr);
148 mtspr(SPRN_FSCR, system_registers.fscr);
150 if (init_pmu_registers)
151 init_pmu_registers();
153 cpufeatures_flush_tlb();
156 static char dt_cpu_name[64];
158 static struct cpu_spec __initdata base_cpu_spec = {
160 .cpu_features = CPU_FTRS_BASE,
161 .cpu_user_features = COMMON_USER_BASE,
162 .cpu_user_features2 = COMMON_USER2_BASE,
164 .icache_bsize = 32, /* minimum block size, fixed by */
165 .dcache_bsize = 32, /* cache info init. */
167 .pmc_type = PPC_PMC_DEFAULT,
168 .oprofile_cpu_type = NULL,
169 .oprofile_type = PPC_OPROFILE_INVALID,
171 .cpu_restore = __restore_cpu_cpufeatures,
173 .machine_check_early = NULL,
177 static void __init cpufeatures_setup_cpu(void)
179 set_cur_cpu_spec(&base_cpu_spec);
181 cur_cpu_spec->pvr_mask = -1;
182 cur_cpu_spec->pvr_value = mfspr(SPRN_PVR);
184 /* Initialize the base environment -- clear FSCR/HFSCR. */
185 hv_mode = !!(mfmsr() & MSR_HV);
187 /* CPU_FTR_HVMODE is used early in PACA setup */
188 cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE;
189 mtspr(SPRN_HFSCR, 0);
194 * LPCR does not get cleared, to match behaviour with secondaries
195 * in __restore_cpu_cpufeatures. Once the idle code is fixed, this
196 * could clear LPCR too.
200 static int __init feat_try_enable_unknown(struct dt_cpu_feature *f)
202 if (f->hv_support == HV_SUPPORT_NONE) {
203 } else if (f->hv_support & HV_SUPPORT_HFSCR) {
204 u64 hfscr = mfspr(SPRN_HFSCR);
205 hfscr |= 1UL << f->hfscr_bit_nr;
206 mtspr(SPRN_HFSCR, hfscr);
208 /* Does not have a known recipe */
212 if (f->os_support == OS_SUPPORT_NONE) {
213 } else if (f->os_support & OS_SUPPORT_FSCR) {
214 u64 fscr = mfspr(SPRN_FSCR);
215 fscr |= 1UL << f->fscr_bit_nr;
216 mtspr(SPRN_FSCR, fscr);
218 /* Does not have a known recipe */
222 if ((f->usable_privilege & USABLE_PR) && (f->hwcap_bit_nr != -1)) {
223 uint32_t word = f->hwcap_bit_nr / 32;
224 uint32_t bit = f->hwcap_bit_nr % 32;
227 cur_cpu_spec->cpu_user_features |= 1U << bit;
229 cur_cpu_spec->cpu_user_features2 |= 1U << bit;
231 pr_err("%s could not advertise to user (no hwcap bits)\n", f->name);
237 static int __init feat_enable(struct dt_cpu_feature *f)
239 if (f->hv_support != HV_SUPPORT_NONE) {
240 if (f->hfscr_bit_nr != -1) {
241 u64 hfscr = mfspr(SPRN_HFSCR);
242 hfscr |= 1UL << f->hfscr_bit_nr;
243 mtspr(SPRN_HFSCR, hfscr);
247 if (f->os_support != OS_SUPPORT_NONE) {
248 if (f->fscr_bit_nr != -1) {
249 u64 fscr = mfspr(SPRN_FSCR);
250 fscr |= 1UL << f->fscr_bit_nr;
251 mtspr(SPRN_FSCR, fscr);
255 if ((f->usable_privilege & USABLE_PR) && (f->hwcap_bit_nr != -1)) {
256 uint32_t word = f->hwcap_bit_nr / 32;
257 uint32_t bit = f->hwcap_bit_nr % 32;
260 cur_cpu_spec->cpu_user_features |= 1U << bit;
262 cur_cpu_spec->cpu_user_features2 |= 1U << bit;
264 pr_err("CPU feature: %s could not advertise to user (no hwcap bits)\n", f->name);
270 static int __init feat_disable(struct dt_cpu_feature *f)
275 static int __init feat_enable_hv(struct dt_cpu_feature *f)
280 pr_err("CPU feature hypervisor present in device tree but HV mode not enabled in the CPU. Ignoring.\n");
286 lpcr = mfspr(SPRN_LPCR);
287 lpcr &= ~LPCR_LPES0; /* HV external interrupts */
288 mtspr(SPRN_LPCR, lpcr);
290 cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE;
295 static int __init feat_enable_le(struct dt_cpu_feature *f)
297 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_TRUE_LE;
301 static int __init feat_enable_smt(struct dt_cpu_feature *f)
303 cur_cpu_spec->cpu_features |= CPU_FTR_SMT;
304 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_SMT;
308 static int __init feat_enable_idle_nap(struct dt_cpu_feature *f)
312 /* Set PECE wakeup modes for ISA 207 */
313 lpcr = mfspr(SPRN_LPCR);
317 mtspr(SPRN_LPCR, lpcr);
322 static int __init feat_enable_align_dsisr(struct dt_cpu_feature *f)
324 cur_cpu_spec->cpu_features &= ~CPU_FTR_NODSISRALIGN;
329 static int __init feat_enable_idle_stop(struct dt_cpu_feature *f)
333 /* Set PECE wakeup modes for ISAv3.0B */
334 lpcr = mfspr(SPRN_LPCR);
338 mtspr(SPRN_LPCR, lpcr);
343 static int __init feat_enable_mmu_hash(struct dt_cpu_feature *f)
347 lpcr = mfspr(SPRN_LPCR);
353 lpcr |= 0x10UL << LPCR_VRMASD_SH; /* L=1 LP=00 */
354 mtspr(SPRN_LPCR, lpcr);
356 cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE;
357 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU;
362 static int __init feat_enable_mmu_hash_v3(struct dt_cpu_feature *f)
366 lpcr = mfspr(SPRN_LPCR);
368 mtspr(SPRN_LPCR, lpcr);
370 cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE;
371 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU;
377 static int __init feat_enable_mmu_radix(struct dt_cpu_feature *f)
379 #ifdef CONFIG_PPC_RADIX_MMU
380 cur_cpu_spec->mmu_features |= MMU_FTR_TYPE_RADIX;
381 cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE;
382 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU;
389 static int __init feat_enable_dscr(struct dt_cpu_feature *f)
395 lpcr = mfspr(SPRN_LPCR);
397 lpcr |= (4UL << LPCR_DPFD_SH);
398 mtspr(SPRN_LPCR, lpcr);
403 static void hfscr_pmu_enable(void)
405 u64 hfscr = mfspr(SPRN_HFSCR);
406 hfscr |= PPC_BIT(60);
407 mtspr(SPRN_HFSCR, hfscr);
410 static void init_pmu_power8(void)
413 mtspr(SPRN_MMCRC, 0);
414 mtspr(SPRN_MMCRH, 0);
417 mtspr(SPRN_MMCRA, 0);
418 mtspr(SPRN_MMCR0, 0);
419 mtspr(SPRN_MMCR1, 0);
420 mtspr(SPRN_MMCR2, 0);
421 mtspr(SPRN_MMCRS, 0);
424 static int __init feat_enable_mce_power8(struct dt_cpu_feature *f)
426 cur_cpu_spec->platform = "power8";
427 cur_cpu_spec->flush_tlb = __flush_tlb_power8;
428 cur_cpu_spec->machine_check_early = __machine_check_early_realmode_p8;
433 static int __init feat_enable_pmu_power8(struct dt_cpu_feature *f)
438 init_pmu_registers = init_pmu_power8;
440 cur_cpu_spec->cpu_features |= CPU_FTR_MMCRA;
441 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_PSERIES_PERFMON_COMPAT;
442 if (pvr_version_is(PVR_POWER8E))
443 cur_cpu_spec->cpu_features |= CPU_FTR_PMAO_BUG;
445 cur_cpu_spec->num_pmcs = 6;
446 cur_cpu_spec->pmc_type = PPC_PMC_IBM;
447 cur_cpu_spec->oprofile_cpu_type = "ppc64/power8";
452 static void init_pmu_power9(void)
455 mtspr(SPRN_MMCRC, 0);
457 mtspr(SPRN_MMCRA, 0);
458 mtspr(SPRN_MMCR0, 0);
459 mtspr(SPRN_MMCR1, 0);
460 mtspr(SPRN_MMCR2, 0);
463 static int __init feat_enable_mce_power9(struct dt_cpu_feature *f)
465 cur_cpu_spec->platform = "power9";
466 cur_cpu_spec->flush_tlb = __flush_tlb_power9;
467 cur_cpu_spec->machine_check_early = __machine_check_early_realmode_p9;
472 static int __init feat_enable_pmu_power9(struct dt_cpu_feature *f)
477 init_pmu_registers = init_pmu_power9;
479 cur_cpu_spec->cpu_features |= CPU_FTR_MMCRA;
480 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_PSERIES_PERFMON_COMPAT;
482 cur_cpu_spec->num_pmcs = 6;
483 cur_cpu_spec->pmc_type = PPC_PMC_IBM;
484 cur_cpu_spec->oprofile_cpu_type = "ppc64/power9";
489 static int __init feat_enable_tm(struct dt_cpu_feature *f)
491 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
493 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_HTM_NOSC;
499 static int __init feat_enable_fp(struct dt_cpu_feature *f)
502 cur_cpu_spec->cpu_features &= ~CPU_FTR_FPU_UNAVAILABLE;
507 static int __init feat_enable_vector(struct dt_cpu_feature *f)
509 #ifdef CONFIG_ALTIVEC
511 cur_cpu_spec->cpu_features |= CPU_FTR_ALTIVEC;
512 cur_cpu_spec->cpu_features |= CPU_FTR_VMX_COPY;
513 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_ALTIVEC;
520 static int __init feat_enable_vsx(struct dt_cpu_feature *f)
524 cur_cpu_spec->cpu_features |= CPU_FTR_VSX;
525 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_VSX;
532 static int __init feat_enable_purr(struct dt_cpu_feature *f)
534 cur_cpu_spec->cpu_features |= CPU_FTR_PURR | CPU_FTR_SPURR;
539 static int __init feat_enable_ebb(struct dt_cpu_feature *f)
542 * PPC_FEATURE2_EBB is enabled in PMU init code because it has
543 * historically been related to the PMU facility. This may have
544 * to be decoupled if EBB becomes more generic. For now, follow
545 * existing convention.
547 f->hwcap_bit_nr = -1;
553 static int __init feat_enable_dbell(struct dt_cpu_feature *f)
557 /* P9 has an HFSCR for privileged state */
560 cur_cpu_spec->cpu_features |= CPU_FTR_DBELL;
562 lpcr = mfspr(SPRN_LPCR);
563 lpcr |= LPCR_PECEDH; /* hyp doorbell wakeup */
564 mtspr(SPRN_LPCR, lpcr);
569 static int __init feat_enable_hvi(struct dt_cpu_feature *f)
574 * POWER9 XIVE interrupts including in OPAL XICS compatibility
575 * are always delivered as hypervisor virtualization interrupts (HVI)
578 * However LPES0 is not set here, in the chance that an EE does get
579 * delivered to the host somehow, the EE handler would not expect it
580 * to be delivered in LPES0 mode (e.g., using SRR[01]). This could
581 * happen if there is a bug in interrupt controller code, or IC is
582 * misconfigured in systemsim.
585 lpcr = mfspr(SPRN_LPCR);
586 lpcr |= LPCR_HVICE; /* enable hvi interrupts */
587 lpcr |= LPCR_HEIC; /* disable ee interrupts when MSR_HV */
588 lpcr |= LPCR_PECE_HVEE; /* hvi can wake from stop */
589 mtspr(SPRN_LPCR, lpcr);
594 static int __init feat_enable_large_ci(struct dt_cpu_feature *f)
596 cur_cpu_spec->mmu_features |= MMU_FTR_CI_LARGE_PAGE;
601 struct dt_cpu_feature_match {
603 int (*enable)(struct dt_cpu_feature *f);
604 u64 cpu_ftr_bit_mask;
607 static struct dt_cpu_feature_match __initdata
608 dt_cpu_feature_match_table[] = {
609 {"hypervisor", feat_enable_hv, 0},
610 {"big-endian", feat_enable, 0},
611 {"little-endian", feat_enable_le, CPU_FTR_REAL_LE},
612 {"smt", feat_enable_smt, 0},
613 {"interrupt-facilities", feat_enable, 0},
614 {"timer-facilities", feat_enable, 0},
615 {"timer-facilities-v3", feat_enable, 0},
616 {"debug-facilities", feat_enable, 0},
617 {"come-from-address-register", feat_enable, CPU_FTR_CFAR},
618 {"branch-tracing", feat_enable, 0},
619 {"floating-point", feat_enable_fp, 0},
620 {"vector", feat_enable_vector, 0},
621 {"vector-scalar", feat_enable_vsx, 0},
622 {"vector-scalar-v3", feat_enable, 0},
623 {"decimal-floating-point", feat_enable, 0},
624 {"decimal-integer", feat_enable, 0},
625 {"quadword-load-store", feat_enable, 0},
626 {"vector-crypto", feat_enable, 0},
627 {"mmu-hash", feat_enable_mmu_hash, 0},
628 {"mmu-radix", feat_enable_mmu_radix, 0},
629 {"mmu-hash-v3", feat_enable_mmu_hash_v3, 0},
630 {"virtual-page-class-key-protection", feat_enable, 0},
631 {"transactional-memory", feat_enable_tm, CPU_FTR_TM},
632 {"transactional-memory-v3", feat_enable_tm, 0},
633 {"idle-nap", feat_enable_idle_nap, 0},
634 {"alignment-interrupt-dsisr", feat_enable_align_dsisr, 0},
635 {"idle-stop", feat_enable_idle_stop, 0},
636 {"machine-check-power8", feat_enable_mce_power8, 0},
637 {"performance-monitor-power8", feat_enable_pmu_power8, 0},
638 {"data-stream-control-register", feat_enable_dscr, CPU_FTR_DSCR},
639 {"event-based-branch", feat_enable_ebb, 0},
640 {"target-address-register", feat_enable, 0},
641 {"branch-history-rolling-buffer", feat_enable, 0},
642 {"control-register", feat_enable, CPU_FTR_CTRL},
643 {"processor-control-facility", feat_enable_dbell, CPU_FTR_DBELL},
644 {"processor-control-facility-v3", feat_enable_dbell, CPU_FTR_DBELL},
645 {"processor-utilization-of-resources-register", feat_enable_purr, 0},
646 {"no-execute", feat_enable, 0},
647 {"strong-access-ordering", feat_enable, CPU_FTR_SAO},
648 {"cache-inhibited-large-page", feat_enable_large_ci, 0},
649 {"coprocessor-icswx", feat_enable, CPU_FTR_ICSWX},
650 {"hypervisor-virtualization-interrupt", feat_enable_hvi, 0},
651 {"program-priority-register", feat_enable, CPU_FTR_HAS_PPR},
652 {"wait", feat_enable, 0},
653 {"atomic-memory-operations", feat_enable, 0},
654 {"branch-v3", feat_enable, 0},
655 {"copy-paste", feat_enable, 0},
656 {"decimal-floating-point-v3", feat_enable, 0},
657 {"decimal-integer-v3", feat_enable, 0},
658 {"fixed-point-v3", feat_enable, 0},
659 {"floating-point-v3", feat_enable, 0},
660 {"group-start-register", feat_enable, 0},
661 {"pc-relative-addressing", feat_enable, 0},
662 {"machine-check-power9", feat_enable_mce_power9, 0},
663 {"performance-monitor-power9", feat_enable_pmu_power9, 0},
664 {"event-based-branch-v3", feat_enable, 0},
665 {"random-number-generator", feat_enable, 0},
666 {"system-call-vectored", feat_disable, 0},
667 {"trace-interrupt-v3", feat_enable, 0},
668 {"vector-v3", feat_enable, 0},
669 {"vector-binary128", feat_enable, 0},
670 {"vector-binary16", feat_enable, 0},
671 {"wait-v3", feat_enable, 0},
674 static bool __initdata using_dt_cpu_ftrs;
675 static bool __initdata enable_unknown = true;
677 static int __init dt_cpu_ftrs_parse(char *str)
682 if (!strcmp(str, "off"))
683 using_dt_cpu_ftrs = false;
684 else if (!strcmp(str, "known"))
685 enable_unknown = false;
691 early_param("dt_cpu_ftrs", dt_cpu_ftrs_parse);
693 static void __init cpufeatures_setup_start(u32 isa)
695 pr_info("setup for ISA %d\n", isa);
698 cur_cpu_spec->cpu_features |= CPU_FTR_ARCH_300;
699 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_ARCH_3_00;
703 static bool __init cpufeatures_process_feature(struct dt_cpu_feature *f)
705 const struct dt_cpu_feature_match *m;
709 for (i = 0; i < ARRAY_SIZE(dt_cpu_feature_match_table); i++) {
710 m = &dt_cpu_feature_match_table[i];
711 if (!strcmp(f->name, m->name)) {
716 pr_info("not enabling: %s (disabled or unsupported by kernel)\n",
722 if (!known && enable_unknown) {
723 if (!feat_try_enable_unknown(f)) {
724 pr_info("not enabling: %s (unknown and unsupported by kernel)\n",
730 if (m->cpu_ftr_bit_mask)
731 cur_cpu_spec->cpu_features |= m->cpu_ftr_bit_mask;
734 pr_debug("enabling: %s\n", f->name);
736 pr_debug("enabling: %s (unknown)\n", f->name);
741 static __init void cpufeatures_cpu_quirks(void)
743 int version = mfspr(SPRN_PVR);
746 * Not all quirks can be derived from the cpufeatures device tree.
748 if ((version & 0xffffff00) == 0x004e0100)
749 cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD1;
752 static void __init cpufeatures_setup_finished(void)
754 cpufeatures_cpu_quirks();
756 if (hv_mode && !(cur_cpu_spec->cpu_features & CPU_FTR_HVMODE)) {
757 pr_err("hypervisor not present in device tree but HV mode is enabled in the CPU. Enabling.\n");
758 cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE;
761 system_registers.lpcr = mfspr(SPRN_LPCR);
762 system_registers.hfscr = mfspr(SPRN_HFSCR);
763 system_registers.fscr = mfspr(SPRN_FSCR);
765 cpufeatures_flush_tlb();
767 pr_info("final cpu/mmu features = 0x%016lx 0x%08x\n",
768 cur_cpu_spec->cpu_features, cur_cpu_spec->mmu_features);
771 static int __init disabled_on_cmdline(void)
773 unsigned long root, chosen;
776 root = of_get_flat_dt_root();
777 chosen = of_get_flat_dt_subnode_by_name(root, "chosen");
778 if (chosen == -FDT_ERR_NOTFOUND)
781 p = of_get_flat_dt_prop(chosen, "bootargs", NULL);
785 if (strstr(p, "dt_cpu_ftrs=off"))
791 static int __init fdt_find_cpu_features(unsigned long node, const char *uname,
792 int depth, void *data)
794 if (of_flat_dt_is_compatible(node, "ibm,powerpc-cpu-features")
795 && of_get_flat_dt_prop(node, "isa", NULL))
801 bool __init dt_cpu_ftrs_in_use(void)
803 return using_dt_cpu_ftrs;
806 bool __init dt_cpu_ftrs_init(void *fdt)
808 using_dt_cpu_ftrs = false;
810 /* Setup and verify the FDT, if it fails we just bail */
811 if (!early_init_dt_verify(fdt))
814 if (!of_scan_flat_dt(fdt_find_cpu_features, NULL))
817 if (disabled_on_cmdline())
820 cpufeatures_setup_cpu();
822 using_dt_cpu_ftrs = true;
826 static int nr_dt_cpu_features;
827 static struct dt_cpu_feature *dt_cpu_features;
829 static int __init process_cpufeatures_node(unsigned long node,
830 const char *uname, int i)
833 struct dt_cpu_feature *f;
836 f = &dt_cpu_features[i];
837 memset(f, 0, sizeof(struct dt_cpu_feature));
843 prop = of_get_flat_dt_prop(node, "isa", &len);
845 pr_warn("%s: missing isa property\n", uname);
848 f->isa = be32_to_cpup(prop);
850 prop = of_get_flat_dt_prop(node, "usable-privilege", &len);
852 pr_warn("%s: missing usable-privilege property", uname);
855 f->usable_privilege = be32_to_cpup(prop);
857 prop = of_get_flat_dt_prop(node, "hv-support", &len);
859 f->hv_support = be32_to_cpup(prop);
861 f->hv_support = HV_SUPPORT_NONE;
863 prop = of_get_flat_dt_prop(node, "os-support", &len);
865 f->os_support = be32_to_cpup(prop);
867 f->os_support = OS_SUPPORT_NONE;
869 prop = of_get_flat_dt_prop(node, "hfscr-bit-nr", &len);
871 f->hfscr_bit_nr = be32_to_cpup(prop);
873 f->hfscr_bit_nr = -1;
874 prop = of_get_flat_dt_prop(node, "fscr-bit-nr", &len);
876 f->fscr_bit_nr = be32_to_cpup(prop);
879 prop = of_get_flat_dt_prop(node, "hwcap-bit-nr", &len);
881 f->hwcap_bit_nr = be32_to_cpup(prop);
883 f->hwcap_bit_nr = -1;
885 if (f->usable_privilege & USABLE_HV) {
886 if (!(mfmsr() & MSR_HV)) {
887 pr_warn("%s: HV feature passed to guest\n", uname);
891 if (f->hv_support == HV_SUPPORT_NONE && f->hfscr_bit_nr != -1) {
892 pr_warn("%s: unwanted hfscr_bit_nr\n", uname);
896 if (f->hv_support == HV_SUPPORT_HFSCR) {
897 if (f->hfscr_bit_nr == -1) {
898 pr_warn("%s: missing hfscr_bit_nr\n", uname);
903 if (f->hv_support != HV_SUPPORT_NONE || f->hfscr_bit_nr != -1) {
904 pr_warn("%s: unwanted hv_support/hfscr_bit_nr\n", uname);
909 if (f->usable_privilege & USABLE_OS) {
910 if (f->os_support == OS_SUPPORT_NONE && f->fscr_bit_nr != -1) {
911 pr_warn("%s: unwanted fscr_bit_nr\n", uname);
915 if (f->os_support == OS_SUPPORT_FSCR) {
916 if (f->fscr_bit_nr == -1) {
917 pr_warn("%s: missing fscr_bit_nr\n", uname);
922 if (f->os_support != OS_SUPPORT_NONE || f->fscr_bit_nr != -1) {
923 pr_warn("%s: unwanted os_support/fscr_bit_nr\n", uname);
928 if (!(f->usable_privilege & USABLE_PR)) {
929 if (f->hwcap_bit_nr != -1) {
930 pr_warn("%s: unwanted hwcap_bit_nr\n", uname);
935 /* Do all the independent features in the first pass */
936 if (!of_get_flat_dt_prop(node, "dependencies", &len)) {
937 if (cpufeatures_process_feature(f))
946 static void __init cpufeatures_deps_enable(struct dt_cpu_feature *f)
953 if (f->enabled || f->disabled)
956 prop = of_get_flat_dt_prop(f->node, "dependencies", &len);
958 pr_warn("%s: missing dependencies property", f->name);
962 nr_deps = len / sizeof(int);
964 for (i = 0; i < nr_deps; i++) {
965 unsigned long phandle = be32_to_cpu(prop[i]);
968 for (j = 0; j < nr_dt_cpu_features; j++) {
969 struct dt_cpu_feature *d = &dt_cpu_features[j];
971 if (of_get_flat_dt_phandle(d->node) == phandle) {
972 cpufeatures_deps_enable(d);
981 if (cpufeatures_process_feature(f))
987 static int __init scan_cpufeatures_subnodes(unsigned long node,
993 process_cpufeatures_node(node, uname, *count);
1000 static int __init count_cpufeatures_subnodes(unsigned long node,
1011 static int __init dt_cpu_ftrs_scan_callback(unsigned long node, const char
1012 *uname, int depth, void *data)
1018 /* We are scanning "ibm,powerpc-cpu-features" nodes only */
1019 if (!of_flat_dt_is_compatible(node, "ibm,powerpc-cpu-features"))
1022 prop = of_get_flat_dt_prop(node, "isa", NULL);
1024 /* We checked before, "can't happen" */
1027 isa = be32_to_cpup(prop);
1029 /* Count and allocate space for cpu features */
1030 of_scan_flat_dt_subnodes(node, count_cpufeatures_subnodes,
1031 &nr_dt_cpu_features);
1032 dt_cpu_features = __va(
1033 memblock_alloc(sizeof(struct dt_cpu_feature)*
1034 nr_dt_cpu_features, PAGE_SIZE));
1036 cpufeatures_setup_start(isa);
1038 /* Scan nodes into dt_cpu_features and enable those without deps */
1040 of_scan_flat_dt_subnodes(node, scan_cpufeatures_subnodes, &count);
1042 /* Recursive enable remaining features with dependencies */
1043 for (i = 0; i < nr_dt_cpu_features; i++) {
1044 struct dt_cpu_feature *f = &dt_cpu_features[i];
1046 cpufeatures_deps_enable(f);
1049 prop = of_get_flat_dt_prop(node, "display-name", NULL);
1050 if (prop && strlen((char *)prop) != 0) {
1051 strlcpy(dt_cpu_name, (char *)prop, sizeof(dt_cpu_name));
1052 cur_cpu_spec->cpu_name = dt_cpu_name;
1055 cpufeatures_setup_finished();
1057 memblock_free(__pa(dt_cpu_features),
1058 sizeof(struct dt_cpu_feature)*nr_dt_cpu_features);
1063 void __init dt_cpu_ftrs_scan(void)
1065 if (!using_dt_cpu_ftrs)
1068 of_scan_flat_dt(dt_cpu_ftrs_scan_callback, NULL);