3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@fsmlabs.com) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@fsmlabs.com>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
22 #include <linux/errno.h>
23 #include <linux/sys.h>
24 #include <linux/threads.h>
28 #include <asm/cputable.h>
29 #include <asm/thread_info.h>
30 #include <asm/ppc_asm.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/unistd.h>
33 #include <asm/ftrace.h>
34 #include <asm/ptrace.h>
37 #undef SHOW_SYSCALLS_TASK
40 * MSR_KERNEL is > 0x10000 on 4xx/Book-E since it include MSR_CE.
42 #if MSR_KERNEL >= 0x10000
43 #define LOAD_MSR_KERNEL(r, x) lis r,(x)@h; ori r,r,(x)@l
45 #define LOAD_MSR_KERNEL(r, x) li r,(x)
49 .globl mcheck_transfer_to_handler
50 mcheck_transfer_to_handler:
57 .globl debug_transfer_to_handler
58 debug_transfer_to_handler:
65 .globl crit_transfer_to_handler
66 crit_transfer_to_handler:
67 #ifdef CONFIG_PPC_BOOK3E_MMU
78 #ifdef CONFIG_PHYS_64BIT
81 #endif /* CONFIG_PHYS_64BIT */
82 #endif /* CONFIG_PPC_BOOK3E_MMU */
92 /* set the stack limit to the current stack
93 * and set the limit to protect the thread_info
96 mfspr r8,SPRN_SPRG_THREAD
98 stw r0,SAVED_KSP_LIMIT(r11)
99 rlwimi r0,r1,0,0,(31-THREAD_SHIFT)
105 .globl crit_transfer_to_handler
106 crit_transfer_to_handler:
112 stw r0,crit_srr0@l(0)
114 stw r0,crit_srr1@l(0)
116 /* set the stack limit to the current stack
117 * and set the limit to protect the thread_info
120 mfspr r8,SPRN_SPRG_THREAD
122 stw r0,saved_ksp_limit@l(0)
123 rlwimi r0,r1,0,0,(31-THREAD_SHIFT)
129 * This code finishes saving the registers to the exception frame
130 * and jumps to the appropriate handler for the exception, turning
131 * on address translation.
132 * Note that we rely on the caller having set cr0.eq iff the exception
133 * occurred in kernel mode (i.e. MSR:PR = 0).
135 .globl transfer_to_handler_full
136 transfer_to_handler_full:
140 .globl transfer_to_handler
150 mfspr r12,SPRN_SPRG_THREAD
152 tovirt(r2,r2) /* set r2 to current */
153 beq 2f /* if from user, fix up THREAD.regs */
154 addi r11,r1,STACK_FRAME_OVERHEAD
156 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
157 /* Check to see if the dbcr0 register is set up to debug. Use the
158 internal debug mode bit to do this. */
159 lwz r12,THREAD_DBCR0(r12)
160 andis. r12,r12,DBCR0_IDM@h
162 /* From user and task is ptraced - load up global dbcr0 */
163 li r12,-1 /* clear all pending debug events */
165 lis r11,global_dbcr0@ha
167 addi r11,r11,global_dbcr0@l
169 CURRENT_THREAD_INFO(r9, r1)
182 2: /* if from kernel, check interrupted DOZE/NAP mode and
183 * check for stack overflow
185 lwz r9,KSP_LIMIT(r12)
186 cmplw r1,r9 /* if r1 <= ksp_limit */
187 ble- stack_ovf /* then the kernel stack overflowed */
189 #if defined(CONFIG_6xx) || defined(CONFIG_E500)
190 CURRENT_THREAD_INFO(r9, r1)
191 tophys(r9,r9) /* check local flags */
192 lwz r12,TI_LOCAL_FLAGS(r9)
194 bt- 31-TLF_NAPPING,4f
195 bt- 31-TLF_SLEEPING,7f
196 #endif /* CONFIG_6xx || CONFIG_E500 */
197 .globl transfer_to_handler_cont
198 transfer_to_handler_cont:
201 lwz r11,0(r9) /* virtual address of handler */
202 lwz r9,4(r9) /* where to go when done */
203 #ifdef CONFIG_TRACE_IRQFLAGS
204 lis r12,reenable_mmu@h
205 ori r12,r12,reenable_mmu@l
210 reenable_mmu: /* re-enable mmu so we can */
214 andi. r10,r10,MSR_EE /* Did EE change? */
218 * The trace_hardirqs_off will use CALLER_ADDR0 and CALLER_ADDR1.
219 * If from user mode there is only one stack frame on the stack, and
220 * accessing CALLER_ADDR1 will cause oops. So we need create a dummy
221 * stack frame to make trace_hardirqs_off happy.
223 * This is handy because we also need to save a bunch of GPRs,
224 * r3 can be different from GPR3(r1) at this point, r9 and r11
225 * contains the old MSR and handler address respectively,
226 * r4 & r5 can contain page fault arguments that need to be passed
227 * along as well. r12, CCR, CTR, XER etc... are left clobbered as
228 * they aren't useful past this point (aren't syscall arguments),
229 * the rest is restored from the exception frame.
237 bl trace_hardirqs_off
250 bctr /* jump to handler */
251 #else /* CONFIG_TRACE_IRQFLAGS */
256 RFI /* jump to handler, enable MMU */
257 #endif /* CONFIG_TRACE_IRQFLAGS */
259 #if defined (CONFIG_6xx) || defined(CONFIG_E500)
260 4: rlwinm r12,r12,0,~_TLF_NAPPING
261 stw r12,TI_LOCAL_FLAGS(r9)
262 b power_save_ppc32_restore
264 7: rlwinm r12,r12,0,~_TLF_SLEEPING
265 stw r12,TI_LOCAL_FLAGS(r9)
266 lwz r9,_MSR(r11) /* if sleeping, clear MSR.EE */
267 rlwinm r9,r9,0,~MSR_EE
268 lwz r12,_LINK(r11) /* and return to address in LR */
269 b fast_exception_return
273 * On kernel stack overflow, load up an initial stack pointer
274 * and call StackOverflow(regs), which should not return.
277 /* sometimes we use a statically-allocated stack, which is OK. */
281 ble 5b /* r1 <= &_end is OK */
283 addi r3,r1,STACK_FRAME_OVERHEAD
284 lis r1,init_thread_union@ha
285 addi r1,r1,init_thread_union@l
286 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
287 lis r9,StackOverflow@ha
288 addi r9,r9,StackOverflow@l
289 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
297 * Handle a system call.
299 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
300 .stabs "entry_32.S",N_SO,0,0,0f
307 lwz r11,_CCR(r1) /* Clear SO bit in CR */
312 #endif /* SHOW_SYSCALLS */
313 #ifdef CONFIG_TRACE_IRQFLAGS
314 /* Return from syscalls can (and generally will) hard enable
315 * interrupts. You aren't supposed to call a syscall with
316 * interrupts disabled in the first place. However, to ensure
317 * that we get it right vs. lockdep if it happens, we force
318 * that hard enable here with appropriate tracing if we see
319 * that we have been called with interrupts off
324 /* We came in with interrupts disabled, we enable them now */
337 #endif /* CONFIG_TRACE_IRQFLAGS */
338 CURRENT_THREAD_INFO(r10, r1)
339 lwz r11,TI_FLAGS(r10)
340 andi. r11,r11,_TIF_SYSCALL_T_OR_A
342 syscall_dotrace_cont:
343 cmplwi 0,r0,NR_syscalls
344 lis r10,sys_call_table@h
345 ori r10,r10,sys_call_table@l
348 lwzx r10,r10,r0 /* Fetch system call handler [ptr] */
350 addi r9,r1,STACK_FRAME_OVERHEAD
352 blrl /* Call handler */
353 .globl ret_from_syscall
356 bl do_show_syscall_exit
359 CURRENT_THREAD_INFO(r12, r1)
360 /* disable interrupts so current_thread_info()->flags can't change */
361 LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */
362 /* Note: We don't bother telling lockdep about it */
367 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
368 bne- syscall_exit_work
370 blt+ syscall_exit_cont
371 lwz r11,_CCR(r1) /* Load CR */
373 oris r11,r11,0x1000 /* Set SO bit in CR */
377 #ifdef CONFIG_TRACE_IRQFLAGS
378 /* If we are going to return from the syscall with interrupts
379 * off, we trace that here. It shouldn't happen though but we
380 * want to catch the bugger if it does right ?
385 bl trace_hardirqs_off
388 #endif /* CONFIG_TRACE_IRQFLAGS */
389 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
390 /* If the process has its own DBCR0 value, load it up. The internal
391 debug mode bit tells us that dbcr0 should be loaded. */
392 lwz r0,THREAD+THREAD_DBCR0(r2)
393 andis. r10,r0,DBCR0_IDM@h
397 BEGIN_MMU_FTR_SECTION
398 lis r4,icache_44x_need_flush@ha
399 lwz r5,icache_44x_need_flush@l(r4)
403 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_47x)
404 #endif /* CONFIG_44x */
407 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
408 stwcx. r0,0,r1 /* to clear the reservation */
424 stw r7,icache_44x_need_flush@l(r4)
426 #endif /* CONFIG_44x */
438 .globl ret_from_kernel_thread
439 ret_from_kernel_thread:
447 b do_exit # no return
449 .globl __ret_from_kernel_execve
450 __ret_from_kernel_execve:
451 addi r1,r3,-STACK_FRAME_OVERHEAD
454 /* Traced system call support */
459 addi r3,r1,STACK_FRAME_OVERHEAD
460 bl do_syscall_trace_enter
462 * Restore argument registers possibly just changed.
463 * We use the return value of do_syscall_trace_enter
464 * for call number to look up in the table (r0).
474 b syscall_dotrace_cont
477 andi. r0,r9,_TIF_RESTOREALL
483 andi. r0,r9,_TIF_NOERROR
485 lwz r11,_CCR(r1) /* Load CR */
487 oris r11,r11,0x1000 /* Set SO bit in CR */
490 1: stw r6,RESULT(r1) /* Save result */
491 stw r3,GPR3(r1) /* Update return value */
492 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
495 /* Clear per-syscall TIF flags if any are set. */
497 li r11,_TIF_PERSYSCALL_MASK
498 addi r12,r12,TI_FLAGS
501 #ifdef CONFIG_IBM405_ERR77
506 subi r12,r12,TI_FLAGS
508 4: /* Anything which requires enabling interrupts? */
509 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
512 /* Re-enable interrupts. There is no need to trace that with
513 * lockdep as we are supposed to have IRQs on at this point
519 /* Save NVGPRS if they're not saved already */
527 addi r3,r1,STACK_FRAME_OVERHEAD
528 bl do_syscall_trace_leave
529 b ret_from_except_full
533 #ifdef SHOW_SYSCALLS_TASK
534 lis r11,show_syscalls_task@ha
535 lwz r11,show_syscalls_task@l(r11)
566 do_show_syscall_exit:
567 #ifdef SHOW_SYSCALLS_TASK
568 lis r11,show_syscalls_task@ha
569 lwz r11,show_syscalls_task@l(r11)
575 stw r3,RESULT(r1) /* Save result */
585 7: .string "syscall %d(%x, %x, %x, %x, %x, "
586 77: .string "%x), current=%p\n"
587 79: .string " -> %x\n"
590 #ifdef SHOW_SYSCALLS_TASK
592 .globl show_syscalls_task
597 #endif /* SHOW_SYSCALLS */
600 * The fork/clone functions need to copy the full register set into
601 * the child process. Therefore we need to save all the nonvolatile
602 * registers (r13 - r31) before calling the C code.
608 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
609 stw r0,_TRAP(r1) /* register set saved */
616 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
617 stw r0,_TRAP(r1) /* register set saved */
624 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
625 stw r0,_TRAP(r1) /* register set saved */
628 .globl ppc_swapcontext
632 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
633 stw r0,_TRAP(r1) /* register set saved */
637 * Top-level page fault handling.
638 * This is in assembler because if do_page_fault tells us that
639 * it is a bad kernel page fault, we want to save the non-volatile
640 * registers before calling bad_page_fault.
642 .globl handle_page_fault
645 addi r3,r1,STACK_FRAME_OVERHEAD
654 addi r3,r1,STACK_FRAME_OVERHEAD
657 b ret_from_except_full
660 * This routine switches between two different tasks. The process
661 * state of one is saved on its kernel stack. Then the state
662 * of the other is restored from its kernel stack. The memory
663 * management hardware is updated to the second process's state.
664 * Finally, we can return to the second process.
665 * On entry, r3 points to the THREAD for the current task, r4
666 * points to the THREAD for the new task.
668 * This routine is always called with interrupts disabled.
670 * Note: there are two ways to get to the "going out" portion
671 * of this code; either by coming in via the entry (_switch)
672 * or via "fork" which must set up an environment equivalent
673 * to the "_switch" path. If you change this , you'll have to
674 * change the fork code also.
676 * The code which creates the new task context is in 'copy_thread'
677 * in arch/ppc/kernel/process.c
680 stwu r1,-INT_FRAME_SIZE(r1)
682 stw r0,INT_FRAME_SIZE+4(r1)
683 /* r3-r12 are caller saved -- Cort */
685 stw r0,_NIP(r1) /* Return to switch caller */
687 li r0,MSR_FP /* Disable floating-point */
688 #ifdef CONFIG_ALTIVEC
690 oris r0,r0,MSR_VEC@h /* Disable altivec */
691 mfspr r12,SPRN_VRSAVE /* save vrsave register value */
692 stw r12,THREAD+THREAD_VRSAVE(r2)
693 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
694 #endif /* CONFIG_ALTIVEC */
697 oris r0,r0,MSR_SPE@h /* Disable SPE */
698 mfspr r12,SPRN_SPEFSCR /* save spefscr register value */
699 stw r12,THREAD+THREAD_SPEFSCR(r2)
700 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
701 #endif /* CONFIG_SPE */
702 and. r0,r0,r11 /* FP or altivec or SPE enabled? */
710 stw r1,KSP(r3) /* Set old stack pointer */
713 /* We need a sync somewhere here to make sure that if the
714 * previous task gets rescheduled on another CPU, it sees all
715 * stores it has performed on this one.
718 #endif /* CONFIG_SMP */
722 mtspr SPRN_SPRG_THREAD,r0 /* Update current THREAD phys addr */
723 lwz r1,KSP(r4) /* Load new stack pointer */
725 /* save the old current 'last' for return value */
727 addi r2,r4,-THREAD /* Update current */
729 #ifdef CONFIG_ALTIVEC
731 lwz r0,THREAD+THREAD_VRSAVE(r2)
732 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
733 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
734 #endif /* CONFIG_ALTIVEC */
737 lwz r0,THREAD+THREAD_SPEFSCR(r2)
738 mtspr SPRN_SPEFSCR,r0 /* restore SPEFSCR reg */
739 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
740 #endif /* CONFIG_SPE */
744 /* r3-r12 are destroyed -- Cort */
747 lwz r4,_NIP(r1) /* Return to _switch caller in new task */
749 addi r1,r1,INT_FRAME_SIZE
752 .globl fast_exception_return
753 fast_exception_return:
754 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
755 andi. r10,r9,MSR_RI /* check for recoverable interrupt */
756 beq 1f /* if not, we've got problems */
759 2: REST_4GPRS(3, r11)
774 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
775 /* check if the exception happened in a restartable section */
776 1: lis r3,exc_exit_restart_end@ha
777 addi r3,r3,exc_exit_restart_end@l
780 lis r4,exc_exit_restart@ha
781 addi r4,r4,exc_exit_restart@l
784 lis r3,fee_restarts@ha
786 lwz r5,fee_restarts@l(r3)
788 stw r5,fee_restarts@l(r3)
789 mr r12,r4 /* restart at exc_exit_restart */
798 /* aargh, a nonrecoverable interrupt, panic */
799 /* aargh, we don't know which trap this is */
800 /* but the 601 doesn't implement the RI bit, so assume it's OK */
804 END_FTR_SECTION_IFSET(CPU_FTR_601)
807 addi r3,r1,STACK_FRAME_OVERHEAD
809 ori r10,r10,MSR_KERNEL@l
810 bl transfer_to_handler_full
811 .long nonrecoverable_exception
812 .long ret_from_except
815 .globl ret_from_except_full
816 ret_from_except_full:
820 .globl ret_from_except
822 /* Hard-disable interrupts so that current_thread_info()->flags
823 * can't change between when we test it and when we return
824 * from the interrupt. */
825 /* Note: We don't bother telling lockdep about it */
826 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
827 SYNC /* Some chip revs have problems here... */
828 MTMSRD(r10) /* disable interrupts */
830 lwz r3,_MSR(r1) /* Returning to user mode? */
834 user_exc_return: /* r10 contains MSR_KERNEL here */
835 /* Check current_thread_info()->flags */
836 CURRENT_THREAD_INFO(r9, r1)
838 andi. r0,r9,_TIF_USER_WORK_MASK
842 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
843 /* Check whether this process has its own DBCR0 value. The internal
844 debug mode bit tells us that dbcr0 should be loaded. */
845 lwz r0,THREAD+THREAD_DBCR0(r2)
846 andis. r10,r0,DBCR0_IDM@h
852 /* N.B. the only way to get here is from the beq following ret_from_except. */
854 /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
855 CURRENT_THREAD_INFO(r9, r1)
857 andis. r8,r8,_TIF_EMULATE_STACK_STORE@h
860 addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
863 subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */
864 mr r4,r1 /* src: current exception frame */
865 mr r1,r3 /* Reroute the trampoline frame to r1 */
867 /* Copy from the original to the trampoline. */
868 li r5,INT_FRAME_SIZE/4 /* size: INT_FRAME_SIZE */
869 li r6,0 /* start offset: 0 */
876 /* Do real store operation to complete stwu */
880 /* Clear _TIF_EMULATE_STACK_STORE flag */
881 lis r11,_TIF_EMULATE_STACK_STORE@h
885 #ifdef CONFIG_IBM405_ERR77
892 #ifdef CONFIG_PREEMPT
893 /* check current_thread_info->preempt_count */
894 lwz r0,TI_PREEMPT(r9)
895 cmpwi 0,r0,0 /* if non-zero, just restore regs and return */
897 andi. r8,r8,_TIF_NEED_RESCHED
900 andi. r0,r3,MSR_EE /* interrupts off? */
901 beq restore /* don't schedule if so */
902 #ifdef CONFIG_TRACE_IRQFLAGS
903 /* Lockdep thinks irqs are enabled, we need to call
904 * preempt_schedule_irq with IRQs off, so we inform lockdep
905 * now that we -did- turn them off already
907 bl trace_hardirqs_off
909 1: bl preempt_schedule_irq
910 CURRENT_THREAD_INFO(r9, r1)
912 andi. r0,r3,_TIF_NEED_RESCHED
914 #ifdef CONFIG_TRACE_IRQFLAGS
915 /* And now, to properly rebalance the above, we tell lockdep they
916 * are being turned back on, which will happen when we return
920 #endif /* CONFIG_PREEMPT */
922 /* interrupts are hard-disabled at this point */
925 BEGIN_MMU_FTR_SECTION
927 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x)
928 lis r4,icache_44x_need_flush@ha
929 lwz r5,icache_44x_need_flush@l(r4)
934 stw r6,icache_44x_need_flush@l(r4)
936 #endif /* CONFIG_44x */
939 #ifdef CONFIG_TRACE_IRQFLAGS
940 /* Lockdep doesn't know about the fact that IRQs are temporarily turned
941 * off in this assembly code while peeking at TI_FLAGS() and such. However
942 * we need to inform it if the exception turned interrupts off, and we
943 * are about to trun them back on.
945 * The problem here sadly is that we don't know whether the exceptions was
946 * one that turned interrupts off or not. So we always tell lockdep about
947 * turning them on here when we go back to wherever we came from with EE
948 * on, even if that may meen some redudant calls being tracked. Maybe later
949 * we could encode what the exception did somewhere or test the exception
950 * type in the pt_regs but that sounds overkill
955 * Since the ftrace irqsoff latency trace checks CALLER_ADDR1,
956 * which is the stack frame here, we need to force a stack frame
957 * in case we came from user space.
968 #endif /* CONFIG_TRACE_IRQFLAGS */
983 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
984 stwcx. r0,0,r1 /* to clear the reservation */
986 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
987 andi. r10,r9,MSR_RI /* check if this exception occurred */
988 beql nonrecoverable /* at a bad place (MSR:RI = 0) */
996 * Once we put values in SRR0 and SRR1, we are in a state
997 * where exceptions are not recoverable, since taking an
998 * exception will trash SRR0 and SRR1. Therefore we clear the
999 * MSR:RI bit to indicate this. If we do take an exception,
1000 * we can't return to the point of the exception but we
1001 * can restart the exception exit path at the label
1002 * exc_exit_restart below. -- paulus
1004 LOAD_MSR_KERNEL(r10,MSR_KERNEL & ~MSR_RI)
1006 MTMSRD(r10) /* clear the RI bit */
1007 .globl exc_exit_restart
1015 .globl exc_exit_restart_end
1016 exc_exit_restart_end:
1020 #else /* !(CONFIG_4xx || CONFIG_BOOKE) */
1022 * This is a bit different on 4xx/Book-E because it doesn't have
1023 * the RI bit in the MSR.
1024 * The TLB miss handler checks if we have interrupted
1025 * the exception exit path and restarts it if so
1026 * (well maybe one day it will... :).
1033 .globl exc_exit_restart
1042 .globl exc_exit_restart_end
1043 exc_exit_restart_end:
1046 b . /* prevent prefetch past rfi */
1049 * Returning from a critical interrupt in user mode doesn't need
1050 * to be any different from a normal exception. For a critical
1051 * interrupt in the kernel, we just return (without checking for
1052 * preemption) since the interrupt may have happened at some crucial
1053 * place (e.g. inside the TLB miss handler), and because we will be
1054 * running with r1 pointing into critical_stack, not the current
1055 * process's kernel stack (and therefore current_thread_info() will
1056 * give the wrong answer).
1057 * We have to restore various SPRs that may have been in use at the
1058 * time of the critical interrupt.
1062 #define PPC_40x_TURN_OFF_MSR_DR \
1063 /* avoid any possible TLB misses here by turning off MSR.DR, we \
1064 * assume the instructions here are mapped by a pinned TLB entry */ \
1070 #define PPC_40x_TURN_OFF_MSR_DR
1073 #define RET_FROM_EXC_LEVEL(exc_lvl_srr0, exc_lvl_srr1, exc_lvl_rfi) \
1076 andi. r3,r3,MSR_PR; \
1077 LOAD_MSR_KERNEL(r10,MSR_KERNEL); \
1078 bne user_exc_return; \
1081 REST_4GPRS(3, r1); \
1082 REST_2GPRS(7, r1); \
1085 mtspr SPRN_XER,r10; \
1087 PPC405_ERR77(0,r1); \
1088 stwcx. r0,0,r1; /* to clear the reservation */ \
1089 lwz r11,_LINK(r1); \
1093 PPC_40x_TURN_OFF_MSR_DR; \
1096 mtspr SPRN_DEAR,r9; \
1097 mtspr SPRN_ESR,r10; \
1100 mtspr exc_lvl_srr0,r11; \
1101 mtspr exc_lvl_srr1,r12; \
1103 lwz r12,GPR12(r1); \
1104 lwz r10,GPR10(r1); \
1105 lwz r11,GPR11(r1); \
1107 PPC405_ERR77_SYNC; \
1109 b .; /* prevent prefetch past exc_lvl_rfi */
1111 #define RESTORE_xSRR(exc_lvl_srr0, exc_lvl_srr1) \
1112 lwz r9,_##exc_lvl_srr0(r1); \
1113 lwz r10,_##exc_lvl_srr1(r1); \
1114 mtspr SPRN_##exc_lvl_srr0,r9; \
1115 mtspr SPRN_##exc_lvl_srr1,r10;
1117 #if defined(CONFIG_PPC_BOOK3E_MMU)
1118 #ifdef CONFIG_PHYS_64BIT
1119 #define RESTORE_MAS7 \
1121 mtspr SPRN_MAS7,r11;
1123 #define RESTORE_MAS7
1124 #endif /* CONFIG_PHYS_64BIT */
1125 #define RESTORE_MMU_REGS \
1129 mtspr SPRN_MAS0,r9; \
1131 mtspr SPRN_MAS1,r10; \
1133 mtspr SPRN_MAS2,r11; \
1134 mtspr SPRN_MAS3,r9; \
1135 mtspr SPRN_MAS6,r10; \
1137 #elif defined(CONFIG_44x)
1138 #define RESTORE_MMU_REGS \
1140 mtspr SPRN_MMUCR,r9;
1142 #define RESTORE_MMU_REGS
1146 .globl ret_from_crit_exc
1148 mfspr r9,SPRN_SPRG_THREAD
1149 lis r10,saved_ksp_limit@ha;
1150 lwz r10,saved_ksp_limit@l(r10);
1152 stw r10,KSP_LIMIT(r9)
1153 lis r9,crit_srr0@ha;
1154 lwz r9,crit_srr0@l(r9);
1155 lis r10,crit_srr1@ha;
1156 lwz r10,crit_srr1@l(r10);
1158 mtspr SPRN_SRR1,r10;
1159 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
1160 #endif /* CONFIG_40x */
1163 .globl ret_from_crit_exc
1165 mfspr r9,SPRN_SPRG_THREAD
1166 lwz r10,SAVED_KSP_LIMIT(r1)
1167 stw r10,KSP_LIMIT(r9)
1168 RESTORE_xSRR(SRR0,SRR1);
1170 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
1172 .globl ret_from_debug_exc
1174 mfspr r9,SPRN_SPRG_THREAD
1175 lwz r10,SAVED_KSP_LIMIT(r1)
1176 stw r10,KSP_LIMIT(r9)
1177 lwz r9,THREAD_INFO-THREAD(r9)
1178 CURRENT_THREAD_INFO(r10, r1)
1179 lwz r10,TI_PREEMPT(r10)
1180 stw r10,TI_PREEMPT(r9)
1181 RESTORE_xSRR(SRR0,SRR1);
1182 RESTORE_xSRR(CSRR0,CSRR1);
1184 RET_FROM_EXC_LEVEL(SPRN_DSRR0, SPRN_DSRR1, PPC_RFDI)
1186 .globl ret_from_mcheck_exc
1187 ret_from_mcheck_exc:
1188 mfspr r9,SPRN_SPRG_THREAD
1189 lwz r10,SAVED_KSP_LIMIT(r1)
1190 stw r10,KSP_LIMIT(r9)
1191 RESTORE_xSRR(SRR0,SRR1);
1192 RESTORE_xSRR(CSRR0,CSRR1);
1193 RESTORE_xSRR(DSRR0,DSRR1);
1195 RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, PPC_RFMCI)
1196 #endif /* CONFIG_BOOKE */
1199 * Load the DBCR0 value for a task that is being ptraced,
1200 * having first saved away the global DBCR0. Note that r0
1201 * has the dbcr0 value to set upon entry to this.
1204 mfmsr r10 /* first disable debug exceptions */
1205 rlwinm r10,r10,0,~MSR_DE
1208 mfspr r10,SPRN_DBCR0
1209 lis r11,global_dbcr0@ha
1210 addi r11,r11,global_dbcr0@l
1212 CURRENT_THREAD_INFO(r9, r1)
1223 mtspr SPRN_DBSR,r11 /* clear all pending debug events */
1231 #endif /* !(CONFIG_4xx || CONFIG_BOOKE) */
1233 do_work: /* r10 contains MSR_KERNEL here */
1234 andi. r0,r9,_TIF_NEED_RESCHED
1237 do_resched: /* r10 contains MSR_KERNEL here */
1238 /* Note: We don't need to inform lockdep that we are enabling
1239 * interrupts here. As far as it knows, they are already enabled
1243 MTMSRD(r10) /* hard-enable interrupts */
1246 /* Note: And we don't tell it we are disabling them again
1247 * neither. Those disable/enable cycles used to peek at
1248 * TI_FLAGS aren't advertised.
1250 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
1252 MTMSRD(r10) /* disable interrupts */
1253 CURRENT_THREAD_INFO(r9, r1)
1255 andi. r0,r9,_TIF_NEED_RESCHED
1257 andi. r0,r9,_TIF_USER_WORK_MASK
1259 do_user_signal: /* r10 contains MSR_KERNEL here */
1262 MTMSRD(r10) /* hard-enable interrupts */
1263 /* save r13-r31 in the exception frame, if not already done */
1270 2: addi r3,r1,STACK_FRAME_OVERHEAD
1277 * We come here when we are at the end of handling an exception
1278 * that occurred at a place where taking an exception will lose
1279 * state information, such as the contents of SRR0 and SRR1.
1282 lis r10,exc_exit_restart_end@ha
1283 addi r10,r10,exc_exit_restart_end@l
1286 lis r11,exc_exit_restart@ha
1287 addi r11,r11,exc_exit_restart@l
1290 lis r10,ee_restarts@ha
1291 lwz r12,ee_restarts@l(r10)
1293 stw r12,ee_restarts@l(r10)
1294 mr r12,r11 /* restart at exc_exit_restart */
1296 3: /* OK, we can't recover, kill this process */
1297 /* but the 601 doesn't implement the RI bit, so assume it's OK */
1300 END_FTR_SECTION_IFSET(CPU_FTR_601)
1307 4: addi r3,r1,STACK_FRAME_OVERHEAD
1308 bl nonrecoverable_exception
1309 /* shouldn't return */
1319 * PROM code for specific machines follows. Put it
1320 * here so it's easy to add arch-specific sections later.
1323 #ifdef CONFIG_PPC_RTAS
1325 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
1326 * called with the MMU off.
1329 stwu r1,-INT_FRAME_SIZE(r1)
1331 stw r0,INT_FRAME_SIZE+4(r1)
1332 LOAD_REG_ADDR(r4, rtas)
1333 lis r6,1f@ha /* physical return address for rtas */
1337 lwz r8,RTASENTRY(r4)
1341 LOAD_MSR_KERNEL(r0,MSR_KERNEL)
1342 SYNC /* disable interrupts so SRR0/1 */
1343 MTMSRD(r0) /* don't get trashed */
1344 li r9,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1346 mtspr SPRN_SPRG_RTAS,r7
1351 lwz r8,INT_FRAME_SIZE+4(r9) /* get return address */
1352 lwz r9,8(r9) /* original msr value */
1354 addi r1,r1,INT_FRAME_SIZE
1356 mtspr SPRN_SPRG_RTAS,r0
1359 RFI /* return to caller */
1361 .globl machine_check_in_rtas
1362 machine_check_in_rtas:
1364 /* XXX load up BATs and panic */
1366 #endif /* CONFIG_PPC_RTAS */
1368 #ifdef CONFIG_FUNCTION_TRACER
1369 #ifdef CONFIG_DYNAMIC_FTRACE
1373 * It is required that _mcount on PPC32 must preserve the
1374 * link register. But we have r0 to play with. We use r0
1375 * to push the return address back to the caller of mcount
1376 * into the ctr register, restore the link register and
1377 * then jump back using the ctr register.
1385 _GLOBAL(ftrace_caller)
1387 /* r3 ends up with link register */
1388 subi r3, r3, MCOUNT_INSN_SIZE
1393 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1394 .globl ftrace_graph_call
1397 _GLOBAL(ftrace_graph_stub)
1399 MCOUNT_RESTORE_FRAME
1400 /* old link register ends up in ctr reg */
1408 subi r3, r3, MCOUNT_INSN_SIZE
1409 LOAD_REG_ADDR(r5, ftrace_trace_function)
1416 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1417 b ftrace_graph_caller
1419 MCOUNT_RESTORE_FRAME
1423 _GLOBAL(ftrace_stub)
1426 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1427 _GLOBAL(ftrace_graph_caller)
1428 /* load r4 with local address */
1430 subi r4, r4, MCOUNT_INSN_SIZE
1432 /* get the parent address */
1435 bl prepare_ftrace_return
1438 MCOUNT_RESTORE_FRAME
1439 /* old link register ends up in ctr reg */
1442 _GLOBAL(return_to_handler)
1443 /* need to save return values */
1450 bl ftrace_return_to_handler
1453 /* return value has real return address */
1461 /* Jump back to real return address */
1463 #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
1465 #endif /* CONFIG_MCOUNT */