3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
21 #include <linux/errno.h>
22 #include <asm/unistd.h>
23 #include <asm/processor.h>
26 #include <asm/thread_info.h>
27 #include <asm/ppc_asm.h>
28 #include <asm/asm-offsets.h>
29 #include <asm/cputable.h>
30 #include <asm/firmware.h>
32 #include <asm/ptrace.h>
33 #include <asm/irqflags.h>
34 #include <asm/ftrace.h>
41 .tc .sys_call_table[TC],.sys_call_table
43 /* This value is used to mark exception frames on the stack. */
45 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
52 .globl system_call_common
56 addi r1,r1,-INT_FRAME_SIZE
64 ACCOUNT_CPU_USER_ENTRY(r10, r11)
66 * This "crclr so" clears CR0.SO, which is the error indication on
67 * return from this system call. There must be no cmp instruction
68 * between it and the "mfcr r9" below, otherwise if XER.SO is set,
69 * CR0.SO will get set, causing all system calls to appear to fail.
97 addi r9,r1,STACK_FRAME_OVERHEAD
98 ld r11,exception_marker@toc(r2)
99 std r11,-16(r9) /* "regshere" marker */
100 #if defined(CONFIG_VIRT_CPU_ACCOUNTING) && defined(CONFIG_PPC_SPLPAR)
103 /* if from user, see if there are any DTL entries to process */
104 ld r10,PACALPPACAPTR(r13) /* get ptr to VPA */
105 ld r11,PACA_DTL_RIDX(r13) /* get log read index */
106 ld r10,LPPACA_DTLIDX(r10) /* get log write index */
109 bl .accumulate_stolen_time
113 addi r9,r1,STACK_FRAME_OVERHEAD
115 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
116 #endif /* CONFIG_VIRT_CPU_ACCOUNTING && CONFIG_PPC_SPLPAR */
119 * A syscall should always be called with interrupts enabled
120 * so we just unconditionally hard-enable here. When some kind
121 * of irq tracing is used, we additionally check that condition
124 #if defined(CONFIG_TRACE_IRQFLAGS) && defined(CONFIG_BUG)
125 lbz r10,PACASOFTIRQEN(r13)
128 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
131 #ifdef CONFIG_PPC_BOOK3E
137 #endif /* CONFIG_PPC_BOOK3E */
139 /* We do need to set SOFTE in the stack frame or the return
140 * from interrupt will be painful
150 addi r9,r1,STACK_FRAME_OVERHEAD
152 clrrdi r11,r1,THREAD_SHIFT
154 andi. r11,r10,_TIF_SYSCALL_T_OR_A
156 syscall_dotrace_cont:
157 cmpldi 0,r0,NR_syscalls
160 system_call: /* label this so stack traces look sane */
162 * Need to vector to 32 Bit or default sys_call_table here,
163 * based on caller's run-mode / personality.
165 ld r11,.SYS_CALL_TABLE@toc(2)
166 andi. r10,r10,_TIF_32BIT
168 addi r11,r11,8 /* use 32-bit syscall entries */
177 ldx r10,r11,r0 /* Fetch system call handler [ptr] */
179 bctrl /* Call handler */
184 bl .do_show_syscall_exit
187 clrrdi r12,r1,THREAD_SHIFT
190 #ifdef CONFIG_PPC_BOOK3S
191 /* No MSR:RI on BookE */
196 * Disable interrupts so current_thread_info()->flags can't change,
197 * and so that we don't get interrupted after loading SRR0/1.
199 #ifdef CONFIG_PPC_BOOK3E
204 #endif /* CONFIG_PPC_BOOK3E */
208 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
209 bne- syscall_exit_work
216 stdcx. r0,0,r1 /* to clear the reservation */
217 END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
221 * Clear RI before restoring r13. If we are returning to
222 * userspace and we take an exception after restoring r13,
223 * we end up corrupting the userspace r13 value.
225 #ifdef CONFIG_PPC_BOOK3S
226 /* No MSR:RI on BookE */
229 mtmsrd r11,1 /* clear MSR.RI */
230 #endif /* CONFIG_PPC_BOOK3S */
233 ACCOUNT_CPU_USER_EXIT(r11, r12)
234 ld r13,GPR13(r1) /* only restore r13 if returning to usermode */
242 b . /* prevent speculative execution */
245 oris r5,r5,0x1000 /* Set SO bit in CR */
250 /* Traced system call support */
253 addi r3,r1,STACK_FRAME_OVERHEAD
254 bl .do_syscall_trace_enter
256 * Restore argument registers possibly just changed.
257 * We use the return value of do_syscall_trace_enter
258 * for the call number to look up in the table (r0).
267 addi r9,r1,STACK_FRAME_OVERHEAD
268 clrrdi r10,r1,THREAD_SHIFT
270 b syscall_dotrace_cont
277 /* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr.
278 If TIF_NOERROR is set, just save r3 as it is. */
280 andi. r0,r9,_TIF_RESTOREALL
284 0: cmpld r3,r11 /* r10 is -LAST_ERRNO */
286 andi. r0,r9,_TIF_NOERROR
290 oris r5,r5,0x1000 /* Set SO bit in CR */
293 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
296 /* Clear per-syscall TIF flags if any are set. */
298 li r11,_TIF_PERSYSCALL_MASK
299 addi r12,r12,TI_FLAGS
304 subi r12,r12,TI_FLAGS
306 4: /* Anything else left to do? */
307 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
308 beq .ret_from_except_lite
310 /* Re-enable interrupts */
311 #ifdef CONFIG_PPC_BOOK3E
317 #endif /* CONFIG_PPC_BOOK3E */
320 addi r3,r1,STACK_FRAME_OVERHEAD
321 bl .do_syscall_trace_leave
324 /* Save non-volatile GPRs, if not already saved. */
336 * The sigsuspend and rt_sigsuspend system calls can call do_signal
337 * and thus put the process into the stopped state where we might
338 * want to examine its user state with ptrace. Therefore we need
339 * to save all the nonvolatile registers (r14 - r31) before calling
340 * the C code. Similarly, fork, vfork and clone need the full
341 * register state on the stack so that it can be copied to the child.
359 _GLOBAL(ppc32_swapcontext)
361 bl .compat_sys_swapcontext
364 _GLOBAL(ppc64_swapcontext)
369 _GLOBAL(ret_from_fork)
376 * This routine switches between two different tasks. The process
377 * state of one is saved on its kernel stack. Then the state
378 * of the other is restored from its kernel stack. The memory
379 * management hardware is updated to the second process's state.
380 * Finally, we can return to the second process, via ret_from_except.
381 * On entry, r3 points to the THREAD for the current task, r4
382 * points to the THREAD for the new task.
384 * Note: there are two ways to get to the "going out" portion
385 * of this code; either by coming in via the entry (_switch)
386 * or via "fork" which must set up an environment equivalent
387 * to the "_switch" path. If you change this you'll have to change
388 * the fork code also.
390 * The code which creates the new task context is in 'copy_thread'
391 * in arch/powerpc/kernel/process.c
397 stdu r1,-SWITCH_FRAME_SIZE(r1)
398 /* r3-r13 are caller saved -- Cort */
401 mflr r20 /* Return to switch caller */
406 oris r0,r0,MSR_VSX@h /* Disable VSX */
407 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
408 #endif /* CONFIG_VSX */
409 #ifdef CONFIG_ALTIVEC
411 oris r0,r0,MSR_VEC@h /* Disable altivec */
412 mfspr r24,SPRN_VRSAVE /* save vrsave register value */
413 std r24,THREAD_VRSAVE(r3)
414 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
415 #endif /* CONFIG_ALTIVEC */
419 std r25,THREAD_DSCR(r3)
420 END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
430 std r1,KSP(r3) /* Set old stack pointer */
433 /* We need a sync somewhere here to make sure that if the
434 * previous task gets rescheduled on another CPU, it sees all
435 * stores it has performed on this one.
438 #endif /* CONFIG_SMP */
441 * If we optimise away the clear of the reservation in system
442 * calls because we know the CPU tracks the address of the
443 * reservation, then we need to clear it here to cover the
444 * case that the kernel context switch path has no larx
449 END_FTR_SECTION_IFSET(CPU_FTR_STCX_CHECKS_ADDRESS)
451 addi r6,r4,-THREAD /* Convert THREAD to 'current' */
452 std r6,PACACURRENT(r13) /* Set new 'current' */
454 ld r8,KSP(r4) /* new stack pointer */
455 #ifdef CONFIG_PPC_BOOK3S
457 BEGIN_FTR_SECTION_NESTED(95)
458 clrrdi r6,r8,28 /* get its ESID */
459 clrrdi r9,r1,28 /* get current sp ESID */
460 FTR_SECTION_ELSE_NESTED(95)
461 clrrdi r6,r8,40 /* get its 1T ESID */
462 clrrdi r9,r1,40 /* get current sp 1T ESID */
463 ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_1T_SEGMENT, 95)
466 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_SLB)
467 clrldi. r0,r6,2 /* is new ESID c00000000? */
468 cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
470 beq 2f /* if yes, don't slbie it */
472 /* Bolt in the new stack SLB entry */
473 ld r7,KSP_VSID(r4) /* Get new stack's VSID */
474 oris r0,r6,(SLB_ESID_V)@h
475 ori r0,r0,(SLB_NUM_BOLTED-1)@l
477 li r9,MMU_SEGSIZE_1T /* insert B field */
478 oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
479 rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0
480 END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
482 /* Update the last bolted SLB. No write barriers are needed
483 * here, provided we only update the current CPU's SLB shadow
486 ld r9,PACA_SLBSHADOWPTR(r13)
488 std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
489 std r7,SLBSHADOW_STACKVSID(r9) /* Save VSID */
490 std r0,SLBSHADOW_STACKESID(r9) /* Save ESID */
492 /* No need to check for MMU_FTR_NO_SLBIE_B here, since when
493 * we have 1TB segments, the only CPUs known to have the errata
494 * only support less than 1TB of system memory and we'll never
495 * actually hit this code path.
499 slbie r6 /* Workaround POWER5 < DD2.1 issue */
503 #endif /* !CONFIG_PPC_BOOK3S */
505 clrrdi r7,r8,THREAD_SHIFT /* base of new stack */
506 /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
507 because we don't need to leave the 288-byte ABI gap at the
508 top of the kernel stack. */
509 addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE
511 mr r1,r8 /* start using new stack pointer */
512 std r7,PACAKSAVE(r13)
517 #ifdef CONFIG_ALTIVEC
519 ld r0,THREAD_VRSAVE(r4)
520 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
521 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
522 #endif /* CONFIG_ALTIVEC */
525 ld r0,THREAD_DSCR(r4)
530 END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
533 /* r3-r13 are destroyed -- Cort */
537 /* convert old thread to its task_struct for return value */
539 ld r7,_NIP(r1) /* Return to _switch caller in new task */
541 addi r1,r1,SWITCH_FRAME_SIZE
545 _GLOBAL(ret_from_except)
548 bne .ret_from_except_lite
551 _GLOBAL(ret_from_except_lite)
553 * Disable interrupts so that current_thread_info()->flags
554 * can't change between when we test it and when we return
555 * from the interrupt.
557 #ifdef CONFIG_PPC_BOOK3E
560 mfmsr r10 /* Get current interrupt state */
561 rldicl r9,r10,48,1 /* clear MSR_EE */
563 mtmsrd r9,1 /* Update machine state */
564 #endif /* CONFIG_PPC_BOOK3E */
566 #ifdef CONFIG_PREEMPT
567 clrrdi r9,r1,THREAD_SHIFT /* current_thread_info() */
568 li r0,_TIF_NEED_RESCHED /* bits to check */
571 /* Move MSR_PR bit in r3 to _TIF_SIGPENDING position in r0 */
572 rlwimi r0,r3,32+TIF_SIGPENDING-MSR_PR_LG,_TIF_SIGPENDING
573 and. r0,r4,r0 /* check NEED_RESCHED and maybe SIGPENDING */
576 #else /* !CONFIG_PREEMPT */
577 ld r3,_MSR(r1) /* Returning to user mode? */
579 beq restore /* if not, just restore regs and return */
581 /* Check current_thread_info()->flags */
582 clrrdi r9,r1,THREAD_SHIFT
584 andi. r0,r4,_TIF_USER_WORK_MASK
586 #endif /* !CONFIG_PREEMPT */
590 TRACE_AND_RESTORE_IRQ(r5);
592 /* extract EE bit and use it to restore paca->hard_enabled */
594 rldicl r4,r3,49,63 /* r0 = (r3 >> 15) & 1 */
595 stb r4,PACAHARDIRQEN(r13)
597 #ifdef CONFIG_PPC_BOOK3E
598 b .exception_return_book3e
613 * Clear the reservation. If we know the CPU tracks the address of
614 * the reservation then we can potentially save some cycles and use
615 * a larx. On POWER6 and POWER7 this is significantly faster.
618 stdcx. r0,0,r1 /* to clear the reservation */
621 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
624 * Clear RI before restoring r13. If we are returning to
625 * userspace and we take an exception after restoring r13,
626 * we end up corrupting the userspace r13 value.
629 andc r4,r4,r0 /* r0 contains MSR_RI here */
633 * r13 is our per cpu area, only restore it if we are returning to
638 ACCOUNT_CPU_USER_EXIT(r2, r4)
655 b . /* prevent speculative execution */
657 #endif /* CONFIG_PPC_BOOK3E */
660 #ifdef CONFIG_PREEMPT
661 andi. r0,r3,MSR_PR /* Returning to user mode? */
663 /* Check that preempt_count() == 0 and interrupts are enabled */
664 lwz r8,TI_PREEMPT(r9)
668 crandc eq,cr1*4+eq,eq
671 /* Here we are preempting the current task.
673 * Ensure interrupts are soft-disabled. We also properly mark
674 * the PACA to reflect the fact that they are hard-disabled
675 * and trace the change
678 stb r0,PACASOFTIRQEN(r13)
679 stb r0,PACAHARDIRQEN(r13)
682 /* Call the scheduler with soft IRQs off */
683 1: bl .preempt_schedule_irq
685 /* Hard-disable interrupts again (and update PACA) */
686 #ifdef CONFIG_PPC_BOOK3E
693 #endif /* CONFIG_PPC_BOOK3E */
695 stb r0,PACAHARDIRQEN(r13)
697 /* Re-test flags and eventually loop */
698 clrrdi r9,r1,THREAD_SHIFT
700 andi. r0,r4,_TIF_NEED_RESCHED
705 #endif /* CONFIG_PREEMPT */
707 /* Enable interrupts */
708 #ifdef CONFIG_PPC_BOOK3E
713 #endif /* CONFIG_PPC_BOOK3E */
715 andi. r0,r4,_TIF_NEED_RESCHED
718 TRACE_AND_RESTORE_IRQ(r5);
720 b .ret_from_except_lite
724 TRACE_AND_RESTORE_IRQ(r5);
725 addi r3,r1,STACK_FRAME_OVERHEAD
730 addi r3,r1,STACK_FRAME_OVERHEAD
731 bl .unrecoverable_exception
734 #ifdef CONFIG_PPC_RTAS
736 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
737 * called with the MMU off.
739 * In addition, we need to be in 32b mode, at least for now.
741 * Note: r3 is an input parameter to rtas, so don't trash it...
746 stdu r1,-RTAS_FRAME_SIZE(r1) /* Save SP and create stack space. */
748 /* Because RTAS is running in 32b mode, it clobbers the high order half
749 * of all registers that it saves. We therefore save those registers
750 * RTAS might touch to the stack. (r0, r3-r13 are caller saved)
752 SAVE_GPR(2, r1) /* Save the TOC */
753 SAVE_GPR(13, r1) /* Save paca */
754 SAVE_8GPRS(14, r1) /* Save the non-volatiles */
755 SAVE_10GPRS(22, r1) /* ditto */
768 /* Temporary workaround to clear CR until RTAS can be modified to
775 /* There is no way it is acceptable to get here with interrupts enabled,
776 * check it with the asm equivalent of WARN_ON
778 lbz r0,PACASOFTIRQEN(r13)
780 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
783 /* Hard-disable interrupts */
789 /* Unfortunately, the stack pointer and the MSR are also clobbered,
790 * so they are saved in the PACA which allows us to restore
791 * our original state after RTAS returns.
794 std r6,PACASAVEDMSR(r13)
796 /* Setup our real return addr */
797 LOAD_REG_ADDR(r4,.rtas_return_loc)
798 clrldi r4,r4,2 /* convert to realmode address */
802 ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI
806 rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG)
807 ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI
809 sync /* disable interrupts so SRR0/1 */
810 mtmsrd r0 /* don't get trashed */
812 LOAD_REG_ADDR(r4, rtas)
813 ld r5,RTASENTRY(r4) /* get the rtas->entry value */
814 ld r4,RTASBASE(r4) /* get the rtas->base value */
819 b . /* prevent speculative execution */
821 _STATIC(rtas_return_loc)
822 /* relocation is off at this point */
824 clrldi r4,r4,2 /* convert to realmode address */
828 ld r3,(1f-0b)(r3) /* get &.rtas_restore_regs */
836 ld r1,PACAR1(r4) /* Restore our SP */
837 ld r4,PACASAVEDMSR(r4) /* Restore our MSR */
842 b . /* prevent speculative execution */
845 1: .llong .rtas_restore_regs
847 _STATIC(rtas_restore_regs)
848 /* relocation is on at this point */
849 REST_GPR(2, r1) /* Restore the TOC */
850 REST_GPR(13, r1) /* Restore paca */
851 REST_8GPRS(14, r1) /* Restore the non-volatiles */
852 REST_10GPRS(22, r1) /* ditto */
867 addi r1,r1,RTAS_FRAME_SIZE /* Unstack our frame */
868 ld r0,16(r1) /* get return address */
871 blr /* return to caller */
873 #endif /* CONFIG_PPC_RTAS */
878 stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */
880 /* Because PROM is running in 32b mode, it clobbers the high order half
881 * of all registers that it saves. We therefore save those registers
882 * PROM might touch to the stack. (r0, r3-r13 are caller saved)
893 /* Get the PROM entrypoint */
896 /* Switch MSR to 32 bits mode
898 #ifdef CONFIG_PPC_BOOK3E
899 rlwinm r11,r11,0,1,31
901 #else /* CONFIG_PPC_BOOK3E */
904 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
907 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
910 #endif /* CONFIG_PPC_BOOK3E */
913 /* Enter PROM here... */
916 /* Just make sure that r1 top 32 bits didn't get
921 /* Restore the MSR (back to 64 bits) */
926 /* Restore other registers */
934 addi r1,r1,PROM_FRAME_SIZE
939 #ifdef CONFIG_FUNCTION_TRACER
940 #ifdef CONFIG_DYNAMIC_FTRACE
945 _GLOBAL(ftrace_caller)
946 /* Taken from output of objdump from lib64/glibc */
952 subi r3, r3, MCOUNT_INSN_SIZE
957 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
958 .globl ftrace_graph_call
961 _GLOBAL(ftrace_graph_stub)
973 /* Taken from output of objdump from lib64/glibc */
980 subi r3, r3, MCOUNT_INSN_SIZE
981 LOAD_REG_ADDR(r5,ftrace_trace_function)
989 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
990 b ftrace_graph_caller
998 #endif /* CONFIG_DYNAMIC_FTRACE */
1000 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1001 _GLOBAL(ftrace_graph_caller)
1002 /* load r4 with local address */
1004 subi r4, r4, MCOUNT_INSN_SIZE
1006 /* get the parent address */
1010 bl .prepare_ftrace_return
1018 _GLOBAL(return_to_handler)
1019 /* need to save return values */
1026 bl .ftrace_return_to_handler
1029 /* return value has real return address */
1037 /* Jump back to real return address */
1040 _GLOBAL(mod_return_to_handler)
1041 /* need to save return values */
1051 * We are in a module using the module's TOC.
1052 * Switch to our TOC to run inside the core kernel.
1056 bl .ftrace_return_to_handler
1059 /* return value has real return address */
1068 /* Jump back to real return address */
1070 #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
1071 #endif /* CONFIG_FUNCTION_TRACER */