2 * This file contains the 64-bit "server" PowerPC variant
3 * of the low level exception handling including exception
4 * vectors, exception return, part of the slb and stab
5 * handling and other fixed offset specific things.
7 * This file is meant to be #included from head_64.S due to
8 * position dependent assembly.
10 * Most of this originates from head_64.S and thus has the same
15 #include <asm/hw_irq.h>
16 #include <asm/exception-64s.h>
17 #include <asm/ptrace.h>
18 #include <asm/cpuidle.h>
19 #include <asm/head-64.h>
22 * There are a few constraints to be concerned with.
23 * - Real mode exceptions code/data must be located at their physical location.
24 * - Virtual mode exceptions must be mapped at their 0xc000... location.
25 * - Fixed location code must not call directly beyond the __end_interrupts
26 * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence
28 * - LOAD_HANDLER targets must be within first 64K of physical 0 /
30 * - Conditional branch targets must be within +/-32K of caller.
32 * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and
33 * therefore don't have to run in physically located code or rfid to
34 * virtual mode kernel code. However on relocatable kernels they do have
35 * to branch to KERNELBASE offset because the rest of the kernel (outside
36 * the exception vectors) may be located elsewhere.
38 * Virtual exceptions correspond with physical, except their entry points
39 * are offset by 0xc000000000000000 and also tend to get an added 0x4000
40 * offset applied. Virtual exceptions are enabled with the Alternate
41 * Interrupt Location (AIL) bit set in the LPCR. However this does not
42 * guarantee they will be delivered virtually. Some conditions (see the ISA)
43 * cause exceptions to be delivered in real mode.
45 * It's impossible to receive interrupts below 0x300 via AIL.
47 * KVM: None of the virtual exceptions are from the guest. Anything that
48 * escalated to HV=1 from HV=0 is delivered via real mode handlers.
51 * We layout physical memory as follows:
52 * 0x0000 - 0x00ff : Secondary processor spin code
53 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors
54 * 0x1900 - 0x3fff : Real mode trampolines
55 * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors
56 * 0x5900 - 0x6fff : Relon mode trampolines
57 * 0x7000 - 0x7fff : FWNMI data area
58 * 0x8000 - .... : Common interrupt handlers, remaining early
59 * setup code, rest of kernel.
61 * We could reclaim 0x4000-0x42ff for real mode trampolines if the space
62 * is necessary. Until then it's more consistent to explicitly put VIRT_NONE
65 OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900)
66 OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000)
67 OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900)
68 OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000)
69 #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
71 * Data area reserved for FWNMI option.
72 * This address (0x7000) is fixed by the RPA.
73 * pseries and powernv need to keep the whole page from
74 * 0x7000 to 0x8000 free for use by the firmware
76 ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000)
77 OPEN_TEXT_SECTION(0x8000)
79 OPEN_TEXT_SECTION(0x7000)
82 USE_FIXED_SECTION(real_vectors)
85 * This is the start of the interrupt handlers for pSeries
86 * This code runs with relocation off.
87 * Code from here to __end_interrupts gets copied down to real
88 * address 0x100 when we are running a relocatable kernel.
89 * Therefore any relative branches in this section must only
90 * branch to labels in this section.
92 .globl __start_interrupts
95 /* No virt vectors corresponding with 0x0..0x100 */
96 EXC_VIRT_NONE(0x4000, 0x100)
99 #ifdef CONFIG_PPC_P7_NAP
101 * If running native on arch 2.06 or later, check if we are waking up
102 * from nap/sleep/winkle, and branch to idle handler. The idle wakeup
103 * handler initially runs in real mode, but we branch to the 0xc000...
104 * address so we can turn on relocation with mtmsr.
106 #define IDLETEST(n) \
107 BEGIN_FTR_SECTION ; \
108 mfspr r10,SPRN_SRR1 ; \
109 rlwinm. r10,r10,47-31,30,31 ; \
112 BRANCH_TO_C000(r10, system_reset_idle_common) ; \
114 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
116 #define IDLETEST NOTEST
119 EXC_REAL_BEGIN(system_reset, 0x100, 0x100)
122 * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is
123 * being used, so a nested NMI exception would corrupt it.
125 EXCEPTION_PROLOG_PSERIES_NORI(PACA_EXNMI, system_reset_common, EXC_STD,
128 EXC_REAL_END(system_reset, 0x100, 0x100)
129 EXC_VIRT_NONE(0x4100, 0x100)
131 #ifdef CONFIG_PPC_P7_NAP
132 EXC_COMMON_BEGIN(system_reset_idle_common)
134 b pnv_powersave_wakeup
137 EXC_COMMON_BEGIN(system_reset_common)
139 * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able
140 * to recover, but nested NMI will notice in_nmi and not recover
141 * because of the use of the NMI stack. in_nmi reentrancy is tested in
142 * system_reset_exception.
144 lhz r10,PACA_IN_NMI(r13)
146 sth r10,PACA_IN_NMI(r13)
151 ld r1,PACA_NMI_EMERG_SP(r13)
152 subi r1,r1,INT_FRAME_SIZE
153 EXCEPTION_COMMON_NORET_STACK(PACA_EXNMI, 0x100,
154 system_reset, system_reset_exception,
155 ADD_NVGPRS;ADD_RECONCILE)
158 * The stack is no longer in use, decrement in_nmi.
160 lhz r10,PACA_IN_NMI(r13)
162 sth r10,PACA_IN_NMI(r13)
166 #ifdef CONFIG_PPC_PSERIES
168 * Vectors for the FWNMI option. Share common code.
170 TRAMP_REAL_BEGIN(system_reset_fwnmi)
171 SET_SCRATCH0(r13) /* save r13 */
172 /* See comment at system_reset exception */
173 EXCEPTION_PROLOG_PSERIES_NORI(PACA_EXNMI, system_reset_common,
174 EXC_STD, NOTEST, 0x100)
175 #endif /* CONFIG_PPC_PSERIES */
178 EXC_REAL_BEGIN(machine_check, 0x200, 0x100)
179 /* This is moved out of line as it can be patched by FW, but
180 * some code path might still want to branch into the original
183 SET_SCRATCH0(r13) /* save r13 */
184 EXCEPTION_PROLOG_0(PACA_EXMC)
186 b machine_check_powernv_early
188 b machine_check_pSeries_0
189 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
190 EXC_REAL_END(machine_check, 0x200, 0x100)
191 EXC_VIRT_NONE(0x4200, 0x100)
192 TRAMP_REAL_BEGIN(machine_check_powernv_early)
194 EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200)
199 * Original R9 to R13 is saved on PACA_EXMC
201 * Switch to mc_emergency stack and handle re-entrancy (we limit
202 * the nested MCE upto level 4 to avoid stack overflow).
203 * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1
205 * We use paca->in_mce to check whether this is the first entry or
206 * nested machine check. We increment paca->in_mce to track nested
209 * If this is the first entry then set stack pointer to
210 * paca->mc_emergency_sp, otherwise r1 is already pointing to
211 * stack frame on mc_emergency stack.
213 * NOTE: We are here with MSR_ME=0 (off), which means we risk a
214 * checkstop if we get another machine check exception before we do
215 * rfid with MSR_ME=1.
217 * This interrupt can wake directly from idle. If that is the case,
218 * the machine check is handled then the idle wakeup code is called
219 * to restore state. In that case, the POWER9 DD1 idle PACA workaround
220 * is not applied in the early machine check code, which will cause
223 mr r11,r1 /* Save r1 */
224 lhz r10,PACA_IN_MCE(r13)
225 cmpwi r10,0 /* Are we in nested machine check */
226 bne 0f /* Yes, we are. */
227 /* First machine check entry */
228 ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */
229 0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
230 addi r10,r10,1 /* increment paca->in_mce */
231 sth r10,PACA_IN_MCE(r13)
232 /* Limit nested MCE to level 4 to avoid stack overflow */
234 bgt 2f /* Check if we hit limit of 4 */
235 std r11,GPR1(r1) /* Save r1 on the stack. */
236 std r11,0(r1) /* make stack chain pointer */
237 mfspr r11,SPRN_SRR0 /* Save SRR0 */
239 mfspr r11,SPRN_SRR1 /* Save SRR1 */
241 mfspr r11,SPRN_DAR /* Save DAR */
243 mfspr r11,SPRN_DSISR /* Save DSISR */
245 std r9,_CCR(r1) /* Save CR in stackframe */
246 /* Save r9 through r13 from EXMC save area to stack frame. */
247 EXCEPTION_PROLOG_COMMON_2(PACA_EXMC)
248 mfmsr r11 /* get MSR value */
249 ori r11,r11,MSR_ME /* turn on ME bit */
250 ori r11,r11,MSR_RI /* turn on RI bit */
251 LOAD_HANDLER(r12, machine_check_handle_early)
252 1: mtspr SPRN_SRR0,r12
255 b . /* prevent speculative execution */
257 /* Stack overflow. Stay on emergency stack and panic.
258 * Keep the ME bit off while panic-ing, so that if we hit
259 * another machine check we checkstop.
261 addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */
263 LOAD_HANDLER(r12, unrecover_mce)
265 andc r11,r11,r10 /* Turn off MSR_ME */
267 b . /* prevent speculative execution */
268 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
270 TRAMP_REAL_BEGIN(machine_check_pSeries)
271 .globl machine_check_fwnmi
273 SET_SCRATCH0(r13) /* save r13 */
274 EXCEPTION_PROLOG_0(PACA_EXMC)
275 machine_check_pSeries_0:
276 EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200)
278 * MSR_RI is not enabled, because PACA_EXMC is being used, so a
279 * nested machine check corrupts it. machine_check_common enables
282 EXCEPTION_PROLOG_PSERIES_1_NORI(machine_check_common, EXC_STD)
284 TRAMP_KVM_SKIP(PACA_EXMC, 0x200)
286 EXC_COMMON_BEGIN(machine_check_common)
288 * Machine check is different because we use a different
289 * save area: PACA_EXMC instead of PACA_EXGEN.
292 std r10,PACA_EXMC+EX_DAR(r13)
294 stw r10,PACA_EXMC+EX_DSISR(r13)
295 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
297 RECONCILE_IRQ_STATE(r10, r11)
298 ld r3,PACA_EXMC+EX_DAR(r13)
299 lwz r4,PACA_EXMC+EX_DSISR(r13)
300 /* Enable MSR_RI when finished with PACA_EXMC */
306 addi r3,r1,STACK_FRAME_OVERHEAD
307 bl machine_check_exception
310 #define MACHINE_CHECK_HANDLER_WINDUP \
311 /* Clear MSR_RI before setting SRR0 and SRR1. */\
313 mfmsr r9; /* get MSR value */ \
315 mtmsrd r9,1; /* Clear MSR_RI */ \
316 /* Move original SRR0 and SRR1 into the respective regs */ \
318 mtspr SPRN_SRR1,r9; \
320 mtspr SPRN_SRR0,r3; \
332 /* Decrement paca->in_mce. */ \
333 lhz r12,PACA_IN_MCE(r13); \
335 sth r12,PACA_IN_MCE(r13); \
337 REST_2GPRS(12, r1); \
338 /* restore original r1. */ \
341 #ifdef CONFIG_PPC_P7_NAP
343 * This is an idle wakeup. Low level machine check has already been
344 * done. Queue the event then call the idle code to do the wake up.
346 EXC_COMMON_BEGIN(machine_check_idle_common)
347 bl machine_check_queue_event
350 * We have not used any non-volatile GPRs here, and as a rule
351 * most exception code including machine check does not.
352 * Therefore PACA_NAPSTATELOST does not need to be set. Idle
353 * wakeup will restore volatile registers.
355 * Load the original SRR1 into r3 for pnv_powersave_wakeup_mce.
357 * Then decrement MCE nesting after finishing with the stack.
361 lhz r11,PACA_IN_MCE(r13)
363 sth r11,PACA_IN_MCE(r13)
365 /* Turn off the RI bit because SRR1 is used by idle wakeup code. */
366 /* Recoverability could be improved by reducing the use of SRR1. */
370 b pnv_powersave_wakeup_mce
373 * Handle machine check early in real mode. We come here with
374 * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack.
376 EXC_COMMON_BEGIN(machine_check_handle_early)
377 std r0,GPR0(r1) /* Save r0 */
378 EXCEPTION_PROLOG_COMMON_3(0x200)
380 addi r3,r1,STACK_FRAME_OVERHEAD
381 bl machine_check_early
382 std r3,RESULT(r1) /* Save result */
385 #ifdef CONFIG_PPC_P7_NAP
387 * Check if thread was in power saving mode. We come here when any
388 * of the following is true:
389 * a. thread wasn't in power saving mode
390 * b. thread was in power saving mode with no state loss,
391 * supervisor state loss or hypervisor state loss.
393 * Go back to nap/sleep/winkle mode again if (b) is true.
396 rlwinm. r11,r12,47-31,30,31
397 bne machine_check_idle_common
398 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
402 * Check if we are coming from hypervisor userspace. If yes then we
403 * continue in host kernel in V mode to deliver the MC event.
405 rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */
407 andi. r11,r12,MSR_PR /* See if coming from user. */
408 bne 9f /* continue in V mode if we are. */
411 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
413 * We are coming from kernel context. Check if we are coming from
414 * guest. if yes, then we can continue. We will fall through
415 * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest.
417 lbz r11,HSTATE_IN_GUEST(r13)
418 cmpwi r11,0 /* Check if coming from guest */
419 bne 9f /* continue if we are. */
422 * At this point we are not sure about what context we come from.
423 * Queue up the MCE event and return from the interrupt.
424 * But before that, check if this is an un-recoverable exception.
425 * If yes, then stay on emergency stack and panic.
429 1: mfspr r11,SPRN_SRR0
430 LOAD_HANDLER(r10,unrecover_mce)
434 * We are going down. But there are chances that we might get hit by
435 * another MCE during panic path and we may run into unstable state
436 * with no way out. Hence, turn ME bit off while going down, so that
437 * when another MCE is hit during panic path, system will checkstop
438 * and hypervisor will get restarted cleanly by SP.
441 andc r10,r10,r3 /* Turn off MSR_ME */
447 * Check if we have successfully handled/recovered from error, if not
448 * then stay on emergency stack and panic.
450 ld r3,RESULT(r1) /* Load result */
451 cmpdi r3,0 /* see if we handled MCE successfully */
453 beq 1b /* if !handled then panic */
455 * Return from MC interrupt.
456 * Queue up the MCE event so that we can log it later, while
457 * returning from kernel or opal call.
459 bl machine_check_queue_event
460 MACHINE_CHECK_HANDLER_WINDUP
463 /* Deliver the machine check to host kernel in V mode. */
464 MACHINE_CHECK_HANDLER_WINDUP
465 b machine_check_pSeries
467 EXC_COMMON_BEGIN(unrecover_mce)
468 /* Invoke machine_check_exception to print MCE event and panic. */
469 addi r3,r1,STACK_FRAME_OVERHEAD
470 bl machine_check_exception
472 * We will not reach here. Even if we did, there is no way out. Call
473 * unrecoverable_exception and die.
475 1: addi r3,r1,STACK_FRAME_OVERHEAD
476 bl unrecoverable_exception
480 EXC_REAL(data_access, 0x300, 0x80)
481 EXC_VIRT(data_access, 0x4300, 0x80, 0x300)
482 TRAMP_KVM_SKIP(PACA_EXGEN, 0x300)
484 EXC_COMMON_BEGIN(data_access_common)
486 * Here r13 points to the paca, r9 contains the saved CR,
487 * SRR0 and SRR1 are saved in r11 and r12,
488 * r9 - r13 are saved in paca->exgen.
491 std r10,PACA_EXGEN+EX_DAR(r13)
493 stw r10,PACA_EXGEN+EX_DSISR(r13)
494 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
495 RECONCILE_IRQ_STATE(r10, r11)
497 ld r3,PACA_EXGEN+EX_DAR(r13)
498 lwz r4,PACA_EXGEN+EX_DSISR(r13)
502 BEGIN_MMU_FTR_SECTION
503 b do_hash_page /* Try to handle as hpte fault */
506 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
509 EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80)
511 EXCEPTION_PROLOG_0(PACA_EXSLB)
512 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380)
513 mr r12,r3 /* save r3 */
517 #ifndef CONFIG_RELOCATABLE
521 * We can't just use a direct branch to slb_miss_realmode
522 * because the distance from here to there depends on where
523 * the kernel ends up being put.
525 LOAD_HANDLER(r10, slb_miss_realmode)
529 EXC_REAL_END(data_access_slb, 0x380, 0x80)
531 EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80)
533 EXCEPTION_PROLOG_0(PACA_EXSLB)
534 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380)
535 mr r12,r3 /* save r3 */
539 #ifndef CONFIG_RELOCATABLE
543 * We can't just use a direct branch to slb_miss_realmode
544 * because the distance from here to there depends on where
545 * the kernel ends up being put.
547 LOAD_HANDLER(r10, slb_miss_realmode)
551 EXC_VIRT_END(data_access_slb, 0x4380, 0x80)
552 TRAMP_KVM_SKIP(PACA_EXSLB, 0x380)
555 EXC_REAL(instruction_access, 0x400, 0x80)
556 EXC_VIRT(instruction_access, 0x4400, 0x80, 0x400)
557 TRAMP_KVM(PACA_EXGEN, 0x400)
559 EXC_COMMON_BEGIN(instruction_access_common)
560 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
561 RECONCILE_IRQ_STATE(r10, r11)
568 BEGIN_MMU_FTR_SECTION
569 b do_hash_page /* Try to handle as hpte fault */
572 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
575 EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80)
577 EXCEPTION_PROLOG_0(PACA_EXSLB)
578 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480)
579 mr r12,r3 /* save r3 */
580 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
583 #ifndef CONFIG_RELOCATABLE
586 LOAD_HANDLER(r10, slb_miss_realmode)
590 EXC_REAL_END(instruction_access_slb, 0x480, 0x80)
592 EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80)
594 EXCEPTION_PROLOG_0(PACA_EXSLB)
595 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480)
596 mr r12,r3 /* save r3 */
597 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
600 #ifndef CONFIG_RELOCATABLE
603 LOAD_HANDLER(r10, slb_miss_realmode)
607 EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80)
608 TRAMP_KVM(PACA_EXSLB, 0x480)
611 /* This handler is used by both 0x380 and 0x480 slb miss interrupts */
612 EXC_COMMON_BEGIN(slb_miss_realmode)
614 * r13 points to the PACA, r9 contains the saved CR,
615 * r12 contains the saved r3,
616 * r11 contain the saved SRR1, SRR0 is still ready for return
617 * r3 has the faulting address
618 * r9 - r13 are saved in paca->exslb.
619 * cr6.eq is set for a D-SLB miss, clear for a I-SLB miss
620 * We assume we aren't going to take any exceptions during this
624 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
625 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
628 * Test MSR_RI before calling slb_allocate_realmode, because the
629 * MSR in r11 gets clobbered. However we still want to allocate
630 * SLB in case MSR_RI=0, to minimise the risk of getting stuck in
631 * recursive SLB faults. So use cr5 for this, which is preserved.
633 andi. r11,r11,MSR_RI /* check for unrecoverable exception */
637 #ifdef CONFIG_PPC_STD_MMU_64
638 BEGIN_MMU_FTR_SECTION
639 bl slb_allocate_realmode
640 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX)
643 ld r10,PACA_EXSLB+EX_LR(r13)
644 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
647 beq- 8f /* if bad address, make full stack frame */
649 bne- cr5,2f /* if unrecoverable exception, oops */
651 /* All done -- return from exception. */
656 mtcrf 0x04,r9 /* MSR[RI] indication is in cr5 */
657 mtcrf 0x02,r9 /* I/D indication is in cr6 */
658 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
661 RESTORE_CTR(r9, PACA_EXSLB)
662 RESTORE_PPR_PACA(PACA_EXSLB, r9)
664 ld r9,PACA_EXSLB+EX_R9(r13)
665 ld r10,PACA_EXSLB+EX_R10(r13)
666 ld r11,PACA_EXSLB+EX_R11(r13)
667 ld r12,PACA_EXSLB+EX_R12(r13)
668 ld r13,PACA_EXSLB+EX_R13(r13)
670 b . /* prevent speculative execution */
672 2: std r3,PACA_EXSLB+EX_DAR(r13)
676 LOAD_HANDLER(r10,unrecov_slb)
683 8: std r3,PACA_EXSLB+EX_DAR(r13)
687 LOAD_HANDLER(r10,bad_addr_slb)
694 EXC_COMMON_BEGIN(unrecov_slb)
695 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
696 RECONCILE_IRQ_STATE(r10, r11)
698 1: addi r3,r1,STACK_FRAME_OVERHEAD
699 bl unrecoverable_exception
702 EXC_COMMON_BEGIN(bad_addr_slb)
703 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB)
704 RECONCILE_IRQ_STATE(r10, r11)
705 ld r3, PACA_EXSLB+EX_DAR(r13)
708 li r10, 0x480 /* fix trap number for I-SLB miss */
711 addi r3, r1, STACK_FRAME_OVERHEAD
715 EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100)
716 .globl hardware_interrupt_hv;
717 hardware_interrupt_hv:
719 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
720 EXC_HV, SOFTEN_TEST_HV)
722 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
723 EXC_STD, SOFTEN_TEST_PR)
724 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
725 EXC_REAL_END(hardware_interrupt, 0x500, 0x100)
727 EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100)
728 .globl hardware_interrupt_relon_hv;
729 hardware_interrupt_relon_hv:
731 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_HV, SOFTEN_TEST_HV)
733 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_STD, SOFTEN_TEST_PR)
734 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
735 EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100)
737 TRAMP_KVM(PACA_EXGEN, 0x500)
738 TRAMP_KVM_HV(PACA_EXGEN, 0x500)
739 EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ)
742 EXC_REAL(alignment, 0x600, 0x100)
743 EXC_VIRT(alignment, 0x4600, 0x100, 0x600)
744 TRAMP_KVM(PACA_EXGEN, 0x600)
745 EXC_COMMON_BEGIN(alignment_common)
747 std r10,PACA_EXGEN+EX_DAR(r13)
749 stw r10,PACA_EXGEN+EX_DSISR(r13)
750 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
751 ld r3,PACA_EXGEN+EX_DAR(r13)
752 lwz r4,PACA_EXGEN+EX_DSISR(r13)
756 RECONCILE_IRQ_STATE(r10, r11)
757 addi r3,r1,STACK_FRAME_OVERHEAD
758 bl alignment_exception
762 EXC_REAL(program_check, 0x700, 0x100)
763 EXC_VIRT(program_check, 0x4700, 0x100, 0x700)
764 TRAMP_KVM(PACA_EXGEN, 0x700)
765 EXC_COMMON_BEGIN(program_check_common)
766 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
768 RECONCILE_IRQ_STATE(r10, r11)
769 addi r3,r1,STACK_FRAME_OVERHEAD
770 bl program_check_exception
774 EXC_REAL(fp_unavailable, 0x800, 0x100)
775 EXC_VIRT(fp_unavailable, 0x4800, 0x100, 0x800)
776 TRAMP_KVM(PACA_EXGEN, 0x800)
777 EXC_COMMON_BEGIN(fp_unavailable_common)
778 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
779 bne 1f /* if from user, just load it up */
781 RECONCILE_IRQ_STATE(r10, r11)
782 addi r3,r1,STACK_FRAME_OVERHEAD
783 bl kernel_fp_unavailable_exception
786 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
788 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
789 * transaction), go do TM stuff
791 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
793 END_FTR_SECTION_IFSET(CPU_FTR_TM)
796 b fast_exception_return
797 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
798 2: /* User process was in a transaction */
800 RECONCILE_IRQ_STATE(r10, r11)
801 addi r3,r1,STACK_FRAME_OVERHEAD
807 EXC_REAL_MASKABLE(decrementer, 0x900, 0x80)
808 EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x80, 0x900)
809 TRAMP_KVM(PACA_EXGEN, 0x900)
810 EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt)
813 EXC_REAL_HV(hdecrementer, 0x980, 0x80)
814 EXC_VIRT_HV(hdecrementer, 0x4980, 0x80, 0x980)
815 TRAMP_KVM_HV(PACA_EXGEN, 0x980)
816 EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt)
819 EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0x100)
820 EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x100, 0xa00)
821 TRAMP_KVM(PACA_EXGEN, 0xa00)
822 #ifdef CONFIG_PPC_DOORBELL
823 EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception)
825 EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception)
829 EXC_REAL(trap_0b, 0xb00, 0x100)
830 EXC_VIRT(trap_0b, 0x4b00, 0x100, 0xb00)
831 TRAMP_KVM(PACA_EXGEN, 0xb00)
832 EXC_COMMON(trap_0b_common, 0xb00, unknown_exception)
835 * system call / hypercall (0xc00, 0x4c00)
837 * The system call exception is invoked with "sc 0" and does not alter HV bit.
838 * There is support for kernel code to invoke system calls but there are no
841 * The hypercall is invoked with "sc 1" and sets HV=1.
843 * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to
844 * 0x4c00 virtual mode.
848 * syscall register convention is in Documentation/powerpc/syscall64-abi.txt
850 * For hypercalls, the register convention is as follows:
853 * r3 volatile parameter and return value for status
854 * r4-r10 volatile input and output value
855 * r11 volatile hypercall number and output value
857 * r13-r31 nonvolatile
861 * CR0-1 CR5-7 volatile
863 * Other registers nonvolatile
865 * The intersection of volatile registers that don't contain possible
866 * inputs is: r12, cr0, xer, ctr. We may use these as scratch regs
867 * upon entry without saving.
869 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
871 * There is a little bit of juggling to get syscall and hcall
872 * working well. Save r10 in ctr to be restored in case it is a
875 * Userspace syscalls have already saved the PPR, hcalls must save
876 * it before setting HMT_MEDIUM.
878 #define SYSCALL_KVMTEST \
882 KVMTEST_PR(0xc00); /* uses r10, branch to do_kvm_0xc00_system_call */ \
887 #define SYSCALL_KVMTEST \
893 #define LOAD_SYSCALL_HANDLER(reg) \
894 __LOAD_HANDLER(reg, system_call_common)
896 #define SYSCALL_FASTENDIAN_TEST \
900 END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \
903 * After SYSCALL_KVMTEST, we reach here with PACA in r13, r13 in r9,
906 #define SYSCALL_REAL \
907 mfspr r11,SPRN_SRR0 ; \
908 mfspr r12,SPRN_SRR1 ; \
909 LOAD_SYSCALL_HANDLER(r10) ; \
910 mtspr SPRN_SRR0,r10 ; \
911 ld r10,PACAKMSR(r13) ; \
912 mtspr SPRN_SRR1,r10 ; \
914 b . ; /* prevent speculative execution */
916 #define SYSCALL_FASTENDIAN \
917 /* Fast LE/BE switch system call */ \
918 1: mfspr r12,SPRN_SRR1 ; \
919 xori r12,r12,MSR_LE ; \
920 mtspr SPRN_SRR1,r12 ; \
922 rfid ; /* return to userspace */ \
923 b . ; /* prevent speculative execution */
925 #if defined(CONFIG_RELOCATABLE)
927 * We can't branch directly so we do it via the CTR which
928 * is volatile across system calls.
930 #define SYSCALL_VIRT \
931 LOAD_SYSCALL_HANDLER(r10) ; \
933 mfspr r11,SPRN_SRR0 ; \
934 mfspr r12,SPRN_SRR1 ; \
939 /* We can branch directly */
940 #define SYSCALL_VIRT \
941 mfspr r11,SPRN_SRR0 ; \
942 mfspr r12,SPRN_SRR1 ; \
944 mtmsrd r10,1 ; /* Set RI (EE=0) */ \
945 b system_call_common ;
948 EXC_REAL_BEGIN(system_call, 0xc00, 0x100)
949 SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */
950 SYSCALL_FASTENDIAN_TEST
953 EXC_REAL_END(system_call, 0xc00, 0x100)
955 EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100)
956 SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */
957 SYSCALL_FASTENDIAN_TEST
960 EXC_VIRT_END(system_call, 0x4c00, 0x100)
962 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
964 * This is a hcall, so register convention is as above, with these
970 TRAMP_KVM_BEGIN(do_kvm_0xc00)
972 * Save the PPR (on systems that support it) before changing to
973 * HMT_MEDIUM. That allows the KVM code to save that value into the
974 * guest state (it is the guest's PPR value).
976 OPT_GET_SPR(r0, SPRN_PPR, CPU_FTR_HAS_PPR)
978 OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r0, CPU_FTR_HAS_PPR)
981 std r9,PACA_EXGEN+EX_R9(r13)
983 std r10,PACA_EXGEN+EX_R10(r13)
984 KVM_HANDLER(PACA_EXGEN, EXC_STD, 0xc00)
988 EXC_REAL(single_step, 0xd00, 0x100)
989 EXC_VIRT(single_step, 0x4d00, 0x100, 0xd00)
990 TRAMP_KVM(PACA_EXGEN, 0xd00)
991 EXC_COMMON(single_step_common, 0xd00, single_step_exception)
993 EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0x20)
994 EXC_VIRT_OOL_HV(h_data_storage, 0x4e00, 0x20, 0xe00)
995 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00)
996 EXC_COMMON_BEGIN(h_data_storage_common)
998 std r10,PACA_EXGEN+EX_DAR(r13)
999 mfspr r10,SPRN_HDSISR
1000 stw r10,PACA_EXGEN+EX_DSISR(r13)
1001 EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN)
1003 RECONCILE_IRQ_STATE(r10, r11)
1004 addi r3,r1,STACK_FRAME_OVERHEAD
1005 bl unknown_exception
1009 EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0x20)
1010 EXC_VIRT_OOL_HV(h_instr_storage, 0x4e20, 0x20, 0xe20)
1011 TRAMP_KVM_HV(PACA_EXGEN, 0xe20)
1012 EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception)
1015 EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0x20)
1016 EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x20, 0xe40)
1017 TRAMP_KVM_HV(PACA_EXGEN, 0xe40)
1018 EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt)
1022 * hmi_exception trampoline is a special case. It jumps to hmi_exception_early
1023 * first, and then eventaully from there to the trampoline to get into virtual
1026 __EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0x20, hmi_exception_early)
1027 __TRAMP_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60)
1028 EXC_VIRT_NONE(0x4e60, 0x20)
1029 TRAMP_KVM_HV(PACA_EXGEN, 0xe60)
1030 TRAMP_REAL_BEGIN(hmi_exception_early)
1031 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60)
1032 mr r10,r1 /* Save r1 */
1033 ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */
1034 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
1035 mfspr r11,SPRN_HSRR0 /* Save HSRR0 */
1036 mfspr r12,SPRN_HSRR1 /* Save HSRR1 */
1037 EXCEPTION_PROLOG_COMMON_1()
1038 EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN)
1039 EXCEPTION_PROLOG_COMMON_3(0xe60)
1040 addi r3,r1,STACK_FRAME_OVERHEAD
1041 BRANCH_LINK_TO_FAR(hmi_exception_realmode) /* Function call ABI */
1042 /* Windup the stack. */
1043 /* Move original HSRR0 and HSRR1 into the respective regs */
1061 /* restore original r1. */
1065 * Go to virtual mode and pull the HMI event information from
1068 .globl hmi_exception_after_realmode
1069 hmi_exception_after_realmode:
1071 EXCEPTION_PROLOG_0(PACA_EXGEN)
1072 b tramp_real_hmi_exception
1074 EXC_COMMON_ASYNC(hmi_exception_common, 0xe60, handle_hmi_exception)
1077 EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0x20)
1078 EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x20, 0xe80)
1079 TRAMP_KVM_HV(PACA_EXGEN, 0xe80)
1080 #ifdef CONFIG_PPC_DOORBELL
1081 EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception)
1083 EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception)
1087 EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0x20)
1088 EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x20, 0xea0)
1089 TRAMP_KVM_HV(PACA_EXGEN, 0xea0)
1090 EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ)
1093 EXC_REAL_NONE(0xec0, 0x20)
1094 EXC_VIRT_NONE(0x4ec0, 0x20)
1095 EXC_REAL_NONE(0xee0, 0x20)
1096 EXC_VIRT_NONE(0x4ee0, 0x20)
1099 EXC_REAL_OOL(performance_monitor, 0xf00, 0x20)
1100 EXC_VIRT_OOL(performance_monitor, 0x4f00, 0x20, 0xf00)
1101 TRAMP_KVM(PACA_EXGEN, 0xf00)
1102 EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception)
1105 EXC_REAL_OOL(altivec_unavailable, 0xf20, 0x20)
1106 EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x20, 0xf20)
1107 TRAMP_KVM(PACA_EXGEN, 0xf20)
1108 EXC_COMMON_BEGIN(altivec_unavailable_common)
1109 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
1110 #ifdef CONFIG_ALTIVEC
1113 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1114 BEGIN_FTR_SECTION_NESTED(69)
1115 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1116 * transaction), go do TM stuff
1118 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1120 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1123 b fast_exception_return
1124 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1125 2: /* User process was in a transaction */
1127 RECONCILE_IRQ_STATE(r10, r11)
1128 addi r3,r1,STACK_FRAME_OVERHEAD
1129 bl altivec_unavailable_tm
1133 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1136 RECONCILE_IRQ_STATE(r10, r11)
1137 addi r3,r1,STACK_FRAME_OVERHEAD
1138 bl altivec_unavailable_exception
1142 EXC_REAL_OOL(vsx_unavailable, 0xf40, 0x20)
1143 EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x20, 0xf40)
1144 TRAMP_KVM(PACA_EXGEN, 0xf40)
1145 EXC_COMMON_BEGIN(vsx_unavailable_common)
1146 EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN)
1150 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1151 BEGIN_FTR_SECTION_NESTED(69)
1152 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1153 * transaction), go do TM stuff
1155 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1157 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1160 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1161 2: /* User process was in a transaction */
1163 RECONCILE_IRQ_STATE(r10, r11)
1164 addi r3,r1,STACK_FRAME_OVERHEAD
1165 bl vsx_unavailable_tm
1169 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1172 RECONCILE_IRQ_STATE(r10, r11)
1173 addi r3,r1,STACK_FRAME_OVERHEAD
1174 bl vsx_unavailable_exception
1178 EXC_REAL_OOL(facility_unavailable, 0xf60, 0x20)
1179 EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x20, 0xf60)
1180 TRAMP_KVM(PACA_EXGEN, 0xf60)
1181 EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception)
1184 EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0x20)
1185 EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x20, 0xf80)
1186 TRAMP_KVM_HV(PACA_EXGEN, 0xf80)
1187 EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception)
1190 EXC_REAL_NONE(0xfa0, 0x20)
1191 EXC_VIRT_NONE(0x4fa0, 0x20)
1192 EXC_REAL_NONE(0xfc0, 0x20)
1193 EXC_VIRT_NONE(0x4fc0, 0x20)
1194 EXC_REAL_NONE(0xfe0, 0x20)
1195 EXC_VIRT_NONE(0x4fe0, 0x20)
1197 EXC_REAL_NONE(0x1000, 0x100)
1198 EXC_VIRT_NONE(0x5000, 0x100)
1199 EXC_REAL_NONE(0x1100, 0x100)
1200 EXC_VIRT_NONE(0x5100, 0x100)
1202 #ifdef CONFIG_CBE_RAS
1203 EXC_REAL_HV(cbe_system_error, 0x1200, 0x100)
1204 EXC_VIRT_NONE(0x5200, 0x100)
1205 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200)
1206 EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception)
1207 #else /* CONFIG_CBE_RAS */
1208 EXC_REAL_NONE(0x1200, 0x100)
1209 EXC_VIRT_NONE(0x5200, 0x100)
1213 EXC_REAL(instruction_breakpoint, 0x1300, 0x100)
1214 EXC_VIRT(instruction_breakpoint, 0x5300, 0x100, 0x1300)
1215 TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300)
1216 EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception)
1218 EXC_REAL_NONE(0x1400, 0x100)
1219 EXC_VIRT_NONE(0x5400, 0x100)
1221 EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100)
1222 mtspr SPRN_SPRG_HSCRATCH0,r13
1223 EXCEPTION_PROLOG_0(PACA_EXGEN)
1224 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500)
1226 #ifdef CONFIG_PPC_DENORMALISATION
1227 mfspr r10,SPRN_HSRR1
1228 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
1229 andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */
1230 addi r11,r11,-4 /* HSRR0 is next instruction */
1235 EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV)
1236 EXC_REAL_END(denorm_exception_hv, 0x1500, 0x100)
1238 #ifdef CONFIG_PPC_DENORMALISATION
1239 EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100)
1240 b exc_real_0x1500_denorm_exception_hv
1241 EXC_VIRT_END(denorm_exception, 0x5500, 0x100)
1243 EXC_VIRT_NONE(0x5500, 0x100)
1246 TRAMP_KVM_SKIP(PACA_EXGEN, 0x1500)
1248 #ifdef CONFIG_PPC_DENORMALISATION
1249 TRAMP_REAL_BEGIN(denorm_assist)
1252 * To denormalise we need to move a copy of the register to itself.
1253 * For POWER6 do that here for all FP regs.
1256 ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1)
1257 xori r10,r10,(MSR_FE0|MSR_FE1)
1261 #define FMR2(n) fmr (n), (n) ; fmr n+1, n+1
1262 #define FMR4(n) FMR2(n) ; FMR2(n+2)
1263 #define FMR8(n) FMR4(n) ; FMR4(n+4)
1264 #define FMR16(n) FMR8(n) ; FMR8(n+8)
1265 #define FMR32(n) FMR16(n) ; FMR16(n+16)
1270 * To denormalise we need to move a copy of the register to itself.
1271 * For POWER7 do that here for the first 32 VSX registers only.
1274 oris r10,r10,MSR_VSX@h
1278 #define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1)
1279 #define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2)
1280 #define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4)
1281 #define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8)
1282 #define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16)
1285 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
1289 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1291 * To denormalise we need to move a copy of the register to itself.
1292 * For POWER8 we need to do that for all 64 VSX registers
1296 mtspr SPRN_HSRR0,r11
1298 ld r9,PACA_EXGEN+EX_R9(r13)
1299 RESTORE_PPR_PACA(PACA_EXGEN, r10)
1301 ld r10,PACA_EXGEN+EX_CFAR(r13)
1303 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1304 ld r10,PACA_EXGEN+EX_R10(r13)
1305 ld r11,PACA_EXGEN+EX_R11(r13)
1306 ld r12,PACA_EXGEN+EX_R12(r13)
1307 ld r13,PACA_EXGEN+EX_R13(r13)
1312 EXC_COMMON_HV(denorm_common, 0x1500, unknown_exception)
1315 #ifdef CONFIG_CBE_RAS
1316 EXC_REAL_HV(cbe_maintenance, 0x1600, 0x100)
1317 EXC_VIRT_NONE(0x5600, 0x100)
1318 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600)
1319 EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception)
1320 #else /* CONFIG_CBE_RAS */
1321 EXC_REAL_NONE(0x1600, 0x100)
1322 EXC_VIRT_NONE(0x5600, 0x100)
1326 EXC_REAL(altivec_assist, 0x1700, 0x100)
1327 EXC_VIRT(altivec_assist, 0x5700, 0x100, 0x1700)
1328 TRAMP_KVM(PACA_EXGEN, 0x1700)
1329 #ifdef CONFIG_ALTIVEC
1330 EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception)
1332 EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception)
1336 #ifdef CONFIG_CBE_RAS
1337 EXC_REAL_HV(cbe_thermal, 0x1800, 0x100)
1338 EXC_VIRT_NONE(0x5800, 0x100)
1339 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800)
1340 EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception)
1341 #else /* CONFIG_CBE_RAS */
1342 EXC_REAL_NONE(0x1800, 0x100)
1343 EXC_VIRT_NONE(0x5800, 0x100)
1348 * An interrupt came in while soft-disabled. We set paca->irq_happened, then:
1349 * - If it was a decrementer interrupt, we bump the dec to max and and return.
1350 * - If it was a doorbell we return immediately since doorbells are edge
1351 * triggered and won't automatically refire.
1352 * - If it was a HMI we return immediately since we handled it in realmode
1353 * and it won't refire.
1354 * - else we hard disable and return.
1355 * This is called with r10 containing the value to OR to the paca field.
1357 #define MASKED_INTERRUPT(_H) \
1358 masked_##_H##interrupt: \
1359 std r11,PACA_EXGEN+EX_R11(r13); \
1360 lbz r11,PACAIRQHAPPENED(r13); \
1362 stb r11,PACAIRQHAPPENED(r13); \
1363 cmpwi r10,PACA_IRQ_DEC; \
1366 ori r10,r10,0xffff; \
1367 mtspr SPRN_DEC,r10; \
1369 1: cmpwi r10,PACA_IRQ_DBELL; \
1371 cmpwi r10,PACA_IRQ_HMI; \
1373 mfspr r10,SPRN_##_H##SRR1; \
1374 rldicl r10,r10,48,1; /* clear MSR_EE */ \
1375 rotldi r10,r10,16; \
1376 mtspr SPRN_##_H##SRR1,r10; \
1378 ld r9,PACA_EXGEN+EX_R9(r13); \
1379 ld r10,PACA_EXGEN+EX_R10(r13); \
1380 ld r11,PACA_EXGEN+EX_R11(r13); \
1381 GET_SCRATCH0(r13); \
1386 * Real mode exceptions actually use this too, but alternate
1387 * instruction code patches (which end up in the common .text area)
1388 * cannot reach these if they are put there.
1390 USE_FIXED_SECTION(virt_trampolines)
1394 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1395 TRAMP_REAL_BEGIN(kvmppc_skip_interrupt)
1397 * Here all GPRs are unchanged from when the interrupt happened
1398 * except for r13, which is saved in SPRG_SCRATCH0.
1400 mfspr r13, SPRN_SRR0
1402 mtspr SPRN_SRR0, r13
1407 TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt)
1409 * Here all GPRs are unchanged from when the interrupt happened
1410 * except for r13, which is saved in SPRG_SCRATCH0.
1412 mfspr r13, SPRN_HSRR0
1414 mtspr SPRN_HSRR0, r13
1421 * Ensure that any handlers that get invoked from the exception prologs
1422 * above are below the first 64KB (0x10000) of the kernel image because
1423 * the prologs assemble the addresses of these handlers using the
1424 * LOAD_HANDLER macro, which uses an ori instruction.
1427 /*** Common interrupt handlers ***/
1431 * Relocation-on interrupts: A subset of the interrupts can be delivered
1432 * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering
1433 * it. Addresses are the same as the original interrupt addresses, but
1434 * offset by 0xc000000000004000.
1435 * It's impossible to receive interrupts below 0x300 via this mechanism.
1436 * KVM: None of these traps are from the guest ; anything that escalated
1437 * to HV=1 from HV=0 is delivered via real mode handlers.
1441 * This uses the standard macro, since the original 0x300 vector
1442 * only has extra guff for STAB-based processors -- which never
1446 EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline)
1447 b __ppc64_runlatch_on
1449 USE_FIXED_SECTION(virt_trampolines)
1451 * The __end_interrupts marker must be past the out-of-line (OOL)
1452 * handlers, so that they are copied to real address 0x100 when running
1453 * a relocatable kernel. This ensures they can be reached from the short
1454 * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch
1455 * directly, without using LOAD_HANDLER().
1458 .globl __end_interrupts
1460 DEFINE_FIXED_SYMBOL(__end_interrupts)
1462 #ifdef CONFIG_PPC_970_NAP
1463 EXC_COMMON_BEGIN(power4_fixup_nap)
1465 std r9,TI_LOCAL_FLAGS(r11)
1466 ld r10,_LINK(r1) /* make idle task do the */
1467 std r10,_NIP(r1) /* equivalent of a blr */
1471 CLOSE_FIXED_SECTION(real_vectors);
1472 CLOSE_FIXED_SECTION(real_trampolines);
1473 CLOSE_FIXED_SECTION(virt_vectors);
1474 CLOSE_FIXED_SECTION(virt_trampolines);
1481 .balign IFETCH_ALIGN_BYTES
1483 #ifdef CONFIG_PPC_STD_MMU_64
1484 andis. r0,r4,0xa410 /* weird error? */
1485 bne- handle_page_fault /* if not, try to insert a HPTE */
1486 andis. r0,r4,DSISR_DABRMATCH@h
1487 bne- handle_dabr_fault
1488 CURRENT_THREAD_INFO(r11, r1)
1489 lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */
1490 andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */
1491 bne 77f /* then don't call hash_page now */
1494 * r3 contains the faulting address
1496 * r5 contains the trap number
1499 * at return r3 = 0 for success, 1 for page fault, negative for error
1503 bl __hash_page /* build HPTE if possible */
1504 cmpdi r3,0 /* see if __hash_page succeeded */
1507 beq fast_exc_return_irq /* Return from exception on success */
1511 #endif /* CONFIG_PPC_STD_MMU_64 */
1513 /* Here we have a page fault that hash_page can't handle. */
1517 addi r3,r1,STACK_FRAME_OVERHEAD
1523 addi r3,r1,STACK_FRAME_OVERHEAD
1528 /* We have a data breakpoint exception - handle it */
1533 addi r3,r1,STACK_FRAME_OVERHEAD
1535 12: b ret_from_except_lite
1538 #ifdef CONFIG_PPC_STD_MMU_64
1539 /* We have a page fault that hash_page could handle but HV refused
1544 addi r3,r1,STACK_FRAME_OVERHEAD
1551 * We come here as a result of a DSI at a point where we don't want
1552 * to call hash_page, such as when we are accessing memory (possibly
1553 * user memory) inside a PMU interrupt that occurred while interrupts
1554 * were soft-disabled. We want to invoke the exception handler for
1555 * the access, or panic if there isn't a handler.
1559 addi r3,r1,STACK_FRAME_OVERHEAD
1565 * Here we have detected that the kernel stack pointer is bad.
1566 * R9 contains the saved CR, r13 points to the paca,
1567 * r10 contains the (bad) kernel stack pointer,
1568 * r11 and r12 contain the saved SRR0 and SRR1.
1569 * We switch to using an emergency stack, save the registers there,
1570 * and call kernel_bad_stack(), which panics.
1573 ld r1,PACAEMERGSP(r13)
1574 subi r1,r1,64+INT_FRAME_SIZE
1580 mfspr r12,SPRN_DSISR
1606 std r10,ORIG_GPR3(r1)
1607 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1610 lhz r12,PACA_TRAP_SAVE(r13)
1612 addi r11,r1,INT_FRAME_SIZE
1617 ld r11,exception_marker@toc(r2)
1619 std r11,STACK_FRAME_OVERHEAD-16(r1)
1620 1: addi r3,r1,STACK_FRAME_OVERHEAD
1625 * When doorbell is triggered from system reset wakeup, the message is
1626 * not cleared, so it would fire again when EE is enabled.
1628 * When coming from local_irq_enable, there may be the same problem if
1629 * we were hard disabled.
1631 * Execute msgclr to clear pending exceptions before handling it.
1633 h_doorbell_common_msgclr:
1634 LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36))
1638 doorbell_super_common_msgclr:
1639 LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36))
1641 b doorbell_super_common
1644 * Called from arch_local_irq_enable when an interrupt needs
1645 * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate
1646 * which kind of interrupt. MSR:EE is already off. We generate a
1647 * stackframe like if a real interrupt had happened.
1649 * Note: While MSR:EE is off, we need to make sure that _MSR
1650 * in the generated frame has EE set to 1 or the exception
1651 * handler will not properly re-enable them.
1653 * Note that we don't specify LR as the NIP (return address) for
1654 * the interrupt because that would unbalance the return branch
1657 _GLOBAL(__replay_interrupt)
1658 /* We are going to jump to the exception common code which
1659 * will retrieve various register values from the PACA which
1660 * we don't give a damn about, so we don't bother storing them.
1663 LOAD_REG_ADDR(r11, .L__replay_interrupt_return)
1667 beq decrementer_common
1669 beq hardware_interrupt_common
1672 beq h_doorbell_common_msgclr
1674 beq h_virt_irq_common
1676 beq hmi_exception_common
1679 beq doorbell_super_common_msgclr
1680 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
1681 .L__replay_interrupt_return: