2 * Kernel execution entry point code.
4 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
5 * Initial PowerPC version.
6 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
8 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
9 * Low-level exception handers, MMU support, and rewrite.
10 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
11 * PowerPC 8xx modifications.
12 * Copyright (c) 1998-1999 TiVo, Inc.
13 * PowerPC 403GCX modifications.
14 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
15 * PowerPC 403GCX/405GP modifications.
16 * Copyright 2000 MontaVista Software Inc.
17 * PPC405 modifications
18 * PowerPC 403GCX/405GP modifications.
19 * Author: MontaVista Software, Inc.
20 * frank_rowand@mvista.com or source@mvista.com
21 * debbie_chu@mvista.com
22 * Copyright 2002-2004 MontaVista Software, Inc.
23 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
24 * Copyright 2004 Freescale Semiconductor, Inc
25 * PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
27 * This program is free software; you can redistribute it and/or modify it
28 * under the terms of the GNU General Public License as published by the
29 * Free Software Foundation; either version 2 of the License, or (at your
30 * option) any later version.
33 #include <linux/init.h>
34 #include <linux/threads.h>
35 #include <asm/processor.h>
38 #include <asm/pgtable.h>
39 #include <asm/cputable.h>
40 #include <asm/thread_info.h>
41 #include <asm/ppc_asm.h>
42 #include <asm/asm-offsets.h>
43 #include <asm/cache.h>
44 #include "head_booke.h"
46 /* As with the other PowerPC ports, it is expected that when code
47 * execution begins here, the following registers contain valid, yet
48 * optional, information:
50 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
51 * r4 - Starting address of the init RAM disk
52 * r5 - Ending address of the init RAM disk
53 * r6 - Start of kernel command line string (e.g. "mem=128")
54 * r7 - End of kernel command line string
61 * Reserve a word at a fixed location to store the address
66 * Save parameters we are passed
73 li r25,0 /* phys kernel start (low) */
74 li r24,0 /* CPU number */
75 li r23,0 /* phys kernel start (high) */
77 /* We try to not make any assumptions about how the boot loader
78 * setup or used the TLBs. We invalidate all mappings from the
79 * boot loader and load a single entry in TLB1[0] to map the
80 * first 64M of kernel memory. Any boot info passed from the
81 * bootloader needs to live in this first 64M.
83 * Requirement on bootloader:
84 * - The page we're executing in needs to reside in TLB1 and
85 * have IPROT=1. If not an invalidate broadcast could
86 * evict the entry we're currently executing in.
88 * r3 = Index of TLB1 were executing in
89 * r4 = Current MSR[IS]
90 * r5 = Index of TLB1 temp mapping
92 * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
98 #define ENTRY_MAPPING_BOOT_SETUP
99 #include "fsl_booke_entry_mapping.S"
100 #undef ENTRY_MAPPING_BOOT_SETUP
102 /* Establish the interrupt vector offsets */
103 SET_IVOR(0, CriticalInput);
104 SET_IVOR(1, MachineCheck);
105 SET_IVOR(2, DataStorage);
106 SET_IVOR(3, InstructionStorage);
107 SET_IVOR(4, ExternalInput);
108 SET_IVOR(5, Alignment);
109 SET_IVOR(6, Program);
110 SET_IVOR(7, FloatingPointUnavailable);
111 SET_IVOR(8, SystemCall);
112 SET_IVOR(9, AuxillaryProcessorUnavailable);
113 SET_IVOR(10, Decrementer);
114 SET_IVOR(11, FixedIntervalTimer);
115 SET_IVOR(12, WatchdogTimer);
116 SET_IVOR(13, DataTLBError);
117 SET_IVOR(14, InstructionTLBError);
118 SET_IVOR(15, DebugCrit);
120 /* Establish the interrupt vector base */
121 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
124 /* Setup the defaults for TLB entries */
125 li r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
127 oris r2,r2,MAS4_TLBSELD(1)@h
134 oris r2,r2,HID0_DOZE@h
138 #if !defined(CONFIG_BDI_SWITCH)
140 * The Abatron BDI JTAG debugger does not tolerate others
141 * mucking with the debug registers.
146 /* clear any residual debug events */
152 /* Check to see if we're the second processor, and jump
153 * to the secondary_start code if so
155 lis r24, boot_cpuid@h
156 ori r24, r24, boot_cpuid@l
160 bne __secondary_start
164 * This is where the main kernel code starts.
169 ori r2,r2,init_task@l
171 /* ptr to current thread */
172 addi r4,r2,THREAD /* init task's THREAD */
173 mtspr SPRN_SPRG_THREAD,r4
176 lis r1,init_thread_union@h
177 ori r1,r1,init_thread_union@l
179 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
181 rlwinm r22,r1,0,0,31-THREAD_SHIFT /* current thread_info */
186 #ifdef CONFIG_RELOCATABLE
187 lis r3,kernstart_addr@ha
188 la r3,kernstart_addr@l(r3)
189 #ifdef CONFIG_PHYS_64BIT
198 * Decide what sort of machine this is and initialize the MMU.
208 /* Setup PTE pointers for the Abatron bdiGDB */
209 lis r6, swapper_pg_dir@h
210 ori r6, r6, swapper_pg_dir@l
211 lis r5, abatron_pteptrs@h
212 ori r5, r5, abatron_pteptrs@l
214 ori r4, r4, KERNELBASE@l
215 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
219 lis r4,start_kernel@h
220 ori r4,r4,start_kernel@l
222 ori r3,r3,MSR_KERNEL@l
225 rfi /* change context and jump to start_kernel */
227 /* Macros to hide the PTE size differences
229 * FIND_PTE -- walks the page tables given EA & pgdir pointer
231 * r11 -- PGDIR pointer
233 * label 2: is the bailout case
235 * if we find the pte (fall through):
236 * r11 is low pte word
237 * r12 is pointer to the pte
239 #ifdef CONFIG_PTE_64BIT
241 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
242 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
243 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
244 beq 2f; /* Bail if no table */ \
245 rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
246 lwz r11, 4(r12); /* Get pte entry */
249 rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \
250 lwz r11, 0(r11); /* Get L1 entry */ \
251 rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \
252 beq 2f; /* Bail if no table */ \
253 rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \
254 lwz r11, 0(r12); /* Get Linux PTE */
258 * Interrupt vector entry code
260 * The Book E MMUs are always on so we don't need to handle
261 * interrupts in real mode as with previous PPC processors. In
262 * this case we handle interrupts in the kernel virtual address
265 * Interrupt vectors are dynamically placed relative to the
266 * interrupt prefix as determined by the address of interrupt_base.
267 * The interrupt vectors offsets are programmed using the labels
268 * for each interrupt vector entry.
270 * Interrupt vectors must be aligned on a 16 byte boundary.
271 * We align on a 32 byte cache line boundary for good measure.
275 /* Critical Input Interrupt */
276 CRITICAL_EXCEPTION(0x0100, CriticalInput, unknown_exception)
278 /* Machine Check Interrupt */
280 /* no RFMCI, MCSRRs on E200 */
281 CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
283 MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
286 /* Data Storage Interrupt */
287 START_EXCEPTION(DataStorage)
288 NORMAL_EXCEPTION_PROLOG
289 mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
291 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
292 andis. r10,r5,(ESR_ILK|ESR_DLK)@h
294 EXC_XFER_EE_LITE(0x0300, handle_page_fault)
296 addi r3,r1,STACK_FRAME_OVERHEAD
297 EXC_XFER_EE_LITE(0x0300, CacheLockingException)
299 /* Instruction Storage Interrupt */
300 INSTRUCTION_STORAGE_EXCEPTION
302 /* External Input Interrupt */
303 EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE)
305 /* Alignment Interrupt */
308 /* Program Interrupt */
311 /* Floating Point Unavailable Interrupt */
312 #ifdef CONFIG_PPC_FPU
313 FP_UNAVAILABLE_EXCEPTION
316 /* E200 treats 'normal' floating point instructions as FP Unavail exception */
317 EXCEPTION(0x0800, FloatingPointUnavailable, program_check_exception, EXC_XFER_EE)
319 EXCEPTION(0x0800, FloatingPointUnavailable, unknown_exception, EXC_XFER_EE)
323 /* System Call Interrupt */
324 START_EXCEPTION(SystemCall)
325 NORMAL_EXCEPTION_PROLOG
326 EXC_XFER_EE_LITE(0x0c00, DoSyscall)
328 /* Auxillary Processor Unavailable Interrupt */
329 EXCEPTION(0x2900, AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE)
331 /* Decrementer Interrupt */
332 DECREMENTER_EXCEPTION
334 /* Fixed Internal Timer Interrupt */
335 /* TODO: Add FIT support */
336 EXCEPTION(0x3100, FixedIntervalTimer, unknown_exception, EXC_XFER_EE)
338 /* Watchdog Timer Interrupt */
339 #ifdef CONFIG_BOOKE_WDT
340 CRITICAL_EXCEPTION(0x3200, WatchdogTimer, WatchdogException)
342 CRITICAL_EXCEPTION(0x3200, WatchdogTimer, unknown_exception)
345 /* Data TLB Error Interrupt */
346 START_EXCEPTION(DataTLBError)
347 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
348 mtspr SPRN_SPRG_WSCRATCH1, r11
349 mtspr SPRN_SPRG_WSCRATCH2, r12
350 mtspr SPRN_SPRG_WSCRATCH3, r13
352 mtspr SPRN_SPRG_WSCRATCH4, r11
353 mfspr r10, SPRN_DEAR /* Get faulting address */
355 /* If we are faulting a kernel address, we have to use the
356 * kernel page tables.
358 lis r11, PAGE_OFFSET@h
361 lis r11, swapper_pg_dir@h
362 ori r11, r11, swapper_pg_dir@l
364 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
365 rlwinm r12,r12,0,16,1
370 /* Get the PGD for the current thread */
372 mfspr r11,SPRN_SPRG_THREAD
376 /* Mask of required permission bits. Note that while we
377 * do copy ESR:ST to _PAGE_RW position as trying to write
378 * to an RO page is pretty common, we don't do it with
379 * _PAGE_DIRTY. We could do it, but it's a fairly rare
380 * event so I'd rather take the overhead when it happens
381 * rather than adding an instruction here. We should measure
382 * whether the whole thing is worth it in the first place
383 * as we could avoid loading SPRN_ESR completely in the first
386 * TODO: Is it worth doing that mfspr & rlwimi in the first
387 * place or can we save a couple of instructions here ?
390 #ifdef CONFIG_PTE_64BIT
392 oris r13,r13,_PAGE_ACCESSED@h
394 li r13,_PAGE_PRESENT|_PAGE_ACCESSED
396 rlwimi r13,r12,11,29,29
399 andc. r13,r13,r11 /* Check permission */
401 #ifdef CONFIG_PTE_64BIT
403 subf r10,r11,r12 /* create false data dep */
404 lwzx r13,r11,r10 /* Get upper pte bits */
406 lwz r13,0(r12) /* Get upper pte bits */
410 bne 2f /* Bail if permission/valid mismach */
412 /* Jump to common tlb load */
415 /* The bailout. Restore registers to pre-exception conditions
416 * and call the heavyweights to help us out.
418 mfspr r11, SPRN_SPRG_RSCRATCH4
420 mfspr r13, SPRN_SPRG_RSCRATCH3
421 mfspr r12, SPRN_SPRG_RSCRATCH2
422 mfspr r11, SPRN_SPRG_RSCRATCH1
423 mfspr r10, SPRN_SPRG_RSCRATCH0
426 /* Instruction TLB Error Interrupt */
428 * Nearly the same as above, except we get our
429 * information from different registers and bailout
430 * to a different point.
432 START_EXCEPTION(InstructionTLBError)
433 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
434 mtspr SPRN_SPRG_WSCRATCH1, r11
435 mtspr SPRN_SPRG_WSCRATCH2, r12
436 mtspr SPRN_SPRG_WSCRATCH3, r13
438 mtspr SPRN_SPRG_WSCRATCH4, r11
439 mfspr r10, SPRN_SRR0 /* Get faulting address */
441 /* If we are faulting a kernel address, we have to use the
442 * kernel page tables.
444 lis r11, PAGE_OFFSET@h
447 lis r11, swapper_pg_dir@h
448 ori r11, r11, swapper_pg_dir@l
450 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
451 rlwinm r12,r12,0,16,1
454 /* Make up the required permissions for kernel code */
455 #ifdef CONFIG_PTE_64BIT
456 li r13,_PAGE_PRESENT | _PAGE_BAP_SX
457 oris r13,r13,_PAGE_ACCESSED@h
459 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
463 /* Get the PGD for the current thread */
465 mfspr r11,SPRN_SPRG_THREAD
468 /* Make up the required permissions for user code */
469 #ifdef CONFIG_PTE_64BIT
470 li r13,_PAGE_PRESENT | _PAGE_BAP_UX
471 oris r13,r13,_PAGE_ACCESSED@h
473 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
478 andc. r13,r13,r11 /* Check permission */
480 #ifdef CONFIG_PTE_64BIT
482 subf r10,r11,r12 /* create false data dep */
483 lwzx r13,r11,r10 /* Get upper pte bits */
485 lwz r13,0(r12) /* Get upper pte bits */
489 bne 2f /* Bail if permission mismach */
491 /* Jump to common TLB load point */
495 /* The bailout. Restore registers to pre-exception conditions
496 * and call the heavyweights to help us out.
498 mfspr r11, SPRN_SPRG_RSCRATCH4
500 mfspr r13, SPRN_SPRG_RSCRATCH3
501 mfspr r12, SPRN_SPRG_RSCRATCH2
502 mfspr r11, SPRN_SPRG_RSCRATCH1
503 mfspr r10, SPRN_SPRG_RSCRATCH0
507 /* SPE Unavailable */
508 START_EXCEPTION(SPEUnavailable)
509 NORMAL_EXCEPTION_PROLOG
511 addi r3,r1,STACK_FRAME_OVERHEAD
512 EXC_XFER_EE_LITE(0x2010, KernelSPE)
514 EXCEPTION(0x2020, SPEUnavailable, unknown_exception, EXC_XFER_EE)
515 #endif /* CONFIG_SPE */
517 /* SPE Floating Point Data */
519 EXCEPTION(0x2030, SPEFloatingPointData, SPEFloatingPointException, EXC_XFER_EE);
521 /* SPE Floating Point Round */
522 EXCEPTION(0x2050, SPEFloatingPointRound, SPEFloatingPointRoundException, EXC_XFER_EE)
524 EXCEPTION(0x2040, SPEFloatingPointData, unknown_exception, EXC_XFER_EE)
525 EXCEPTION(0x2050, SPEFloatingPointRound, unknown_exception, EXC_XFER_EE)
526 #endif /* CONFIG_SPE */
528 /* Performance Monitor */
529 EXCEPTION(0x2060, PerformanceMonitor, performance_monitor_exception, EXC_XFER_STD)
531 EXCEPTION(0x2070, Doorbell, doorbell_exception, EXC_XFER_STD)
533 CRITICAL_EXCEPTION(0x2080, CriticalDoorbell, unknown_exception)
535 /* Debug Interrupt */
536 DEBUG_DEBUG_EXCEPTION
544 * Both the instruction and data TLB miss get to this
545 * point to load the TLB.
546 * r10 - available to use
547 * r11 - TLB (info from Linux PTE)
548 * r12 - available to use
549 * r13 - upper bits of PTE (if PTE_64BIT) or available to use
550 * CR5 - results of addr >= PAGE_OFFSET
551 * MAS0, MAS1 - loaded with proper value when we get here
552 * MAS2, MAS3 - will need additional info from Linux PTE
553 * Upon exit, we reload everything and RFI.
557 * We set execute, because we don't have the granularity to
558 * properly set this at the page level (Linux problem).
559 * Many of these bits are software only. Bits we don't set
560 * here we (properly should) assume have the appropriate value.
564 #ifdef CONFIG_PTE_64BIT
565 rlwimi r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */
567 rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
571 #ifdef CONFIG_PTE_64BIT
572 rlwinm r12, r11, 32-2, 26, 31 /* Move in perm bits */
573 andi. r10, r11, _PAGE_DIRTY
575 li r10, MAS3_SW | MAS3_UW
577 1: rlwimi r12, r13, 20, 0, 11 /* grab RPN[32:43] */
578 rlwimi r12, r11, 20, 12, 19 /* grab RPN[44:51] */
580 BEGIN_MMU_FTR_SECTION
581 srwi r10, r13, 12 /* grab RPN[12:31] */
583 END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
585 li r10, (_PAGE_EXEC | _PAGE_PRESENT)
586 rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */
588 andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */
592 rlwimi r11, r12, 0, 20, 31 /* Extract RPN from PTE and merge with perms */
596 /* Round robin TLB1 entries assignment */
599 /* Extract TLB1CFG(NENTRY) */
600 mfspr r11, SPRN_TLB1CFG
601 andi. r11, r11, 0xfff
603 /* Extract MAS0(NV) */
604 andi. r13, r12, 0xfff
609 /* check if we need to wrap */
612 /* wrap back to first free tlbcam entry */
613 lis r13, tlbcam_index@ha
614 lwz r13, tlbcam_index@l(r13)
615 rlwimi r12, r13, 0, 20, 31
618 #endif /* CONFIG_E200 */
622 /* Done...restore registers and get out of here. */
623 mfspr r11, SPRN_SPRG_RSCRATCH4
625 mfspr r13, SPRN_SPRG_RSCRATCH3
626 mfspr r12, SPRN_SPRG_RSCRATCH2
627 mfspr r11, SPRN_SPRG_RSCRATCH1
628 mfspr r10, SPRN_SPRG_RSCRATCH0
629 rfi /* Force context change */
632 /* Note that the SPE support is closely modeled after the AltiVec
633 * support. Changes to one are likely to be applicable to the
637 * Disable SPE for the task which had SPE previously,
638 * and save its SPE registers in its thread_struct.
639 * Enables SPE for use in the kernel on return.
640 * On SMP we know the SPE units are free, since we give it up every
645 mtmsr r5 /* enable use of SPE now */
648 * For SMP, we don't do lazy SPE switching because it just gets too
649 * horrendously complex, especially when a task switches from one CPU
650 * to another. Instead we call giveup_spe in switch_to.
653 lis r3,last_task_used_spe@ha
654 lwz r4,last_task_used_spe@l(r3)
657 addi r4,r4,THREAD /* want THREAD of last_task_used_spe */
658 SAVE_32EVRS(0,r10,r4)
659 evxor evr10, evr10, evr10 /* clear out evr10 */
660 evmwumiaa evr10, evr10, evr10 /* evr10 <- ACC = 0 * 0 + ACC */
662 evstddx evr10, r4, r5 /* save off accumulator */
664 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
666 andc r4,r4,r10 /* disable SPE for previous task */
667 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
669 #endif /* !CONFIG_SMP */
670 /* enable use of SPE after return */
672 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
675 stw r4,THREAD_USED_SPE(r5)
678 REST_32EVRS(0,r10,r5)
681 stw r4,last_task_used_spe@l(r3)
682 #endif /* !CONFIG_SMP */
683 /* restore registers and return */
684 2: REST_4GPRS(3, r11)
699 * SPE unavailable trap from kernel - print a message, but let
700 * the task use SPE in the kernel until it returns to user mode.
705 stw r3,_MSR(r1) /* enable use of SPE after return */
709 mr r4,r2 /* current */
715 87: .string "SPE used in kernel (task=%p, pc=%x) \n"
719 #endif /* CONFIG_SPE */
725 /* Adjust or setup IVORs for e200 */
726 _GLOBAL(__setup_e200_ivors)
729 li r3,SPEUnavailable@l
731 li r3,SPEFloatingPointData@l
733 li r3,SPEFloatingPointRound@l
738 /* Adjust or setup IVORs for e500v1/v2 */
739 _GLOBAL(__setup_e500_ivors)
742 li r3,SPEUnavailable@l
744 li r3,SPEFloatingPointData@l
746 li r3,SPEFloatingPointRound@l
748 li r3,PerformanceMonitor@l
753 /* Adjust or setup IVORs for e500mc */
754 _GLOBAL(__setup_e500mc_ivors)
757 li r3,PerformanceMonitor@l
761 li r3,CriticalDoorbell@l
767 * extern void giveup_altivec(struct task_struct *prev)
769 * The e500 core does not have an AltiVec unit.
771 _GLOBAL(giveup_altivec)
776 * extern void giveup_spe(struct task_struct *prev)
782 mtmsr r5 /* enable use of SPE now */
785 beqlr- /* if no previous owner, done */
786 addi r3,r3,THREAD /* want THREAD of task */
789 SAVE_32EVRS(0, r4, r3)
790 evxor evr6, evr6, evr6 /* clear out evr6 */
791 evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */
793 evstddx evr6, r4, r3 /* save off accumulator */
794 mfspr r6,SPRN_SPEFSCR
795 stw r6,THREAD_SPEFSCR(r3) /* save spefscr register value */
797 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
799 andc r4,r4,r3 /* disable SPE for previous task */
800 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
804 lis r4,last_task_used_spe@ha
805 stw r5,last_task_used_spe@l(r4)
806 #endif /* !CONFIG_SMP */
808 #endif /* CONFIG_SPE */
811 * extern void giveup_fpu(struct task_struct *prev)
813 * Not all FSL Book-E cores have an FPU
815 #ifndef CONFIG_PPC_FPU
821 * extern void abort(void)
823 * At present, this routine just applies a system reset.
827 mtspr SPRN_DBCR0,r13 /* disable all debug events */
830 ori r13,r13,MSR_DE@l /* Enable Debug Events */
834 lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
840 #ifdef CONFIG_BDI_SWITCH
841 /* Context switch the PTE pointer for the Abatron BDI2000.
842 * The PGDIR is the second parameter.
844 lis r5, abatron_pteptrs@h
845 ori r5, r5, abatron_pteptrs@l
849 isync /* Force context change */
852 _GLOBAL(flush_dcache_L1)
855 rlwinm r5,r3,9,3 /* Extract cache block size */
856 twlgti r5,1 /* Only 32 and 64 byte cache blocks
857 * are currently defined.
860 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
861 * log2(number of ways)
863 slw r5,r4,r5 /* r5 = cache block size */
865 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
866 mulli r7,r7,13 /* An 8-way cache will require 13
871 /* save off HID0 and set DCFA */
873 ori r9,r8,HID0_DCFA@l
880 1: lwz r3,0(r4) /* Load... */
888 1: dcbf 0,r4 /* ...and flush. */
899 /* When we get here, r24 needs to hold the CPU # */
900 .globl __secondary_start
902 lis r3,__secondary_hold_acknowledge@h
903 ori r3,r3,__secondary_hold_acknowledge@l
910 lis r3,tlbcam_index@ha
911 lwz r3,tlbcam_index@l(r3)
913 li r26,0 /* r26 safe? */
915 /* Load each CAM entry */
921 /* get current_thread_info and current */
922 lis r1,secondary_ti@ha
923 lwz r1,secondary_ti@l(r1)
927 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
931 /* ptr to current thread */
932 addi r4,r2,THREAD /* address of our thread_struct */
933 mtspr SPRN_SPRG_THREAD,r4
935 /* Setup the defaults for TLB entries */
936 li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
939 /* Jump to start_secondary */
941 ori r4,r4,MSR_KERNEL@l
942 lis r3,start_secondary@h
943 ori r3,r3,start_secondary@l
950 .globl __secondary_hold_acknowledge
951 __secondary_hold_acknowledge:
956 * We put a few things here that have to be page-aligned. This stuff
957 * goes at the beginning of the data segment, which is page-aligned.
963 .globl empty_zero_page
966 .globl swapper_pg_dir
968 .space PGD_TABLE_SIZE
971 * Room for two PTE pointers, usually the kernel and current user pointers
972 * to their respective root page table.