2 * This file contains idle entry/exit functions for POWER7,
3 * POWER8 and POWER9 CPUs.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
11 #include <linux/threads.h>
12 #include <asm/processor.h>
14 #include <asm/cputable.h>
15 #include <asm/thread_info.h>
16 #include <asm/ppc_asm.h>
17 #include <asm/asm-offsets.h>
18 #include <asm/ppc-opcode.h>
19 #include <asm/hw_irq.h>
20 #include <asm/kvm_book3s_asm.h>
22 #include <asm/cpuidle.h>
23 #include <asm/book3s/64/mmu-hash.h>
29 * Use unused space in the interrupt stack to save and restore
30 * registers for winkle support.
43 #define PSSCR_EC_ESL_MASK_SHIFTED (PSSCR_EC | PSSCR_ESL) >> 16
48 * Used by threads before entering deep idle states. Saves SPRs
49 * in interrupt stack frame
53 * Note all register i.e per-core, per-subcore or per-thread is saved
54 * here since any thread in the core might wake up first
60 * Note - SDR1 is dropped in Power ISA v3. Hence not restoring
66 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
87 * Used by threads when the lock bit of core_idle_state is set.
88 * Threads will spin in HMT_LOW until the lock bit is cleared.
89 * r14 - pointer to core_idle_state
90 * r15 - used to load contents of core_idle_state
91 * r9 - used as a temporary variable
97 andi. r15,r15,PNV_CORE_IDLE_LOCK_BIT
101 andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
102 bne core_idle_lock_held
106 * Pass requested state in r3:
107 * r3 - PNV_THREAD_NAP/SLEEP/WINKLE in POWER8
108 * - Requested STOP state in POWER9
110 * To check IRQ_HAPPENED in r4
114 * Address to 'rfid' to in r5
116 _GLOBAL(pnv_powersave_common)
117 /* Use r3 to pass state nap/sleep/winkle */
118 /* NAP is a state loss, we create a regs frame on the
119 * stack, fill it up with the state we care about and
120 * stick a pointer to it in PACAR1. We really only
121 * need to save PC, some CR bits and the NV GPRs,
122 * but for now an interrupt frame will do.
126 stdu r1,-INT_FRAME_SIZE(r1)
130 /* Hard disable interrupts */
134 mtmsrd r9,1 /* hard-disable interrupts */
136 /* Check if something happened while soft-disabled */
137 lbz r0,PACAIRQHAPPENED(r13)
138 andi. r0,r0,~PACA_IRQ_HARD_DIS@l
142 addi r1,r1,INT_FRAME_SIZE
144 li r3,0 /* Return 0 (no nap) */
148 1: /* We mark irqs hard disabled as this is the state we'll
149 * be in when returning and we need to tell arch_local_irq_restore()
152 li r0,PACA_IRQ_HARD_DIS
153 stb r0,PACAIRQHAPPENED(r13)
155 /* We haven't lost state ... yet */
157 stb r0,PACA_NAPSTATELOST(r13)
159 /* Continue saving state */
168 * Go to real mode to do the nap, as required by the architecture.
169 * Also, we need to be in real mode before setting hwthread_state,
170 * because as soon as we do that, another thread can switch
171 * the MMU context to the guest.
173 LOAD_REG_IMMEDIATE(r7, MSR_IDLE)
176 mtmsrd r6, 1 /* clear RI before setting SRR0/1 */
181 .globl pnv_enter_arch207_idle_mode
182 pnv_enter_arch207_idle_mode:
183 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
184 /* Tell KVM we're entering idle */
185 li r4,KVM_HWTHREAD_IN_IDLE
186 /******************************************************/
187 /* N O T E W E L L ! ! ! N O T E W E L L */
188 /* The following store to HSTATE_HWTHREAD_STATE(r13) */
189 /* MUST occur in real mode, i.e. with the MMU off, */
190 /* and the MMU must stay off until we clear this flag */
191 /* and test HSTATE_HWTHREAD_REQ(r13) in the system */
192 /* reset interrupt vector in exceptions-64s.S. */
193 /* The reason is that another thread can switch the */
194 /* MMU to a guest context whenever this flag is set */
195 /* to KVM_HWTHREAD_IN_IDLE, and if the MMU was on, */
196 /* that would potentially cause this thread to start */
197 /* executing instructions from guest memory in */
198 /* hypervisor mode, leading to a host crash or data */
199 /* corruption, or worse. */
200 /******************************************************/
201 stb r4,HSTATE_HWTHREAD_STATE(r13)
203 stb r3,PACA_THREAD_IDLE_STATE(r13)
204 cmpwi cr3,r3,PNV_THREAD_SLEEP
206 IDLE_STATE_ENTER_SEQ_NORET(PPC_NAP)
209 /* Sleep or winkle */
210 lbz r7,PACA_THREAD_MASK(r13)
211 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
215 andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
216 bnel core_idle_lock_held
218 andc r15,r15,r7 /* Clear thread bit */
220 andi. r15,r15,PNV_CORE_IDLE_THREAD_BITS
223 * If cr0 = 0, then current thread is the last thread of the core entering
224 * sleep. Last thread needs to execute the hardware bug workaround code if
225 * required by the platform.
226 * Make the workaround call unconditionally here. The below branch call is
227 * patched out when the idle states are discovered if the platform does not
230 .global pnv_fastsleep_workaround_at_entry
231 pnv_fastsleep_workaround_at_entry:
232 beq fastsleep_workaround_at_entry
238 common_enter: /* common code for all the threads entering sleep or winkle */
240 IDLE_STATE_ENTER_SEQ_NORET(PPC_SLEEP)
242 fastsleep_workaround_at_entry:
243 ori r15,r15,PNV_CORE_IDLE_LOCK_BIT
248 /* Fast sleep workaround */
251 bl opal_config_cpu_idle_state
260 bl save_sprs_to_stack
262 IDLE_STATE_ENTER_SEQ_NORET(PPC_WINKLE)
265 * r3 - PSSCR value corresponding to the requested stop state.
268 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
269 /* Tell KVM we're entering idle */
270 li r4,KVM_HWTHREAD_IN_IDLE
271 /* DO THIS IN REAL MODE! See comment above. */
272 stb r4,HSTATE_HWTHREAD_STATE(r13)
275 * Check if we are executing the lite variant with ESL=EC=0
277 andis. r4,r3,PSSCR_EC_ESL_MASK_SHIFTED
278 clrldi r3,r3,60 /* r3 = Bits[60:63] = Requested Level (RL) */
279 bne .Lhandle_esl_ec_set
280 IDLE_STATE_ENTER_SEQ(PPC_STOP)
281 li r3,0 /* Since we didn't lose state, return 0 */
286 * Check if the requested state is a deep idle state.
288 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
289 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
291 bge .Lhandle_deep_stop
292 IDLE_STATE_ENTER_SEQ_NORET(PPC_STOP)
295 * Entering deep idle state.
296 * Clear thread bit in PACA_CORE_IDLE_STATE, save SPRs to
297 * stack and enter stop
299 lbz r7,PACA_THREAD_MASK(r13)
300 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
304 andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
305 bnel core_idle_lock_held
306 andc r15,r15,r7 /* Clear thread bit */
312 bl save_sprs_to_stack
314 IDLE_STATE_ENTER_SEQ_NORET(PPC_STOP)
317 /* Now check if user or arch enabled NAP mode */
318 LOAD_REG_ADDRBASE(r3,powersave_nap)
319 lwz r4,ADDROFF(powersave_nap)(r3)
328 LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
329 b pnv_powersave_common
332 _GLOBAL(power7_sleep)
333 li r3,PNV_THREAD_SLEEP
335 LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
336 b pnv_powersave_common
339 _GLOBAL(power7_winkle)
340 li r3,PNV_THREAD_WINKLE
342 LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
343 b pnv_powersave_common
346 #define CHECK_HMI_INTERRUPT \
347 mfspr r0,SPRN_SRR1; \
348 BEGIN_FTR_SECTION_NESTED(66); \
349 rlwinm r0,r0,45-31,0xf; /* extract wake reason field (P8) */ \
350 FTR_SECTION_ELSE_NESTED(66); \
351 rlwinm r0,r0,45-31,0xe; /* P7 wake reason field is 3 bits */ \
352 ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \
353 cmpwi r0,0xa; /* Hypervisor maintenance ? */ \
355 /* Invoke opal call to handle hmi */ \
356 ld r2,PACATOC(r13); \
358 std r3,ORIG_GPR3(r1); /* Save original r3 */ \
359 li r3,0; /* NULL argument */ \
360 bl hmi_exception_realmode; \
362 ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \
366 * r3 - The PSSCR value corresponding to the stop state.
367 * r4 - The PSSCR mask corrresonding to the stop state.
369 _GLOBAL(power9_idle_stop)
374 LOAD_REG_ADDR(r5,power_enter_stop)
376 b pnv_powersave_common
379 * Called from reset vector. Check whether we have woken up with
380 * hypervisor state loss. If yes, restore hypervisor state and return
381 * back to reset vector.
383 * r13 - Contents of HSPRG0
384 * cr3 - set to gt if waking up with partial/complete hypervisor state loss
386 _GLOBAL(pnv_restore_hyp_resource)
390 * POWER ISA 3. Use PSSCR to determine if we
391 * are waking up from deep idle state
393 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
394 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
398 * 0-3 bits correspond to Power-Saving Level Status
399 * which indicates the idle state we are waking up from
403 bge cr4,pnv_wakeup_tb_loss
405 * Waking up without hypervisor state loss. Return to
410 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
413 * POWER ISA 2.07 or less.
414 * Check if last bit of HSPGR0 is set. This indicates whether we are
415 * waking up from winkle.
420 /* Now that we are sure r13 is corrected, load TOC */
423 mtspr SPRN_HSPRG0,r13
425 lbz r0,PACA_THREAD_IDLE_STATE(r13)
426 cmpwi cr2,r0,PNV_THREAD_NAP
427 bgt cr2,pnv_wakeup_tb_loss /* Either sleep or Winkle */
430 * We fall through here if PACA_THREAD_IDLE_STATE shows we are waking
431 * up from nap. At this stage CR3 shouldn't contains 'gt' since that
432 * indicates we are waking with hypervisor state loss from nap.
436 blr /* Return back to System Reset vector from where
437 pnv_restore_hyp_resource was invoked */
440 * Called if waking up from idle state which can cause either partial or
441 * complete hyp state loss.
442 * In POWER8, called if waking up from fastsleep or winkle
443 * In POWER9, called if waking up from stop state >= pnv_first_deep_stop_state
446 * cr3 - gt if waking up with partial/complete hypervisor state loss
447 * cr4 - gt or eq if waking up from complete hypervisor state loss.
449 _GLOBAL(pnv_wakeup_tb_loss)
452 * Before entering any idle state, the NVGPRs are saved in the stack
453 * and they are restored before switching to the process context. Hence
454 * until they are restored, they are free to be used.
456 * Save SRR1 and LR in NVGPRs as they might be clobbered in
457 * opal_call() (called in CHECK_HMI_INTERRUPT). SRR1 is required
458 * to determine the wakeup reason if we branch to kvm_start_guest. LR
459 * is required to return back to reset vector after hypervisor state
460 * restore is complete.
466 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
468 lbz r7,PACA_THREAD_MASK(r13)
469 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
472 andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
474 * Lock bit is set in one of the 2 cases-
475 * a. In the sleep/winkle enter path, the last thread is executing
476 * fastsleep workaround code.
477 * b. In the wake up path, another thread is executing fastsleep
478 * workaround undo code or resyncing timebase or restoring context
479 * In either case loop until the lock bit is cleared.
481 bnel core_idle_lock_held
487 * cr2 - eq if first thread to wakeup in core
488 * cr3- gt if waking up with partial/complete hypervisor state loss
489 * cr4 - gt or eq if waking up from complete hypervisor state loss.
492 ori r15,r15,PNV_CORE_IDLE_LOCK_BIT
498 lbz r4,PACA_SUBCORE_SIBLING_MASK(r13)
500 cmpwi r4,0 /* Check if first in subcore */
502 or r15,r15,r7 /* Set thread bit */
503 beq first_thread_in_subcore
504 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
506 or r15,r15,r7 /* Set thread bit */
507 beq cr2,first_thread_in_core
509 /* Not first thread in core or subcore to wake up */
512 first_thread_in_subcore:
514 * If waking up from sleep, subcore state is not lost. Hence
515 * skip subcore state restore
517 blt cr4,subcore_state_restored
519 /* Restore per-subcore state */
528 subcore_state_restored:
530 * Check if the thread is also the first thread in the core. If not,
531 * skip to clear_lock.
535 first_thread_in_core:
538 * First thread in the core waking up from any state which can cause
539 * partial or complete hypervisor state loss. It needs to
540 * call the fastsleep workaround code if the platform requires it.
541 * Call it unconditionally here. The below branch instruction will
542 * be patched out if the platform does not have fastsleep or does not
543 * require the workaround. Patching will be performed during the
544 * discovery of idle-states.
546 .global pnv_fastsleep_workaround_at_exit
547 pnv_fastsleep_workaround_at_exit:
548 b fastsleep_workaround_at_exit
552 * Use cr3 which indicates that we are waking up with atleast partial
553 * hypervisor state loss to determine if TIMEBASE RESYNC is needed.
556 /* Time base re-sync */
557 bl opal_resync_timebase;
559 * If waking up from sleep, per core state is not lost, skip to
565 * First thread in the core to wake up and its waking up with
566 * complete hypervisor state loss. Restore per core hypervisor
574 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
582 andi. r15,r15,PNV_CORE_IDLE_THREAD_BITS
588 * Common to all threads.
590 * If waking up from sleep, hypervisor state is not lost. Hence
591 * skip hypervisor state restore.
593 blt cr4,hypervisor_state_restored
595 /* Waking up from winkle */
597 BEGIN_MMU_FTR_SECTION
599 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
600 /* Restore SLB from PACA */
601 ld r8,PACA_SLBSHADOWPTR(r13)
604 li r3, SLBSHADOW_SAVEAREA
608 andis. r7,r5,SLB_ESID_V@h
615 /* Restore per thread state */
626 /* Call cur_cpu_spec->cpu_restore() */
627 LOAD_REG_ADDR(r4, cur_cpu_spec)
629 ld r12,CPU_SPEC_RESTORE(r4)
630 #ifdef PPC64_ELF_ABI_v1
636 hypervisor_state_restored:
640 blr /* Return back to System Reset vector from where
641 pnv_restore_hyp_resource was invoked */
643 fastsleep_workaround_at_exit:
646 bl opal_config_cpu_idle_state
650 * R3 here contains the value that will be returned to the caller
653 _GLOBAL(pnv_wakeup_loss)
657 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
663 addi r1,r1,INT_FRAME_SIZE
670 * R3 here contains the value that will be returned to the caller
673 _GLOBAL(pnv_wakeup_noloss)
674 lbz r0,PACA_NAPSTATELOST(r13)
679 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
684 addi r1,r1,INT_FRAME_SIZE