2 * This file contains miscellaneous low-level functions.
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
9 * Copyright (C) 2002-2003 Eric Biederman <ebiederm@xmission.com>
10 * GameCube/ppc32 port Copyright (C) 2004 Albert Herranz
11 * PPC44x port. Copyright (C) 2011, IBM Corporation
12 * Author: Suzuki Poulose <suzuki@in.ibm.com>
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
21 #include <linux/sys.h>
22 #include <asm/unistd.h>
23 #include <asm/errno.h>
26 #include <asm/cache.h>
27 #include <asm/cputable.h>
29 #include <asm/ppc_asm.h>
30 #include <asm/thread_info.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/processor.h>
33 #include <asm/kexec.h>
35 #include <asm/ptrace.h>
40 * We store the saved ksp_limit in the unused part
41 * of the STACK_FRAME_OVERHEAD
43 _GLOBAL(call_do_softirq)
46 lwz r10,THREAD+KSP_LIMIT(r2)
47 addi r11,r3,THREAD_INFO_GAP
48 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
51 stw r11,THREAD+KSP_LIMIT(r2)
56 stw r10,THREAD+KSP_LIMIT(r2)
63 lwz r10,THREAD+KSP_LIMIT(r2)
64 addi r11,r3,THREAD_INFO_GAP
65 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r4)
68 stw r11,THREAD+KSP_LIMIT(r2)
73 stw r10,THREAD+KSP_LIMIT(r2)
78 * This returns the high 64 bits of the product of two 64-bit numbers.
90 1: beqlr cr1 /* all done if high part of A is 0 */
105 * sub_reloc_offset(x) returns x - reloc_offset().
107 _GLOBAL(sub_reloc_offset)
119 * reloc_got2 runs through the .got2 section adding an offset
124 lis r7,__got2_start@ha
125 addi r7,r7,__got2_start@l
127 addi r8,r8,__got2_end@l
147 * call_setup_cpu - call the setup_cpu function for this cpu
148 * r3 = data offset, r24 = cpu number
150 * Setup function is called with:
152 * r4 = ptr to CPU spec (relocated)
154 _GLOBAL(call_setup_cpu)
155 addis r4,r3,cur_cpu_spec@ha
156 addi r4,r4,cur_cpu_spec@l
159 lwz r5,CPU_SPEC_SETUP(r4)
166 #if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx)
168 /* This gets called by via-pmu.c to switch the PLL selection
169 * on 750fx CPU. This function should really be moved to some
170 * other place (as most of the cpufreq code in via-pmu
172 _GLOBAL(low_choose_750fx_pll)
178 /* If switching to PLL1, disable HID0:BTIC */
189 /* Calc new HID1 value */
190 mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */
191 rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */
192 rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */
196 /* Store new HID1 image */
197 CURRENT_THREAD_INFO(r6, r1)
200 addis r6,r6,nap_save_hid1@ha
201 stw r4,nap_save_hid1@l(r6)
203 /* If switching to PLL0, enable HID0:BTIC */
218 _GLOBAL(low_choose_7447a_dfs)
224 /* Calc new HID1 value */
226 insrwi r4,r3,1,9 /* insert parameter into bit 9 */
236 #endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */
239 * complement mask on the msr then "or" some values on.
240 * _nmask_and_or_msr(nmask, value_to_or)
242 _GLOBAL(_nmask_and_or_msr)
243 mfmsr r0 /* Get current msr */
244 andc r0,r0,r3 /* And off the bits set in r3 (first parm) */
245 or r0,r0,r4 /* Or on the bits in r4 (second parm) */
246 SYNC /* Some chip revs have problems here... */
247 mtmsr r0 /* Update machine state */
254 * Do an IO access in real mode
272 * Do an IO access in real mode
289 #endif /* CONFIG_40x */
293 * Flush instruction cache.
294 * This is a no-op on the 601.
296 _GLOBAL(flush_instruction_cache)
297 #if defined(CONFIG_8xx)
300 mtspr SPRN_IC_CST, r5
301 #elif defined(CONFIG_4xx)
313 #elif CONFIG_FSL_BOOKE
316 ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC
317 /* msync; isync recommended here */
321 END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
323 ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
327 rlwinm r3,r3,16,16,31
329 beqlr /* for 601, do nothing */
330 /* 603/604 processor - use invalidate-all bit in HID0 */
334 #endif /* CONFIG_8xx/4xx */
339 * Write any modified data cache blocks out to memory
340 * and invalidate the corresponding instruction cache blocks.
341 * This is a no-op on the 601.
343 * flush_icache_range(unsigned long start, unsigned long stop)
345 _KPROBE(flush_icache_range)
348 blr /* for 601, do nothing */
349 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
350 li r5,L1_CACHE_BYTES-1
354 srwi. r4,r4,L1_CACHE_SHIFT
359 addi r3,r3,L1_CACHE_BYTES
361 sync /* wait for dcbst's to get to ram */
365 addi r6,r6,L1_CACHE_BYTES
368 /* Flash invalidate on 44x because we are passed kmapped addresses and
369 this doesn't work for userspace pages due to the virtually tagged
373 sync /* additional sync needed on g4 */
377 * Write any modified data cache blocks out to memory.
378 * Does not invalidate the corresponding cache lines (especially for
379 * any corresponding instruction cache).
381 * clean_dcache_range(unsigned long start, unsigned long stop)
383 _GLOBAL(clean_dcache_range)
384 li r5,L1_CACHE_BYTES-1
388 srwi. r4,r4,L1_CACHE_SHIFT
393 addi r3,r3,L1_CACHE_BYTES
395 sync /* wait for dcbst's to get to ram */
399 * Write any modified data cache blocks out to memory and invalidate them.
400 * Does not invalidate the corresponding instruction cache blocks.
402 * flush_dcache_range(unsigned long start, unsigned long stop)
404 _GLOBAL(flush_dcache_range)
405 li r5,L1_CACHE_BYTES-1
409 srwi. r4,r4,L1_CACHE_SHIFT
414 addi r3,r3,L1_CACHE_BYTES
416 sync /* wait for dcbst's to get to ram */
420 * Like above, but invalidate the D-cache. This is used by the 8xx
421 * to invalidate the cache so the PPC core doesn't get stale data
422 * from the CPM (no cache snooping here :-).
424 * invalidate_dcache_range(unsigned long start, unsigned long stop)
426 _GLOBAL(invalidate_dcache_range)
427 li r5,L1_CACHE_BYTES-1
431 srwi. r4,r4,L1_CACHE_SHIFT
436 addi r3,r3,L1_CACHE_BYTES
438 sync /* wait for dcbi's to get to ram */
442 * Flush a particular page from the data cache to RAM.
443 * Note: this is necessary because the instruction cache does *not*
444 * snoop from the data cache.
445 * This is a no-op on the 601 which has a unified cache.
447 * void __flush_dcache_icache(void *page)
449 _GLOBAL(__flush_dcache_icache)
452 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
453 rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */
454 li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */
457 0: dcbst 0,r3 /* Write line to ram */
458 addi r3,r3,L1_CACHE_BYTES
462 /* We don't flush the icache on 44x. Those have a virtual icache
463 * and we don't have access to the virtual address here (it's
464 * not the page vaddr but where it's mapped in user space). The
465 * flushing of the icache on these is handled elsewhere, when
466 * a change in the address space occurs, before returning to
469 BEGIN_MMU_FTR_SECTION
471 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_44x)
472 #endif /* CONFIG_44x */
475 addi r6,r6,L1_CACHE_BYTES
483 * Flush a particular page from the data cache to RAM, identified
484 * by its physical address. We turn off the MMU so we can just use
485 * the physical address (this may be a highmem page without a kernel
488 * void __flush_dcache_icache_phys(unsigned long physaddr)
490 _GLOBAL(__flush_dcache_icache_phys)
492 blr /* for 601, do nothing */
493 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
495 rlwinm r0,r10,0,28,26 /* clear DR */
498 rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */
499 li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */
502 0: dcbst 0,r3 /* Write line to ram */
503 addi r3,r3,L1_CACHE_BYTES
508 addi r6,r6,L1_CACHE_BYTES
511 mtmsr r10 /* restore DR */
514 #endif /* CONFIG_BOOKE */
517 * Clear pages using the dcbz instruction, which doesn't cause any
518 * memory traffic (except to write out any cache lines which get
519 * displaced). This only works on cacheable memory.
521 * void clear_pages(void *page, int order) ;
524 li r0,PAGE_SIZE/L1_CACHE_BYTES
528 addi r3,r3,L1_CACHE_BYTES
533 * Copy a whole page. We use the dcbz instruction on the destination
534 * to reduce memory traffic (it eliminates the unnecessary reads of
535 * the destination into cache). This requires that the destination
538 #define COPY_16_BYTES \
554 #if MAX_COPY_PREFETCH > 1
555 li r0,MAX_COPY_PREFETCH
559 addi r11,r11,L1_CACHE_BYTES
561 #else /* MAX_COPY_PREFETCH == 1 */
563 li r11,L1_CACHE_BYTES+4
564 #endif /* MAX_COPY_PREFETCH */
565 li r0,PAGE_SIZE/L1_CACHE_BYTES - MAX_COPY_PREFETCH
573 #if L1_CACHE_BYTES >= 32
575 #if L1_CACHE_BYTES >= 64
578 #if L1_CACHE_BYTES >= 128
588 crnot 4*cr0+eq,4*cr0+eq
589 li r0,MAX_COPY_PREFETCH
594 * void atomic_clear_mask(atomic_t mask, atomic_t *addr)
595 * void atomic_set_mask(atomic_t mask, atomic_t *addr);
597 _GLOBAL(atomic_clear_mask)
604 _GLOBAL(atomic_set_mask)
613 * Extended precision shifts.
615 * Updated to be valid for shift counts from 0 to 63 inclusive.
618 * R3/R4 has 64 bit value
622 * ashrdi3: arithmetic right shift (sign propagation)
623 * lshrdi3: logical right shift
624 * ashldi3: left shift
628 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
629 addi r7,r5,32 # could be xori, or addi with -32
630 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
631 rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
632 sraw r7,r3,r7 # t2 = MSW >> (count-32)
633 or r4,r4,r6 # LSW |= t1
634 slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
635 sraw r3,r3,r5 # MSW = MSW >> count
636 or r4,r4,r7 # LSW |= t2
641 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
642 addi r7,r5,32 # could be xori, or addi with -32
643 srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
644 slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
645 or r3,r3,r6 # MSW |= t1
646 slw r4,r4,r5 # LSW = LSW << count
647 or r3,r3,r7 # MSW |= t2
652 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
653 addi r7,r5,32 # could be xori, or addi with -32
654 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
655 srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
656 or r4,r4,r6 # LSW |= t1
657 srw r3,r3,r5 # MSW = MSW >> count
658 or r4,r4,r7 # LSW |= t2
662 * 64-bit comparison: __cmpdi2(s64 a, s64 b)
663 * Returns 0 if a < b, 1 if a == b, 2 if a > b.
676 * 64-bit comparison: __ucmpdi2(u64 a, u64 b)
677 * Returns 0 if a < b, 1 if a == b, 2 if a > b.
695 rlwimi r9,r4,24,16,23
696 rlwimi r10,r3,24,16,23
708 _GLOBAL(start_secondary_resume)
710 CURRENT_THREAD_INFO(r1, r1)
711 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
713 stw r3,0(r1) /* Zero the stack frame pointer */
716 #endif /* CONFIG_SMP */
719 * This routine is just here to keep GCC happy - sigh...
726 * Must be relocatable PIC code callable as a C function.
728 .globl relocate_new_kernel
731 /* r4 = reboot_code_buffer */
732 /* r5 = start_address */
734 #ifdef CONFIG_FSL_BOOKE
740 #define ENTRY_MAPPING_KEXEC_SETUP
741 #include "fsl_booke_entry_mapping.S"
742 #undef ENTRY_MAPPING_KEXEC_SETUP
749 #elif defined(CONFIG_44x)
751 /* Save our parameters */
756 #ifdef CONFIG_PPC_47x
757 /* Check for 47x cores */
760 cmplwi cr0,r3,PVR_476@h
762 cmplwi cr0,r3,PVR_476_ISS@h
764 #endif /* CONFIG_PPC_47x */
767 * Code for setting up 1:1 mapping for PPC440x for KEXEC
769 * We cannot switch off the MMU on PPC44x.
771 * 1) Invalidate all the mappings except the one we are running from.
772 * 2) Create a tmp mapping for our code in the other address space(TS) and
773 * jump to it. Invalidate the entry we started in.
774 * 3) Create a 1:1 mapping for 0-2GiB in chunks of 256M in original TS.
775 * 4) Jump to the 1:1 mapping in original TS.
776 * 5) Invalidate the tmp mapping.
778 * - Based on the kexec support code for FSL BookE
783 * Load the PID with kernel PID (0).
784 * Also load our MSR_IS and TID to MMUCR for TLB search.
791 oris r3,r3,PPC44x_MMUCR_STS@h
797 * Invalidate all the TLB entries except the current entry
798 * where we are running from
800 bl 0f /* Find our address */
801 0: mflr r5 /* Make it accessible */
802 tlbsx r23,0,r5 /* Find entry we are in */
803 li r4,0 /* Start at TLB entry 0 */
804 li r3,0 /* Set PAGEID inval value */
805 1: cmpw r23,r4 /* Is this our entry? */
806 beq skip /* If so, skip the inval */
807 tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */
809 addi r4,r4,1 /* Increment */
810 cmpwi r4,64 /* Are we done? */
811 bne 1b /* If not, repeat */
814 /* Create a temp mapping and jump to it */
815 andi. r6, r23, 1 /* Find the index to use */
816 addi r24, r6, 1 /* r24 will contain 1 or 2 */
818 mfmsr r9 /* get the MSR */
819 rlwinm r5, r9, 27, 31, 31 /* Extract the MSR[IS] */
820 xori r7, r5, 1 /* Use the other address space */
822 /* Read the current mapping entries */
823 tlbre r3, r23, PPC44x_TLB_PAGEID
824 tlbre r4, r23, PPC44x_TLB_XLAT
825 tlbre r5, r23, PPC44x_TLB_ATTRIB
827 /* Save our current XLAT entry */
830 /* Extract the TLB PageSize */
831 li r10, 1 /* r10 will hold PageSize */
832 rlwinm r11, r3, 0, 24, 27 /* bits 24-27 */
834 /* XXX: As of now we use 256M, 4K pages */
835 cmpwi r11, PPC44x_TLB_256M
837 rotlwi r10, r10, 28 /* r10 = 256M */
840 cmpwi r11, PPC44x_TLB_4K
842 rotlwi r10, r10, 12 /* r10 = 4K */
845 rotlwi r10, r10, 10 /* r10 = 1K */
849 * Write out the tmp 1:1 mapping for this code in other address space
850 * Fixup EPN = RPN , TS=other address space
852 insrwi r3, r7, 1, 23 /* Bit 23 is TS for PAGEID field */
854 /* Write out the tmp mapping entries */
855 tlbwe r3, r24, PPC44x_TLB_PAGEID
856 tlbwe r4, r24, PPC44x_TLB_XLAT
857 tlbwe r5, r24, PPC44x_TLB_ATTRIB
859 subi r11, r10, 1 /* PageOffset Mask = PageSize - 1 */
860 not r10, r11 /* Mask for PageNum */
862 /* Switch to other address space in MSR */
863 insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */
867 addi r8, r8, (2f-1b) /* Find the target offset */
869 /* Jump to the tmp mapping */
875 /* Invalidate the entry we were executing from */
877 tlbwe r3, r23, PPC44x_TLB_PAGEID
879 /* attribute fields. rwx for SUPERVISOR mode */
881 ori r5, r5, (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G)
883 /* Create 1:1 mapping in 256M pages */
884 xori r7, r7, 1 /* Revert back to Original TS */
886 li r8, 0 /* PageNumber */
887 li r6, 3 /* TLB Index, start at 3 */
890 rotlwi r3, r8, 28 /* Create EPN (bits 0-3) */
891 mr r4, r3 /* RPN = EPN */
892 ori r3, r3, (PPC44x_TLB_VALID | PPC44x_TLB_256M) /* SIZE = 256M, Valid */
893 insrwi r3, r7, 1, 23 /* Set TS from r7 */
895 tlbwe r3, r6, PPC44x_TLB_PAGEID /* PageID field : EPN, V, SIZE */
896 tlbwe r4, r6, PPC44x_TLB_XLAT /* Address translation : RPN */
897 tlbwe r5, r6, PPC44x_TLB_ATTRIB /* Attributes */
899 addi r8, r8, 1 /* Increment PN */
900 addi r6, r6, 1 /* Increment TLB Index */
901 cmpwi r8, 8 /* Are we done ? */
905 /* Jump to the new mapping 1:1 */
907 insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */
911 and r8, r8, r11 /* Get our offset within page */
914 and r5, r25, r10 /* Get our target PageNum */
915 or r8, r8, r5 /* Target jump address */
921 /* Invalidate the tmp entry we used */
923 tlbwe r3, r24, PPC44x_TLB_PAGEID
927 #ifdef CONFIG_PPC_47x
929 /* 1:1 mapping for 47x */
934 * Load the kernel pid (0) to PID and also to MMUCR[TID].
935 * Also set the MSR IS->MMUCR STS
938 mtspr SPRN_PID, r3 /* Set PID */
939 mfmsr r4 /* Get MSR */
940 andi. r4, r4, MSR_IS@l /* TS=1? */
941 beq 1f /* If not, leave STS=0 */
942 oris r3, r3, PPC47x_MMUCR_STS@h /* Set STS=1 */
943 1: mtspr SPRN_MMUCR, r3 /* Put MMUCR */
946 /* Find the entry we are running from */
950 tlbre r24, r23, 0 /* TLB Word 0 */
951 tlbre r25, r23, 1 /* TLB Word 1 */
952 tlbre r26, r23, 2 /* TLB Word 2 */
956 * Invalidates all the tlb entries by writing to 256 RPNs(r4)
957 * of 4k page size in all 4 ways (0-3 in r3).
958 * This would invalidate the entire UTLB including the one we are
959 * running from. However the shadow TLB entries would help us
960 * to continue the execution, until we flush them (rfi/isync).
962 addis r3, 0, 0x8000 /* specify the way */
963 addi r4, 0, 0 /* TLB Word0 = (EPN=0, VALID = 0) */
967 /* Align the loop to speed things up. from head_44x.S */
975 addis r3, r3, 0x2000 /* Increment the way */
979 addis r4, r4, 0x100 /* Increment the EPN */
983 /* Create the entries in the other address space */
985 rlwinm r7, r5, 27, 31, 31 /* Get the TS (Bit 26) from MSR */
986 xori r7, r7, 1 /* r7 = !TS */
988 insrwi r24, r7, 1, 21 /* Change the TS in the saved TLB word 0 */
991 * write out the TLB entries for the tmp mapping
992 * Use way '0' so that we could easily invalidate it later.
994 lis r3, 0x8000 /* Way '0' */
1000 /* Update the msr to the new TS */
1001 insrwi r5, r7, 1, 26
1005 addi r6, r6, (2f-1b)
1012 * Now we are in the tmp address space.
1013 * Create a 1:1 mapping for 0-2GiB in the original TS.
1017 li r4, 0 /* TLB Word 0 */
1018 li r5, 0 /* TLB Word 1 */
1020 ori r6, r6, PPC47x_TLB2_S_RWX /* TLB word 2 */
1022 li r8, 0 /* PageIndex */
1024 xori r7, r7, 1 /* revert back to original TS */
1027 rotlwi r5, r8, 28 /* RPN = PageIndex * 256M */
1028 /* ERPN = 0 as we don't use memory above 2G */
1030 mr r4, r5 /* EPN = RPN */
1031 ori r4, r4, (PPC47x_TLB0_VALID | PPC47x_TLB0_256M)
1032 insrwi r4, r7, 1, 21 /* Insert the TS to Word 0 */
1034 tlbwe r4, r3, 0 /* Write out the entries */
1038 cmpwi r8, 8 /* Have we completed ? */
1041 /* make sure we complete the TLB write up */
1045 * Prepare to jump to the 1:1 mapping.
1046 * 1) Extract page size of the tmp mapping
1047 * DSIZ = TLB_Word0[22:27]
1048 * 2) Calculate the physical address of the address
1051 rlwinm r10, r24, 0, 22, 27
1053 cmpwi r10, PPC47x_TLB0_4K
1055 li r10, 0x1000 /* r10 = 4k */
1059 /* Defaults to 256M */
1064 addi r4, r4, (2f-1b) /* virtual address of 2f */
1066 subi r11, r10, 1 /* offsetmask = Pagesize - 1 */
1067 not r10, r11 /* Pagemask = ~(offsetmask) */
1069 and r5, r25, r10 /* Physical page */
1070 and r6, r4, r11 /* offset within the current page */
1072 or r5, r5, r6 /* Physical address for 2f */
1074 /* Switch the TS in MSR to the original one */
1076 insrwi r8, r7, 1, 26
1083 /* Invalidate the tmp mapping */
1084 lis r3, 0x8000 /* Way '0' */
1086 clrrwi r24, r24, 12 /* Clear the valid bit */
1091 /* Make sure we complete the TLB write and flush the shadow TLB */
1099 /* Restore the parameters */
1109 * Set Machine Status Register to a known status,
1110 * switch the MMU off and jump to 1: in a single step.
1114 ori r8, r8, MSR_RI|MSR_ME
1116 addi r8, r4, 1f - relocate_new_kernel
1123 /* from this point address translation is turned off */
1124 /* and interrupts are disabled */
1126 /* set a new stack at the bottom of our page... */
1127 /* (not really needed now) */
1128 addi r1, r4, KEXEC_CONTROL_PAGE_SIZE - 8 /* for LR Save+Back Chain */
1132 li r6, 0 /* checksum */
1136 0: /* top, read another word for the indirection page */
1140 /* is it a destination page? (r8) */
1141 rlwinm. r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */
1144 rlwinm r8, r0, 0, 0, 19 /* clear kexec flags, page align */
1147 2: /* is it an indirection page? (r3) */
1148 rlwinm. r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */
1151 rlwinm r3, r0, 0, 0, 19 /* clear kexec flags, page align */
1155 2: /* are we done? */
1156 rlwinm. r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */
1160 2: /* is it a source page? (r9) */
1161 rlwinm. r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */
1164 rlwinm r9, r0, 0, 0, 19 /* clear kexec flags, page align */
1166 li r7, PAGE_SIZE / 4
1171 lwzu r0, 4(r9) /* do the copy */
1185 /* To be certain of avoiding problems with self-modifying code
1186 * execute a serializing instruction here.
1191 mfspr r3, SPRN_PIR /* current core we are running on */
1192 mr r4, r5 /* load physical address of chunk called */
1194 /* jump to the entry point, usually the setup routine */
1200 relocate_new_kernel_end:
1202 .globl relocate_new_kernel_size
1203 relocate_new_kernel_size:
1204 .long relocate_new_kernel_end - relocate_new_kernel