2 * This file contains miscellaneous low-level functions.
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
7 * Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com)
8 * PPC64 updates by Dave Engebretsen (engebret@us.ibm.com)
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
17 #include <linux/sys.h>
18 #include <asm/unistd.h>
19 #include <asm/errno.h>
20 #include <asm/processor.h>
22 #include <asm/cache.h>
23 #include <asm/ppc_asm.h>
24 #include <asm/asm-offsets.h>
25 #include <asm/cputable.h>
26 #include <asm/thread_info.h>
27 #include <asm/kexec.h>
28 #include <asm/ptrace.h>
32 _GLOBAL(call_do_softirq)
35 stdu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
43 _GLOBAL(call_handle_irq)
48 stdu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r5)
58 .tc ppc64_caches[TC],ppc64_caches
62 * Write any modified data cache blocks out to memory
63 * and invalidate the corresponding instruction cache blocks.
65 * flush_icache_range(unsigned long start, unsigned long stop)
67 * flush all bytes from start through stop-1 inclusive
70 _KPROBE(flush_icache_range)
73 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
75 * Flush the data cache to memory
77 * Different systems have different cache line sizes
78 * and in some cases i-cache and d-cache line sizes differ from
81 ld r10,PPC64_CACHES@toc(r2)
82 lwz r7,DCACHEL1LINESIZE(r10)/* Get cache line size */
84 andc r6,r3,r5 /* round low to line bdy */
85 subf r8,r6,r4 /* compute length */
86 add r8,r8,r5 /* ensure we get enough */
87 lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of cache line size */
88 srw. r8,r8,r9 /* compute line count */
89 beqlr /* nothing to do? */
96 /* Now invalidate the instruction cache */
98 lwz r7,ICACHEL1LINESIZE(r10) /* Get Icache line size */
100 andc r6,r3,r5 /* round low to line bdy */
101 subf r8,r6,r4 /* compute length */
103 lwz r9,ICACHEL1LOGLINESIZE(r10) /* Get log-2 of Icache line size */
104 srw. r8,r8,r9 /* compute line count */
105 beqlr /* nothing to do? */
114 * Like above, but only do the D-cache.
116 * flush_dcache_range(unsigned long start, unsigned long stop)
118 * flush all bytes from start to stop-1 inclusive
120 _GLOBAL(flush_dcache_range)
123 * Flush the data cache to memory
125 * Different systems have different cache line sizes
127 ld r10,PPC64_CACHES@toc(r2)
128 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
130 andc r6,r3,r5 /* round low to line bdy */
131 subf r8,r6,r4 /* compute length */
132 add r8,r8,r5 /* ensure we get enough */
133 lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */
134 srw. r8,r8,r9 /* compute line count */
135 beqlr /* nothing to do? */
144 * Like above, but works on non-mapped physical addresses.
145 * Use only for non-LPAR setups ! It also assumes real mode
146 * is cacheable. Used for flushing out the DART before using
147 * it as uncacheable memory
149 * flush_dcache_phys_range(unsigned long start, unsigned long stop)
151 * flush all bytes from start to stop-1 inclusive
153 _GLOBAL(flush_dcache_phys_range)
154 ld r10,PPC64_CACHES@toc(r2)
155 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
157 andc r6,r3,r5 /* round low to line bdy */
158 subf r8,r6,r4 /* compute length */
159 add r8,r8,r5 /* ensure we get enough */
160 lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */
161 srw. r8,r8,r9 /* compute line count */
162 beqlr /* nothing to do? */
163 mfmsr r5 /* Disable MMU Data Relocation */
176 mtmsr r5 /* Re-enable MMU Data Relocation */
181 _GLOBAL(flush_inval_dcache_range)
182 ld r10,PPC64_CACHES@toc(r2)
183 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
185 andc r6,r3,r5 /* round low to line bdy */
186 subf r8,r6,r4 /* compute length */
187 add r8,r8,r5 /* ensure we get enough */
188 lwz r9,DCACHEL1LOGLINESIZE(r10)/* Get log-2 of dcache line size */
189 srw. r8,r8,r9 /* compute line count */
190 beqlr /* nothing to do? */
203 * Flush a particular page from the data cache to RAM.
204 * Note: this is necessary because the instruction cache does *not*
205 * snoop from the data cache.
207 * void __flush_dcache_icache(void *page)
209 _GLOBAL(__flush_dcache_icache)
211 * Flush the data cache to memory
213 * Different systems have different cache line sizes
216 /* Flush the dcache */
217 ld r7,PPC64_CACHES@toc(r2)
218 clrrdi r3,r3,PAGE_SHIFT /* Page align */
219 lwz r4,DCACHEL1LINESPERPAGE(r7) /* Get # dcache lines per page */
220 lwz r5,DCACHEL1LINESIZE(r7) /* Get dcache line size */
228 /* Now invalidate the icache */
230 lwz r4,ICACHEL1LINESPERPAGE(r7) /* Get # icache lines per page */
231 lwz r5,ICACHEL1LINESIZE(r7) /* Get icache line size */
241 rlwinm r7,r3,8,0xffffffff
243 rlwinm r9,r8,8,0xffffffff
244 rlwimi r7,r3,24,16,23
246 rlwimi r9,r8,24,16,23
251 #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE)
284 * Do an IO access in real mode
315 * Do an IO access in real mode
344 #endif /* defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) */
346 #ifdef CONFIG_PPC_PASEMI
348 _GLOBAL(real_205_readb)
363 _GLOBAL(real_205_writeb)
378 #endif /* CONFIG_PPC_PASEMI */
381 #if defined(CONFIG_CPU_FREQ_PMAC64) || defined(CONFIG_CPU_FREQ_MAPLE)
383 * SCOM access functions for 970 (FX only for now)
385 * unsigned long scom970_read(unsigned int address);
386 * void scom970_write(unsigned int address, unsigned long value);
388 * The address passed in is the 24 bits register address. This code
389 * is 970 specific and will not check the status bits, so you should
390 * know what you are doing.
392 _GLOBAL(scom970_read)
399 /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
400 * (including parity). On current CPUs they must be 0'd,
401 * and finally or in RW bit
406 /* do the actual scom read */
415 /* XXX: fixup result on some buggy 970's (ouch ! we lost a bit, bah
416 * that's the best we can do). Not implemented yet as we don't use
417 * the scom on any of the bogus CPUs yet, but may have to be done
421 /* restore interrupts */
426 _GLOBAL(scom970_write)
433 /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
434 * (including parity). On current CPUs they must be 0'd.
440 mtspr SPRN_SCOMD,r4 /* write data */
442 mtspr SPRN_SCOMC,r3 /* write command */
447 /* restore interrupts */
450 #endif /* CONFIG_CPU_FREQ_PMAC64 || CONFIG_CPU_FREQ_MAPLE */
452 /* kexec_wait(phys_cpu)
454 * wait for the flag to change, indicating this kernel is going away but
455 * the slave code for the next one is at addresses 0 to 100.
457 * This is used by all slaves, even those that did not find a matching
458 * paca in the secondary startup code.
460 * Physical (hardware) cpu id should be in r3.
465 addi r5,r5,kexec_flag-1b
468 #ifdef CONFIG_KEXEC /* use no memory without kexec */
475 /* this can be in text because we won't change it until we are
476 * running in real anyways
484 /* kexec_smp_wait(void)
486 * call with interrupts off
487 * note: this is a terminal routine, it does not save lr
489 * get phys id from paca
490 * switch to real mode
491 * mark the paca as no longer used
492 * join other cpus in kexec_wait(phys_id)
494 _GLOBAL(kexec_smp_wait)
495 lhz r3,PACAHWCPUID(r13)
498 li r4,KEXEC_STATE_REAL_MODE
499 stb r4,PACAKEXECSTATE(r13)
505 * switch to real mode (turn mmu off)
506 * we use the early kernel trick that the hardware ignores bits
507 * 0 and 1 (big endian) of the effective address in real mode
509 * don't overwrite r3 here, it is live for kexec_wait above.
511 real_mode: /* assume normal blr return */
514 mflr r11 /* return address to SRR0 */
526 * kexec_sequence(newstack, start, image, control, clear_all())
528 * does the grungy work with stack switching and real mode switches
529 * also does simple calls to other code
532 _GLOBAL(kexec_sequence)
536 /* switch stacks to newstack -- &kexec_stack.stack */
537 stdu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
543 /* save regs for local vars on new stack.
544 * yes, we won't go back, but ...
554 stdu r1,-STACK_FRAME_OVERHEAD-64(r1)
556 /* save args into preserved regs */
557 mr r31,r3 /* newstack (both) */
558 mr r30,r4 /* start (real) */
559 mr r29,r5 /* image (virt) */
560 mr r28,r6 /* control, unused */
561 mr r27,r7 /* clear_all() fn desc */
562 mr r26,r8 /* spare */
563 lhz r25,PACAHWCPUID(r13) /* get our phys cpu from paca */
565 /* disable interrupts, we are overwriting kernel data next */
570 /* copy dest pages, flush whole dest image */
572 bl .kexec_copy_flush /* (image) */
577 /* copy 0x100 bytes starting at start to 0 */
579 mr r4,r30 /* start, aka phys mem offset */
582 bl .copy_and_flush /* (dest, src, copy limit, start offset) */
583 1: /* assume normal blr return */
585 /* release other cpus to the new kernel secondary start at 0x60 */
588 stw r6,kexec_flag-1b(5)
590 /* clear out hardware hash page table and tlb */
591 ld r5,0(r27) /* deref function descriptor */
593 bctrl /* ppc_md.hpte_clear_all(void); */
596 * kexec image calling is:
597 * the first 0x100 bytes of the entry point are copied to 0
599 * all slaves branch to slave = 0x60 (absolute)
600 * slave(phys_cpu_id);
602 * master goes to start = entry point
603 * start(phys_cpu_id, start, 0);
606 * a wrapper is needed to call existing kernels, here is an approximate
607 * description of one method:
610 * start will be near the boot_block (maybe 0x100 bytes before it?)
611 * it will have a 0x60, which will b to boot_block, where it will wait
612 * and 0 will store phys into struct boot-block and load r3 from there,
613 * copy kernel 0-0x100 and tell slaves to back down to 0x60 again
616 * boot block will have all cpus scanning device tree to see if they
617 * are the boot cpu ?????
618 * other device tree differences (prop sizes, va vs pa, etc)...
620 mr r3,r25 # my phys cpu
621 mr r4,r30 # start, aka phys mem offset
624 blr /* image->start(physid, image->start, 0); */
625 #endif /* CONFIG_KEXEC */