2 * This file contains miscellaneous low-level functions.
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
7 * Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com)
8 * PPC64 updates by Dave Engebretsen (engebret@us.ibm.com)
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
17 #include <linux/sys.h>
18 #include <asm/unistd.h>
19 #include <asm/errno.h>
20 #include <asm/processor.h>
22 #include <asm/cache.h>
23 #include <asm/ppc_asm.h>
24 #include <asm/asm-offsets.h>
25 #include <asm/cputable.h>
26 #include <asm/thread_info.h>
27 #include <asm/kexec.h>
31 #ifdef CONFIG_IRQSTACKS
32 _GLOBAL(call_do_softirq)
35 stdu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
43 _GLOBAL(call_handle_irq)
48 stdu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r5)
55 #endif /* CONFIG_IRQSTACKS */
59 .tc ppc64_caches[TC],ppc64_caches
63 * Write any modified data cache blocks out to memory
64 * and invalidate the corresponding instruction cache blocks.
66 * flush_icache_range(unsigned long start, unsigned long stop)
68 * flush all bytes from start through stop-1 inclusive
71 _KPROBE(__flush_icache_range)
74 * Flush the data cache to memory
76 * Different systems have different cache line sizes
77 * and in some cases i-cache and d-cache line sizes differ from
80 ld r10,PPC64_CACHES@toc(r2)
81 lwz r7,DCACHEL1LINESIZE(r10)/* Get cache line size */
83 andc r6,r3,r5 /* round low to line bdy */
84 subf r8,r6,r4 /* compute length */
85 add r8,r8,r5 /* ensure we get enough */
86 lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of cache line size */
87 srw. r8,r8,r9 /* compute line count */
88 beqlr /* nothing to do? */
95 /* Now invalidate the instruction cache */
97 lwz r7,ICACHEL1LINESIZE(r10) /* Get Icache line size */
99 andc r6,r3,r5 /* round low to line bdy */
100 subf r8,r6,r4 /* compute length */
102 lwz r9,ICACHEL1LOGLINESIZE(r10) /* Get log-2 of Icache line size */
103 srw. r8,r8,r9 /* compute line count */
104 beqlr /* nothing to do? */
113 * Like above, but only do the D-cache.
115 * flush_dcache_range(unsigned long start, unsigned long stop)
117 * flush all bytes from start to stop-1 inclusive
119 _GLOBAL(flush_dcache_range)
122 * Flush the data cache to memory
124 * Different systems have different cache line sizes
126 ld r10,PPC64_CACHES@toc(r2)
127 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
129 andc r6,r3,r5 /* round low to line bdy */
130 subf r8,r6,r4 /* compute length */
131 add r8,r8,r5 /* ensure we get enough */
132 lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */
133 srw. r8,r8,r9 /* compute line count */
134 beqlr /* nothing to do? */
143 * Like above, but works on non-mapped physical addresses.
144 * Use only for non-LPAR setups ! It also assumes real mode
145 * is cacheable. Used for flushing out the DART before using
146 * it as uncacheable memory
148 * flush_dcache_phys_range(unsigned long start, unsigned long stop)
150 * flush all bytes from start to stop-1 inclusive
152 _GLOBAL(flush_dcache_phys_range)
153 ld r10,PPC64_CACHES@toc(r2)
154 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
156 andc r6,r3,r5 /* round low to line bdy */
157 subf r8,r6,r4 /* compute length */
158 add r8,r8,r5 /* ensure we get enough */
159 lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */
160 srw. r8,r8,r9 /* compute line count */
161 beqlr /* nothing to do? */
162 mfmsr r5 /* Disable MMU Data Relocation */
175 mtmsr r5 /* Re-enable MMU Data Relocation */
180 _GLOBAL(flush_inval_dcache_range)
181 ld r10,PPC64_CACHES@toc(r2)
182 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
184 andc r6,r3,r5 /* round low to line bdy */
185 subf r8,r6,r4 /* compute length */
186 add r8,r8,r5 /* ensure we get enough */
187 lwz r9,DCACHEL1LOGLINESIZE(r10)/* Get log-2 of dcache line size */
188 srw. r8,r8,r9 /* compute line count */
189 beqlr /* nothing to do? */
202 * Flush a particular page from the data cache to RAM.
203 * Note: this is necessary because the instruction cache does *not*
204 * snoop from the data cache.
206 * void __flush_dcache_icache(void *page)
208 _GLOBAL(__flush_dcache_icache)
210 * Flush the data cache to memory
212 * Different systems have different cache line sizes
215 /* Flush the dcache */
216 ld r7,PPC64_CACHES@toc(r2)
217 clrrdi r3,r3,PAGE_SHIFT /* Page align */
218 lwz r4,DCACHEL1LINESPERPAGE(r7) /* Get # dcache lines per page */
219 lwz r5,DCACHEL1LINESIZE(r7) /* Get dcache line size */
227 /* Now invalidate the icache */
229 lwz r4,ICACHEL1LINESPERPAGE(r7) /* Get # icache lines per page */
230 lwz r5,ICACHEL1LINESIZE(r7) /* Get icache line size */
239 #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE)
241 * Do an IO access in real mode
272 * Do an IO access in real mode
301 #endif /* defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) */
303 #ifdef CONFIG_PPC_PASEMI
305 /* No support in all binutils for these yet, so use defines */
306 #define LBZCIX(RT,RA,RB) .long (0x7c0006aa|(RT<<21)|(RA<<16)|(RB << 11))
307 #define STBCIX(RS,RA,RB) .long (0x7c0007aa|(RS<<21)|(RA<<16)|(RB << 11))
310 _GLOBAL(real_205_readb)
325 _GLOBAL(real_205_writeb)
340 #endif /* CONFIG_PPC_PASEMI */
343 #ifdef CONFIG_CPU_FREQ_PMAC64
345 * SCOM access functions for 970 (FX only for now)
347 * unsigned long scom970_read(unsigned int address);
348 * void scom970_write(unsigned int address, unsigned long value);
350 * The address passed in is the 24 bits register address. This code
351 * is 970 specific and will not check the status bits, so you should
352 * know what you are doing.
354 _GLOBAL(scom970_read)
361 /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
362 * (including parity). On current CPUs they must be 0'd,
363 * and finally or in RW bit
368 /* do the actual scom read */
377 /* XXX: fixup result on some buggy 970's (ouch ! we lost a bit, bah
378 * that's the best we can do). Not implemented yet as we don't use
379 * the scom on any of the bogus CPUs yet, but may have to be done
383 /* restore interrupts */
388 _GLOBAL(scom970_write)
395 /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
396 * (including parity). On current CPUs they must be 0'd.
402 mtspr SPRN_SCOMD,r4 /* write data */
404 mtspr SPRN_SCOMC,r3 /* write command */
409 /* restore interrupts */
412 #endif /* CONFIG_CPU_FREQ_PMAC64 */
416 * Create a kernel thread
417 * kernel_thread(fn, arg, flags)
419 _GLOBAL(kernel_thread)
422 stdu r1,-STACK_FRAME_OVERHEAD(r1)
425 ori r3,r5,CLONE_VM /* flags */
426 oris r3,r3,(CLONE_UNTRACED>>16)
427 li r4,0 /* new sp (unused) */
430 bns+ 1f /* did system call indicate error? */
431 neg r3,r3 /* if so, make return code negative */
432 1: cmpdi 0,r3,0 /* parent or child? */
433 bne 2f /* return if parent */
435 stdu r0,-STACK_FRAME_OVERHEAD(r1)
438 mtlr r29 /* fn addr in lr */
439 mr r3,r30 /* load arg and call fn */
441 li r0,__NR_exit /* exit after child exits */
444 2: addi r1,r1,STACK_FRAME_OVERHEAD
450 * disable_kernel_fp()
453 _GLOBAL(disable_kernel_fp)
455 rldicl r0,r3,(63-MSR_FP_LG),1
456 rldicl r3,r0,(MSR_FP_LG+1),0
457 mtmsrd r3 /* disable use of fpu now */
461 /* kexec_wait(phys_cpu)
463 * wait for the flag to change, indicating this kernel is going away but
464 * the slave code for the next one is at addresses 0 to 100.
466 * This is used by all slaves.
468 * Physical (hardware) cpu id should be in r3.
473 addi r5,r5,kexec_flag-1b
475 li r4,KEXEC_STATE_REAL_MODE
476 stb r4,PACAKEXECSTATE(r13)
480 #ifdef CONFIG_KEXEC /* use no memory without kexec */
487 /* this can be in text because we won't change it until we are
488 * running in real anyways
496 /* kexec_smp_wait(void)
498 * call with interrupts off
499 * note: this is a terminal routine, it does not save lr
501 * get phys id from paca
502 * switch to real mode
503 * join other cpus in kexec_wait(phys_id)
505 _GLOBAL(kexec_smp_wait)
506 lhz r3,PACAHWCPUID(r13)
511 * switch to real mode (turn mmu off)
512 * we use the early kernel trick that the hardware ignores bits
513 * 0 and 1 (big endian) of the effective address in real mode
515 * don't overwrite r3 here, it is live for kexec_wait above.
517 real_mode: /* assume normal blr return */
520 mflr r11 /* return address to SRR0 */
532 * kexec_sequence(newstack, start, image, control, clear_all())
534 * does the grungy work with stack switching and real mode switches
535 * also does simple calls to other code
538 _GLOBAL(kexec_sequence)
542 /* switch stacks to newstack -- &kexec_stack.stack */
543 stdu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
549 /* save regs for local vars on new stack.
550 * yes, we won't go back, but ...
560 stdu r1,-STACK_FRAME_OVERHEAD-64(r1)
562 /* save args into preserved regs */
563 mr r31,r3 /* newstack (both) */
564 mr r30,r4 /* start (real) */
565 mr r29,r5 /* image (virt) */
566 mr r28,r6 /* control, unused */
567 mr r27,r7 /* clear_all() fn desc */
568 mr r26,r8 /* spare */
569 lhz r25,PACAHWCPUID(r13) /* get our phys cpu from paca */
571 /* disable interrupts, we are overwriting kernel data next */
576 /* copy dest pages, flush whole dest image */
578 bl .kexec_copy_flush /* (image) */
583 /* copy 0x100 bytes starting at start to 0 */
585 mr r4,r30 /* start, aka phys mem offset */
588 bl .copy_and_flush /* (dest, src, copy limit, start offset) */
589 1: /* assume normal blr return */
591 /* release other cpus to the new kernel secondary start at 0x60 */
594 stw r6,kexec_flag-1b(5)
596 /* clear out hardware hash page table and tlb */
597 ld r5,0(r27) /* deref function descriptor */
599 bctrl /* ppc_md.hpte_clear_all(void); */
602 * kexec image calling is:
603 * the first 0x100 bytes of the entry point are copied to 0
605 * all slaves branch to slave = 0x60 (absolute)
606 * slave(phys_cpu_id);
608 * master goes to start = entry point
609 * start(phys_cpu_id, start, 0);
612 * a wrapper is needed to call existing kernels, here is an approximate
613 * description of one method:
616 * start will be near the boot_block (maybe 0x100 bytes before it?)
617 * it will have a 0x60, which will b to boot_block, where it will wait
618 * and 0 will store phys into struct boot-block and load r3 from there,
619 * copy kernel 0-0x100 and tell slaves to back down to 0x60 again
622 * boot block will have all cpus scanning device tree to see if they
623 * are the boot cpu ?????
624 * other device tree differences (prop sizes, va vs pa, etc)...
626 mr r3,r25 # my phys cpu
627 mr r4,r30 # start, aka phys mem offset
630 blr /* image->start(physid, image->start, 0); */
631 #endif /* CONFIG_KEXEC */