2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/bootmem.h>
24 #include <linux/export.h>
25 #include <linux/of_address.h>
26 #include <linux/of_pci.h>
28 #include <linux/list.h>
29 #include <linux/syscalls.h>
30 #include <linux/irq.h>
31 #include <linux/vmalloc.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
35 #include <asm/processor.h>
38 #include <asm/pci-bridge.h>
39 #include <asm/byteorder.h>
40 #include <asm/machdep.h>
41 #include <asm/ppc-pci.h>
44 static DEFINE_SPINLOCK(hose_spinlock);
47 /* XXX kill that some day ... */
48 static int global_phb_number; /* Global phb counter */
50 /* ISA Memory physical address */
51 resource_size_t isa_mem_base;
54 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
56 void set_pci_dma_ops(struct dma_map_ops *dma_ops)
58 pci_dma_ops = dma_ops;
61 struct dma_map_ops *get_pci_dma_ops(void)
65 EXPORT_SYMBOL(get_pci_dma_ops);
67 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
69 struct pci_controller *phb;
71 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
74 spin_lock(&hose_spinlock);
75 phb->global_number = global_phb_number++;
76 list_add_tail(&phb->list_node, &hose_list);
77 spin_unlock(&hose_spinlock);
79 phb->is_dynamic = mem_init_done;
82 int nid = of_node_to_nid(dev);
84 if (nid < 0 || !node_online(nid))
87 PHB_SET_NODE(phb, nid);
93 void pcibios_free_controller(struct pci_controller *phb)
95 spin_lock(&hose_spinlock);
96 list_del(&phb->list_node);
97 spin_unlock(&hose_spinlock);
104 * The function is used to return the minimal alignment
105 * for memory or I/O windows of the associated P2P bridge.
106 * By default, 4KiB alignment for I/O windows and 1MiB for
109 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
112 if (ppc_md.pcibios_window_alignment)
113 return ppc_md.pcibios_window_alignment(bus, type);
116 * PCI core will figure out the default
117 * alignment: 4KiB for I/O and 1MiB for
123 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
126 return hose->pci_io_size;
128 return resource_size(&hose->io_resource);
132 int pcibios_vaddr_is_ioport(void __iomem *address)
135 struct pci_controller *hose;
136 resource_size_t size;
138 spin_lock(&hose_spinlock);
139 list_for_each_entry(hose, &hose_list, list_node) {
140 size = pcibios_io_size(hose);
141 if (address >= hose->io_base_virt &&
142 address < (hose->io_base_virt + size)) {
147 spin_unlock(&hose_spinlock);
151 unsigned long pci_address_to_pio(phys_addr_t address)
153 struct pci_controller *hose;
154 resource_size_t size;
155 unsigned long ret = ~0;
157 spin_lock(&hose_spinlock);
158 list_for_each_entry(hose, &hose_list, list_node) {
159 size = pcibios_io_size(hose);
160 if (address >= hose->io_base_phys &&
161 address < (hose->io_base_phys + size)) {
163 (unsigned long)hose->io_base_virt - _IO_BASE;
164 ret = base + (address - hose->io_base_phys);
168 spin_unlock(&hose_spinlock);
172 EXPORT_SYMBOL_GPL(pci_address_to_pio);
175 * Return the domain number for this bus.
177 int pci_domain_nr(struct pci_bus *bus)
179 struct pci_controller *hose = pci_bus_to_host(bus);
181 return hose->global_number;
183 EXPORT_SYMBOL(pci_domain_nr);
185 /* This routine is meant to be used early during boot, when the
186 * PCI bus numbers have not yet been assigned, and you need to
187 * issue PCI config cycles to an OF device.
188 * It could also be used to "fix" RTAS config cycles if you want
189 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
192 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
195 struct pci_controller *hose, *tmp;
196 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
197 if (hose->dn == node)
205 * Reads the interrupt pin to determine if interrupt is use by card.
206 * If the interrupt is used, then gets the interrupt line from the
207 * openfirmware and sets it in the pci_dev and pci_config line.
209 static int pci_read_irq_line(struct pci_dev *pci_dev)
211 struct of_phandle_args oirq;
214 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
217 memset(&oirq, 0xff, sizeof(oirq));
219 /* Try to get a mapping from the device-tree */
220 if (of_irq_parse_pci(pci_dev, &oirq)) {
223 /* If that fails, lets fallback to what is in the config
224 * space and map that through the default controller. We
225 * also set the type to level low since that's what PCI
226 * interrupts are. If your platform does differently, then
227 * either provide a proper interrupt tree or don't use this
230 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
234 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
235 line == 0xff || line == 0) {
238 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
241 virq = irq_create_mapping(NULL, line);
243 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
245 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
246 oirq.args_count, oirq.args[0], oirq.args[1],
247 of_node_full_name(oirq.np));
249 virq = irq_create_of_mapping(&oirq);
252 pr_debug(" Failed to map !\n");
256 pr_debug(" Mapped to linux irq %d\n", virq);
264 * Platform support for /proc/bus/pci/X/Y mmap()s,
265 * modelled on the sparc64 implementation by Dave Miller.
270 * Adjust vm_pgoff of VMA such that it is the physical page offset
271 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
273 * Basically, the user finds the base address for his device which he wishes
274 * to mmap. They read the 32-bit value from the config space base register,
275 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
276 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
278 * Returns negative error code on failure, zero on success.
280 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
281 resource_size_t *offset,
282 enum pci_mmap_state mmap_state)
284 struct pci_controller *hose = pci_bus_to_host(dev->bus);
285 unsigned long io_offset = 0;
289 return NULL; /* should never happen */
291 /* If memory, add on the PCI bridge address offset */
292 if (mmap_state == pci_mmap_mem) {
293 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
294 *offset += hose->pci_mem_offset;
296 res_bit = IORESOURCE_MEM;
298 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
299 *offset += io_offset;
300 res_bit = IORESOURCE_IO;
304 * Check that the offset requested corresponds to one of the
305 * resources of the device.
307 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
308 struct resource *rp = &dev->resource[i];
309 int flags = rp->flags;
311 /* treat ROM as memory (should be already) */
312 if (i == PCI_ROM_RESOURCE)
313 flags |= IORESOURCE_MEM;
315 /* Active and same type? */
316 if ((flags & res_bit) == 0)
319 /* In the range of this resource? */
320 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
323 /* found it! construct the final physical address */
324 if (mmap_state == pci_mmap_io)
325 *offset += hose->io_base_phys - io_offset;
333 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
336 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
338 enum pci_mmap_state mmap_state,
342 /* Write combine is always 0 on non-memory space mappings. On
343 * memory space, if the user didn't pass 1, we check for a
344 * "prefetchable" resource. This is a bit hackish, but we use
345 * this to workaround the inability of /sysfs to provide a write
348 if (mmap_state != pci_mmap_mem)
350 else if (write_combine == 0) {
351 if (rp->flags & IORESOURCE_PREFETCH)
355 /* XXX would be nice to have a way to ask for write-through */
357 return pgprot_noncached_wc(protection);
359 return pgprot_noncached(protection);
363 * This one is used by /dev/mem and fbdev who have no clue about the
364 * PCI device, it tries to find the PCI device first and calls the
367 pgprot_t pci_phys_mem_access_prot(struct file *file,
372 struct pci_dev *pdev = NULL;
373 struct resource *found = NULL;
374 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
377 if (page_is_ram(pfn))
380 prot = pgprot_noncached(prot);
381 for_each_pci_dev(pdev) {
382 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
383 struct resource *rp = &pdev->resource[i];
384 int flags = rp->flags;
386 /* Active and same type? */
387 if ((flags & IORESOURCE_MEM) == 0)
389 /* In the range of this resource? */
390 if (offset < (rp->start & PAGE_MASK) ||
400 if (found->flags & IORESOURCE_PREFETCH)
401 prot = pgprot_noncached_wc(prot);
405 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
406 (unsigned long long)offset, pgprot_val(prot));
413 * Perform the actual remap of the pages for a PCI device mapping, as
414 * appropriate for this architecture. The region in the process to map
415 * is described by vm_start and vm_end members of VMA, the base physical
416 * address is found in vm_pgoff.
417 * The pci device structure is provided so that architectures may make mapping
418 * decisions on a per-device or per-bus basis.
420 * Returns a negative error code on failure, zero on success.
422 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
423 enum pci_mmap_state mmap_state, int write_combine)
425 resource_size_t offset =
426 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
430 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
434 vma->vm_pgoff = offset >> PAGE_SHIFT;
435 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
437 mmap_state, write_combine);
439 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
440 vma->vm_end - vma->vm_start, vma->vm_page_prot);
445 /* This provides legacy IO read access on a bus */
446 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
448 unsigned long offset;
449 struct pci_controller *hose = pci_bus_to_host(bus);
450 struct resource *rp = &hose->io_resource;
453 /* Check if port can be supported by that bus. We only check
454 * the ranges of the PHB though, not the bus itself as the rules
455 * for forwarding legacy cycles down bridges are not our problem
456 * here. So if the host bridge supports it, we do it.
458 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
461 if (!(rp->flags & IORESOURCE_IO))
463 if (offset < rp->start || (offset + size) > rp->end)
465 addr = hose->io_base_virt + port;
469 *((u8 *)val) = in_8(addr);
474 *((u16 *)val) = in_le16(addr);
479 *((u32 *)val) = in_le32(addr);
485 /* This provides legacy IO write access on a bus */
486 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
488 unsigned long offset;
489 struct pci_controller *hose = pci_bus_to_host(bus);
490 struct resource *rp = &hose->io_resource;
493 /* Check if port can be supported by that bus. We only check
494 * the ranges of the PHB though, not the bus itself as the rules
495 * for forwarding legacy cycles down bridges are not our problem
496 * here. So if the host bridge supports it, we do it.
498 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
501 if (!(rp->flags & IORESOURCE_IO))
503 if (offset < rp->start || (offset + size) > rp->end)
505 addr = hose->io_base_virt + port;
507 /* WARNING: The generic code is idiotic. It gets passed a pointer
508 * to what can be a 1, 2 or 4 byte quantity and always reads that
509 * as a u32, which means that we have to correct the location of
510 * the data read within those 32 bits for size 1 and 2
514 out_8(addr, val >> 24);
519 out_le16(addr, val >> 16);
530 /* This provides legacy IO or memory mmap access on a bus */
531 int pci_mmap_legacy_page_range(struct pci_bus *bus,
532 struct vm_area_struct *vma,
533 enum pci_mmap_state mmap_state)
535 struct pci_controller *hose = pci_bus_to_host(bus);
536 resource_size_t offset =
537 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
538 resource_size_t size = vma->vm_end - vma->vm_start;
541 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
542 pci_domain_nr(bus), bus->number,
543 mmap_state == pci_mmap_mem ? "MEM" : "IO",
544 (unsigned long long)offset,
545 (unsigned long long)(offset + size - 1));
547 if (mmap_state == pci_mmap_mem) {
550 * Because X is lame and can fail starting if it gets an error trying
551 * to mmap legacy_mem (instead of just moving on without legacy memory
552 * access) we fake it here by giving it anonymous memory, effectively
553 * behaving just like /dev/zero
555 if ((offset + size) > hose->isa_mem_size) {
557 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
558 current->comm, current->pid, pci_domain_nr(bus), bus->number);
559 if (vma->vm_flags & VM_SHARED)
560 return shmem_zero_setup(vma);
563 offset += hose->isa_mem_phys;
565 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
566 unsigned long roffset = offset + io_offset;
567 rp = &hose->io_resource;
568 if (!(rp->flags & IORESOURCE_IO))
570 if (roffset < rp->start || (roffset + size) > rp->end)
572 offset += hose->io_base_phys;
574 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
576 vma->vm_pgoff = offset >> PAGE_SHIFT;
577 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
578 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
579 vma->vm_end - vma->vm_start,
583 void pci_resource_to_user(const struct pci_dev *dev, int bar,
584 const struct resource *rsrc,
585 resource_size_t *start, resource_size_t *end)
587 struct pci_controller *hose = pci_bus_to_host(dev->bus);
588 resource_size_t offset = 0;
593 if (rsrc->flags & IORESOURCE_IO)
594 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
596 /* We pass a fully fixed up address to userland for MMIO instead of
597 * a BAR value because X is lame and expects to be able to use that
598 * to pass to /dev/mem !
600 * That means that we'll have potentially 64 bits values where some
601 * userland apps only expect 32 (like X itself since it thinks only
602 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
605 * Hopefully, the sysfs insterface is immune to that gunk. Once X
606 * has been fixed (and the fix spread enough), we can re-enable the
607 * 2 lines below and pass down a BAR value to userland. In that case
608 * we'll also have to re-enable the matching code in
609 * __pci_mmap_make_offset().
614 else if (rsrc->flags & IORESOURCE_MEM)
615 offset = hose->pci_mem_offset;
618 *start = rsrc->start - offset;
619 *end = rsrc->end - offset;
623 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
624 * @hose: newly allocated pci_controller to be setup
625 * @dev: device node of the host bridge
626 * @primary: set if primary bus (32 bits only, soon to be deprecated)
628 * This function will parse the "ranges" property of a PCI host bridge device
629 * node and setup the resource mapping of a pci controller based on its
632 * Life would be boring if it wasn't for a few issues that we have to deal
635 * - We can only cope with one IO space range and up to 3 Memory space
636 * ranges. However, some machines (thanks Apple !) tend to split their
637 * space into lots of small contiguous ranges. So we have to coalesce.
639 * - Some busses have IO space not starting at 0, which causes trouble with
640 * the way we do our IO resource renumbering. The code somewhat deals with
641 * it for 64 bits but I would expect problems on 32 bits.
643 * - Some 32 bits platforms such as 4xx can have physical space larger than
644 * 32 bits so we need to use 64 bits values for the parsing
646 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
647 struct device_node *dev, int primary)
649 const __be32 *ranges;
651 int pna = of_n_addr_cells(dev);
655 unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size;
656 struct resource *res;
658 printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
659 dev->full_name, primary ? "(primary)" : "");
661 /* Get ranges property */
662 ranges = of_get_property(dev, "ranges", &rlen);
667 while ((rlen -= np * 4) >= 0) {
668 /* Read next ranges element */
669 pci_space = of_read_number(ranges, 1);
670 pci_addr = of_read_number(ranges + 1, 2);
671 cpu_addr = of_translate_address(dev, ranges + 3);
672 size = of_read_number(ranges + pna + 3, 2);
675 /* If we failed translation or got a zero-sized region
676 * (some FW try to feed us with non sensical zero sized regions
677 * such as power3 which look like some kind of attempt at exposing
678 * the VGA memory hole)
680 if (cpu_addr == OF_BAD_ADDR || size == 0)
683 /* Now consume following elements while they are contiguous */
684 for (; rlen >= np * sizeof(u32);
685 ranges += np, rlen -= np * 4) {
686 if (of_read_number(ranges, 1) != pci_space)
688 pci_next = of_read_number(ranges + 1, 2);
689 cpu_next = of_translate_address(dev, ranges + 3);
690 if (pci_next != pci_addr + size ||
691 cpu_next != cpu_addr + size)
693 size += of_read_number(ranges + pna + 3, 2);
696 /* Act based on address space type */
698 switch ((pci_space >> 24) & 0x3) {
699 case 1: /* PCI IO space */
701 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
702 cpu_addr, cpu_addr + size - 1, pci_addr);
704 /* We support only one IO range */
705 if (hose->pci_io_size) {
707 " \\--> Skipped (too many) !\n");
711 /* On 32 bits, limit I/O space to 16MB */
712 if (size > 0x01000000)
715 /* 32 bits needs to map IOs here */
716 hose->io_base_virt = ioremap(cpu_addr, size);
718 /* Expect trouble if pci_addr is not 0 */
721 (unsigned long)hose->io_base_virt;
722 #endif /* CONFIG_PPC32 */
723 /* pci_io_size and io_base_phys always represent IO
724 * space starting at 0 so we factor in pci_addr
726 hose->pci_io_size = pci_addr + size;
727 hose->io_base_phys = cpu_addr - pci_addr;
730 res = &hose->io_resource;
731 res->flags = IORESOURCE_IO;
732 res->start = pci_addr;
734 case 2: /* PCI Memory space */
735 case 3: /* PCI 64 bits Memory space */
737 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
738 cpu_addr, cpu_addr + size - 1, pci_addr,
739 (pci_space & 0x40000000) ? "Prefetch" : "");
741 /* We support only 3 memory ranges */
744 " \\--> Skipped (too many) !\n");
747 /* Handles ISA memory hole space here */
749 if (primary || isa_mem_base == 0)
750 isa_mem_base = cpu_addr;
751 hose->isa_mem_phys = cpu_addr;
752 hose->isa_mem_size = size;
756 hose->mem_offset[memno] = cpu_addr - pci_addr;
757 res = &hose->mem_resources[memno++];
758 res->flags = IORESOURCE_MEM;
759 if (pci_space & 0x40000000)
760 res->flags |= IORESOURCE_PREFETCH;
761 res->start = cpu_addr;
765 res->name = dev->full_name;
766 res->end = res->start + size - 1;
774 /* Decide whether to display the domain number in /proc */
775 int pci_proc_domain(struct pci_bus *bus)
777 struct pci_controller *hose = pci_bus_to_host(bus);
779 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
781 if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
782 return hose->global_number != 0;
786 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
788 if (ppc_md.pcibios_root_bridge_prepare)
789 return ppc_md.pcibios_root_bridge_prepare(bridge);
794 /* This header fixup will do the resource fixup for all devices as they are
795 * probed, but not for bridge ranges
797 static void pcibios_fixup_resources(struct pci_dev *dev)
799 struct pci_controller *hose = pci_bus_to_host(dev->bus);
803 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
807 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
808 struct resource *res = dev->resource + i;
809 struct pci_bus_region reg;
813 /* If we're going to re-assign everything, we mark all resources
814 * as unset (and 0-base them). In addition, we mark BARs starting
815 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
816 * since in that case, we don't want to re-assign anything
818 pcibios_resource_to_bus(dev->bus, ®, res);
819 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
820 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
821 /* Only print message if not re-assigning */
822 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
823 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] "
826 (unsigned long long)res->start,
827 (unsigned long long)res->end,
828 (unsigned int)res->flags);
829 res->end -= res->start;
831 res->flags |= IORESOURCE_UNSET;
835 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
837 (unsigned long long)res->start,\
838 (unsigned long long)res->end,
839 (unsigned int)res->flags);
842 /* Call machine specific resource fixup */
843 if (ppc_md.pcibios_fixup_resources)
844 ppc_md.pcibios_fixup_resources(dev);
846 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
848 /* This function tries to figure out if a bridge resource has been initialized
849 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
850 * things go more smoothly when it gets it right. It should covers cases such
851 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
853 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
854 struct resource *res)
856 struct pci_controller *hose = pci_bus_to_host(bus);
857 struct pci_dev *dev = bus->self;
858 resource_size_t offset;
859 struct pci_bus_region region;
863 /* We don't do anything if PCI_PROBE_ONLY is set */
864 if (pci_has_flag(PCI_PROBE_ONLY))
867 /* Job is a bit different between memory and IO */
868 if (res->flags & IORESOURCE_MEM) {
869 pcibios_resource_to_bus(dev->bus, ®ion, res);
871 /* If the BAR is non-0 then it's probably been initialized */
872 if (region.start != 0)
875 /* The BAR is 0, let's check if memory decoding is enabled on
876 * the bridge. If not, we consider it unassigned
878 pci_read_config_word(dev, PCI_COMMAND, &command);
879 if ((command & PCI_COMMAND_MEMORY) == 0)
882 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
883 * resources covers that starting address (0 then it's good enough for
884 * us for memory space)
886 for (i = 0; i < 3; i++) {
887 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
888 hose->mem_resources[i].start == hose->mem_offset[i])
892 /* Well, it starts at 0 and we know it will collide so we may as
893 * well consider it as unassigned. That covers the Apple case.
897 /* If the BAR is non-0, then we consider it assigned */
898 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
899 if (((res->start - offset) & 0xfffffffful) != 0)
902 /* Here, we are a bit different than memory as typically IO space
903 * starting at low addresses -is- valid. What we do instead if that
904 * we consider as unassigned anything that doesn't have IO enabled
905 * in the PCI command register, and that's it.
907 pci_read_config_word(dev, PCI_COMMAND, &command);
908 if (command & PCI_COMMAND_IO)
911 /* It's starting at 0 and IO is disabled in the bridge, consider
918 /* Fixup resources of a PCI<->PCI bridge */
919 static void pcibios_fixup_bridge(struct pci_bus *bus)
921 struct resource *res;
924 struct pci_dev *dev = bus->self;
926 pci_bus_for_each_resource(bus, res, i) {
927 if (!res || !res->flags)
929 if (i >= 3 && bus->self->transparent)
932 /* If we're going to reassign everything, we can
933 * shrink the P2P resource to have size as being
934 * of 0 in order to save space.
936 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
937 res->flags |= IORESOURCE_UNSET;
943 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x]\n",
945 (unsigned long long)res->start,\
946 (unsigned long long)res->end,
947 (unsigned int)res->flags);
949 /* Try to detect uninitialized P2P bridge resources,
950 * and clear them out so they get re-assigned later
952 if (pcibios_uninitialized_bridge_resource(bus, res)) {
954 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
959 void pcibios_setup_bus_self(struct pci_bus *bus)
961 /* Fix up the bus resources for P2P bridges */
962 if (bus->self != NULL)
963 pcibios_fixup_bridge(bus);
965 /* Platform specific bus fixups. This is currently only used
966 * by fsl_pci and I'm hoping to get rid of it at some point
968 if (ppc_md.pcibios_fixup_bus)
969 ppc_md.pcibios_fixup_bus(bus);
971 /* Setup bus DMA mappings */
972 if (ppc_md.pci_dma_bus_setup)
973 ppc_md.pci_dma_bus_setup(bus);
976 static void pcibios_setup_device(struct pci_dev *dev)
978 /* Fixup NUMA node as it may not be setup yet by the generic
979 * code and is needed by the DMA init
981 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
983 /* Hook up default DMA ops */
984 set_dma_ops(&dev->dev, pci_dma_ops);
985 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
987 /* Additional platform DMA/iommu setup */
988 if (ppc_md.pci_dma_dev_setup)
989 ppc_md.pci_dma_dev_setup(dev);
991 /* Read default IRQs and fixup if necessary */
992 pci_read_irq_line(dev);
993 if (ppc_md.pci_irq_fixup)
994 ppc_md.pci_irq_fixup(dev);
997 int pcibios_add_device(struct pci_dev *dev)
1000 * We can only call pcibios_setup_device() after bus setup is complete,
1001 * since some of the platform specific DMA setup code depends on it.
1003 if (dev->bus->is_added)
1004 pcibios_setup_device(dev);
1008 void pcibios_setup_bus_devices(struct pci_bus *bus)
1010 struct pci_dev *dev;
1012 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1013 bus->number, bus->self ? pci_name(bus->self) : "PHB");
1015 list_for_each_entry(dev, &bus->devices, bus_list) {
1016 /* Cardbus can call us to add new devices to a bus, so ignore
1017 * those who are already fully discovered
1022 pcibios_setup_device(dev);
1026 void pcibios_set_master(struct pci_dev *dev)
1028 /* No special bus mastering setup handling */
1031 void pcibios_fixup_bus(struct pci_bus *bus)
1033 /* When called from the generic PCI probe, read PCI<->PCI bridge
1034 * bases. This is -not- called when generating the PCI tree from
1035 * the OF device-tree.
1037 pci_read_bridge_bases(bus);
1039 /* Now fixup the bus bus */
1040 pcibios_setup_bus_self(bus);
1042 /* Now fixup devices on that bus */
1043 pcibios_setup_bus_devices(bus);
1045 EXPORT_SYMBOL(pcibios_fixup_bus);
1047 void pci_fixup_cardbus(struct pci_bus *bus)
1049 /* Now fixup devices on that bus */
1050 pcibios_setup_bus_devices(bus);
1054 static int skip_isa_ioresource_align(struct pci_dev *dev)
1056 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
1057 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1063 * We need to avoid collisions with `mirrored' VGA ports
1064 * and other strange ISA hardware, so we always want the
1065 * addresses to be allocated in the 0x000-0x0ff region
1068 * Why? Because some silly external IO cards only decode
1069 * the low 10 bits of the IO address. The 0x00-0xff region
1070 * is reserved for motherboard devices that decode all 16
1071 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1072 * but we want to try to avoid allocating at 0x2900-0x2bff
1073 * which might have be mirrored at 0x0100-0x03ff..
1075 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1076 resource_size_t size, resource_size_t align)
1078 struct pci_dev *dev = data;
1079 resource_size_t start = res->start;
1081 if (res->flags & IORESOURCE_IO) {
1082 if (skip_isa_ioresource_align(dev))
1085 start = (start + 0x3ff) & ~0x3ff;
1090 EXPORT_SYMBOL(pcibios_align_resource);
1093 * Reparent resource children of pr that conflict with res
1094 * under res, and make res replace those children.
1096 static int reparent_resources(struct resource *parent,
1097 struct resource *res)
1099 struct resource *p, **pp;
1100 struct resource **firstpp = NULL;
1102 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1103 if (p->end < res->start)
1105 if (res->end < p->start)
1107 if (p->start < res->start || p->end > res->end)
1108 return -1; /* not completely contained */
1109 if (firstpp == NULL)
1112 if (firstpp == NULL)
1113 return -1; /* didn't find any conflicting entries? */
1114 res->parent = parent;
1115 res->child = *firstpp;
1119 for (p = res->child; p != NULL; p = p->sibling) {
1121 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1123 (unsigned long long)p->start,
1124 (unsigned long long)p->end, res->name);
1130 * Handle resources of PCI devices. If the world were perfect, we could
1131 * just allocate all the resource regions and do nothing more. It isn't.
1132 * On the other hand, we cannot just re-allocate all devices, as it would
1133 * require us to know lots of host bridge internals. So we attempt to
1134 * keep as much of the original configuration as possible, but tweak it
1135 * when it's found to be wrong.
1137 * Known BIOS problems we have to work around:
1138 * - I/O or memory regions not configured
1139 * - regions configured, but not enabled in the command register
1140 * - bogus I/O addresses above 64K used
1141 * - expansion ROMs left enabled (this may sound harmless, but given
1142 * the fact the PCI specs explicitly allow address decoders to be
1143 * shared between expansion ROMs and other resource regions, it's
1144 * at least dangerous)
1147 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1148 * This gives us fixed barriers on where we can allocate.
1149 * (2) Allocate resources for all enabled devices. If there is
1150 * a collision, just mark the resource as unallocated. Also
1151 * disable expansion ROMs during this step.
1152 * (3) Try to allocate resources for disabled devices. If the
1153 * resources were assigned correctly, everything goes well,
1154 * if they weren't, they won't disturb allocation of other
1156 * (4) Assign new addresses to resources which were either
1157 * not configured at all or misconfigured. If explicitly
1158 * requested by the user, configure expansion ROM address
1162 void pcibios_allocate_bus_resources(struct pci_bus *bus)
1166 struct resource *res, *pr;
1168 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1169 pci_domain_nr(bus), bus->number);
1171 pci_bus_for_each_resource(bus, res, i) {
1172 if (!res || !res->flags || res->start > res->end || res->parent)
1175 /* If the resource was left unset at this point, we clear it */
1176 if (res->flags & IORESOURCE_UNSET)
1177 goto clear_resource;
1179 if (bus->parent == NULL)
1180 pr = (res->flags & IORESOURCE_IO) ?
1181 &ioport_resource : &iomem_resource;
1183 pr = pci_find_parent_resource(bus->self, res);
1185 /* this happens when the generic PCI
1186 * code (wrongly) decides that this
1187 * bridge is transparent -- paulus
1193 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1194 "[0x%x], parent %p (%s)\n",
1195 bus->self ? pci_name(bus->self) : "PHB",
1197 (unsigned long long)res->start,
1198 (unsigned long long)res->end,
1199 (unsigned int)res->flags,
1200 pr, (pr && pr->name) ? pr->name : "nil");
1202 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1203 if (request_resource(pr, res) == 0)
1206 * Must be a conflict with an existing entry.
1207 * Move that entry (or entries) under the
1208 * bridge resource and try again.
1210 if (reparent_resources(pr, res) == 0)
1213 pr_warning("PCI: Cannot allocate resource region "
1214 "%d of PCI bridge %d, will remap\n", i, bus->number);
1216 /* The resource might be figured out when doing
1217 * reassignment based on the resources required
1218 * by the downstream PCI devices. Here we set
1219 * the size of the resource to be 0 in order to
1227 list_for_each_entry(b, &bus->children, node)
1228 pcibios_allocate_bus_resources(b);
1231 static inline void alloc_resource(struct pci_dev *dev, int idx)
1233 struct resource *pr, *r = &dev->resource[idx];
1235 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1237 (unsigned long long)r->start,
1238 (unsigned long long)r->end,
1239 (unsigned int)r->flags);
1241 pr = pci_find_parent_resource(dev, r);
1242 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1243 request_resource(pr, r) < 0) {
1244 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1245 " of device %s, will remap\n", idx, pci_name(dev));
1247 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1249 (unsigned long long)pr->start,
1250 (unsigned long long)pr->end,
1251 (unsigned int)pr->flags);
1252 /* We'll assign a new address later */
1253 r->flags |= IORESOURCE_UNSET;
1259 static void __init pcibios_allocate_resources(int pass)
1261 struct pci_dev *dev = NULL;
1266 for_each_pci_dev(dev) {
1267 pci_read_config_word(dev, PCI_COMMAND, &command);
1268 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1269 r = &dev->resource[idx];
1270 if (r->parent) /* Already allocated */
1272 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1273 continue; /* Not assigned at all */
1274 /* We only allocate ROMs on pass 1 just in case they
1275 * have been screwed up by firmware
1277 if (idx == PCI_ROM_RESOURCE )
1279 if (r->flags & IORESOURCE_IO)
1280 disabled = !(command & PCI_COMMAND_IO);
1282 disabled = !(command & PCI_COMMAND_MEMORY);
1283 if (pass == disabled)
1284 alloc_resource(dev, idx);
1288 r = &dev->resource[PCI_ROM_RESOURCE];
1290 /* Turn the ROM off, leave the resource region,
1291 * but keep it unregistered.
1294 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1295 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1296 pr_debug("PCI: Switching off ROM of %s\n",
1298 r->flags &= ~IORESOURCE_ROM_ENABLE;
1299 pci_write_config_dword(dev, dev->rom_base_reg,
1300 reg & ~PCI_ROM_ADDRESS_ENABLE);
1306 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1308 struct pci_controller *hose = pci_bus_to_host(bus);
1309 resource_size_t offset;
1310 struct resource *res, *pres;
1313 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1316 if (!(hose->io_resource.flags & IORESOURCE_IO))
1318 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1319 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1320 BUG_ON(res == NULL);
1321 res->name = "Legacy IO";
1322 res->flags = IORESOURCE_IO;
1323 res->start = offset;
1324 res->end = (offset + 0xfff) & 0xfffffffful;
1325 pr_debug("Candidate legacy IO: %pR\n", res);
1326 if (request_resource(&hose->io_resource, res)) {
1328 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1329 pci_domain_nr(bus), bus->number, res);
1334 /* Check for memory */
1335 for (i = 0; i < 3; i++) {
1336 pres = &hose->mem_resources[i];
1337 offset = hose->mem_offset[i];
1338 if (!(pres->flags & IORESOURCE_MEM))
1340 pr_debug("hose mem res: %pR\n", pres);
1341 if ((pres->start - offset) <= 0xa0000 &&
1342 (pres->end - offset) >= 0xbffff)
1347 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1348 BUG_ON(res == NULL);
1349 res->name = "Legacy VGA memory";
1350 res->flags = IORESOURCE_MEM;
1351 res->start = 0xa0000 + offset;
1352 res->end = 0xbffff + offset;
1353 pr_debug("Candidate VGA memory: %pR\n", res);
1354 if (request_resource(pres, res)) {
1356 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1357 pci_domain_nr(bus), bus->number, res);
1362 void __init pcibios_resource_survey(void)
1366 /* Allocate and assign resources */
1367 list_for_each_entry(b, &pci_root_buses, node)
1368 pcibios_allocate_bus_resources(b);
1369 pcibios_allocate_resources(0);
1370 pcibios_allocate_resources(1);
1372 /* Before we start assigning unassigned resource, we try to reserve
1373 * the low IO area and the VGA memory area if they intersect the
1374 * bus available resources to avoid allocating things on top of them
1376 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1377 list_for_each_entry(b, &pci_root_buses, node)
1378 pcibios_reserve_legacy_regions(b);
1381 /* Now, if the platform didn't decide to blindly trust the firmware,
1382 * we proceed to assigning things that were left unassigned
1384 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1385 pr_debug("PCI: Assigning unassigned resources...\n");
1386 pci_assign_unassigned_resources();
1389 /* Call machine dependent fixup */
1390 if (ppc_md.pcibios_fixup)
1391 ppc_md.pcibios_fixup();
1394 /* This is used by the PCI hotplug driver to allocate resource
1395 * of newly plugged busses. We can try to consolidate with the
1396 * rest of the code later, for now, keep it as-is as our main
1397 * resource allocation function doesn't deal with sub-trees yet.
1399 void pcibios_claim_one_bus(struct pci_bus *bus)
1401 struct pci_dev *dev;
1402 struct pci_bus *child_bus;
1404 list_for_each_entry(dev, &bus->devices, bus_list) {
1407 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1408 struct resource *r = &dev->resource[i];
1410 if (r->parent || !r->start || !r->flags)
1413 pr_debug("PCI: Claiming %s: "
1414 "Resource %d: %016llx..%016llx [%x]\n",
1416 (unsigned long long)r->start,
1417 (unsigned long long)r->end,
1418 (unsigned int)r->flags);
1420 pci_claim_resource(dev, i);
1424 list_for_each_entry(child_bus, &bus->children, node)
1425 pcibios_claim_one_bus(child_bus);
1429 /* pcibios_finish_adding_to_bus
1431 * This is to be called by the hotplug code after devices have been
1432 * added to a bus, this include calling it for a PHB that is just
1435 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1437 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1438 pci_domain_nr(bus), bus->number);
1440 /* Allocate bus and devices resources */
1441 pcibios_allocate_bus_resources(bus);
1442 pcibios_claim_one_bus(bus);
1443 if (!pci_has_flag(PCI_PROBE_ONLY))
1444 pci_assign_unassigned_bus_resources(bus);
1447 eeh_add_device_tree_late(bus);
1449 /* Add new devices to global lists. Register in proc, sysfs. */
1450 pci_bus_add_devices(bus);
1452 /* sysfs files should only be added after devices are added */
1453 eeh_add_sysfs_files(bus);
1455 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1457 int pcibios_enable_device(struct pci_dev *dev, int mask)
1459 if (ppc_md.pcibios_enable_device_hook)
1460 if (ppc_md.pcibios_enable_device_hook(dev))
1463 return pci_enable_resources(dev, mask);
1466 resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
1468 return (unsigned long) hose->io_base_virt - _IO_BASE;
1471 static void pcibios_setup_phb_resources(struct pci_controller *hose,
1472 struct list_head *resources)
1474 struct resource *res;
1475 resource_size_t offset;
1478 /* Hookup PHB IO resource */
1479 res = &hose->io_resource;
1482 printk(KERN_WARNING "PCI: I/O resource not set for host"
1483 " bridge %s (domain %d)\n",
1484 hose->dn->full_name, hose->global_number);
1486 offset = pcibios_io_space_offset(hose);
1488 pr_debug("PCI: PHB IO resource = %08llx-%08llx [%lx] off 0x%08llx\n",
1489 (unsigned long long)res->start,
1490 (unsigned long long)res->end,
1491 (unsigned long)res->flags,
1492 (unsigned long long)offset);
1493 pci_add_resource_offset(resources, res, offset);
1496 /* Hookup PHB Memory resources */
1497 for (i = 0; i < 3; ++i) {
1498 res = &hose->mem_resources[i];
1501 printk(KERN_ERR "PCI: Memory resource 0 not set for "
1502 "host bridge %s (domain %d)\n",
1503 hose->dn->full_name, hose->global_number);
1506 offset = hose->mem_offset[i];
1509 pr_debug("PCI: PHB MEM resource %d = %08llx-%08llx [%lx] off 0x%08llx\n", i,
1510 (unsigned long long)res->start,
1511 (unsigned long long)res->end,
1512 (unsigned long)res->flags,
1513 (unsigned long long)offset);
1515 pci_add_resource_offset(resources, res, offset);
1520 * Null PCI config access functions, for the case when we can't
1523 #define NULL_PCI_OP(rw, size, type) \
1525 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1527 return PCIBIOS_DEVICE_NOT_FOUND; \
1531 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1534 return PCIBIOS_DEVICE_NOT_FOUND;
1538 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1541 return PCIBIOS_DEVICE_NOT_FOUND;
1544 static struct pci_ops null_pci_ops =
1546 .read = null_read_config,
1547 .write = null_write_config,
1551 * These functions are used early on before PCI scanning is done
1552 * and all of the pci_dev and pci_bus structures have been created.
1554 static struct pci_bus *
1555 fake_pci_bus(struct pci_controller *hose, int busnr)
1557 static struct pci_bus bus;
1560 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1564 bus.ops = hose? hose->ops: &null_pci_ops;
1568 #define EARLY_PCI_OP(rw, size, type) \
1569 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1570 int devfn, int offset, type value) \
1572 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1573 devfn, offset, value); \
1576 EARLY_PCI_OP(read, byte, u8 *)
1577 EARLY_PCI_OP(read, word, u16 *)
1578 EARLY_PCI_OP(read, dword, u32 *)
1579 EARLY_PCI_OP(write, byte, u8)
1580 EARLY_PCI_OP(write, word, u16)
1581 EARLY_PCI_OP(write, dword, u32)
1583 extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap);
1584 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1587 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1590 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1592 struct pci_controller *hose = bus->sysdata;
1594 return of_node_get(hose->dn);
1598 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1599 * @hose: Pointer to the PCI host controller instance structure
1601 void pcibios_scan_phb(struct pci_controller *hose)
1603 LIST_HEAD(resources);
1604 struct pci_bus *bus;
1605 struct device_node *node = hose->dn;
1608 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node));
1610 /* Get some IO space for the new PHB */
1611 pcibios_setup_phb_io_space(hose);
1613 /* Wire up PHB bus resources */
1614 pcibios_setup_phb_resources(hose, &resources);
1616 hose->busn.start = hose->first_busno;
1617 hose->busn.end = hose->last_busno;
1618 hose->busn.flags = IORESOURCE_BUS;
1619 pci_add_resource(&resources, &hose->busn);
1621 /* Create an empty bus for the toplevel */
1622 bus = pci_create_root_bus(hose->parent, hose->first_busno,
1623 hose->ops, hose, &resources);
1625 pr_err("Failed to create bus for PCI domain %04x\n",
1626 hose->global_number);
1627 pci_free_resource_list(&resources);
1632 /* Get probe mode and perform scan */
1633 mode = PCI_PROBE_NORMAL;
1634 if (node && ppc_md.pci_probe_mode)
1635 mode = ppc_md.pci_probe_mode(bus);
1636 pr_debug(" probe mode: %d\n", mode);
1637 if (mode == PCI_PROBE_DEVTREE)
1638 of_scan_bus(node, bus);
1640 if (mode == PCI_PROBE_NORMAL) {
1641 pci_bus_update_busn_res_end(bus, 255);
1642 hose->last_busno = pci_scan_child_bus(bus);
1643 pci_bus_update_busn_res_end(bus, hose->last_busno);
1646 /* Platform gets a chance to do some global fixups before
1647 * we proceed to resource allocation
1649 if (ppc_md.pcibios_fixup_phb)
1650 ppc_md.pcibios_fixup_phb(hose);
1652 /* Configure PCI Express settings */
1653 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1654 struct pci_bus *child;
1655 list_for_each_entry(child, &bus->children, node)
1656 pcie_bus_configure_settings(child);
1660 static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1662 int i, class = dev->class >> 8;
1663 /* When configured as agent, programing interface = 1 */
1664 int prog_if = dev->class & 0xf;
1666 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1667 class == PCI_CLASS_BRIDGE_OTHER) &&
1668 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1670 (dev->bus->parent == NULL)) {
1671 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1672 dev->resource[i].start = 0;
1673 dev->resource[i].end = 0;
1674 dev->resource[i].flags = 0;
1678 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1679 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1681 static void fixup_vga(struct pci_dev *pdev)
1685 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1686 if ((cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) || !vga_default_device())
1687 vga_set_default_device(pdev);
1690 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1691 PCI_CLASS_DISPLAY_VGA, 8, fixup_vga);