2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/bootmem.h>
25 #include <linux/list.h>
26 #include <linux/syscalls.h>
27 #include <linux/irq.h>
28 #include <linux/vmalloc.h>
30 #include <asm/processor.h>
33 #include <asm/pci-bridge.h>
34 #include <asm/byteorder.h>
35 #include <asm/machdep.h>
36 #include <asm/ppc-pci.h>
37 #include <asm/firmware.h>
40 static DEFINE_SPINLOCK(hose_spinlock);
43 /* XXX kill that some day ... */
44 static int global_phb_number; /* Global phb counter */
46 /* ISA Memory physical address */
47 resource_size_t isa_mem_base;
49 /* Default PCI flags is 0 on ppc32, modified at boot on ppc64 */
50 unsigned int ppc_pci_flags = 0;
53 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
55 void set_pci_dma_ops(struct dma_map_ops *dma_ops)
57 pci_dma_ops = dma_ops;
60 struct dma_map_ops *get_pci_dma_ops(void)
64 EXPORT_SYMBOL(get_pci_dma_ops);
66 int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
68 return dma_set_mask(&dev->dev, mask);
71 int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
75 rc = dma_set_mask(&dev->dev, mask);
76 dev->dev.coherent_dma_mask = dev->dma_mask;
81 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
83 struct pci_controller *phb;
85 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
88 spin_lock(&hose_spinlock);
89 phb->global_number = global_phb_number++;
90 list_add_tail(&phb->list_node, &hose_list);
91 spin_unlock(&hose_spinlock);
93 phb->is_dynamic = mem_init_done;
96 int nid = of_node_to_nid(dev);
98 if (nid < 0 || !node_online(nid))
101 PHB_SET_NODE(phb, nid);
107 void pcibios_free_controller(struct pci_controller *phb)
109 spin_lock(&hose_spinlock);
110 list_del(&phb->list_node);
111 spin_unlock(&hose_spinlock);
117 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
120 return hose->pci_io_size;
122 return hose->io_resource.end - hose->io_resource.start + 1;
126 int pcibios_vaddr_is_ioport(void __iomem *address)
129 struct pci_controller *hose;
130 resource_size_t size;
132 spin_lock(&hose_spinlock);
133 list_for_each_entry(hose, &hose_list, list_node) {
134 size = pcibios_io_size(hose);
135 if (address >= hose->io_base_virt &&
136 address < (hose->io_base_virt + size)) {
141 spin_unlock(&hose_spinlock);
145 unsigned long pci_address_to_pio(phys_addr_t address)
147 struct pci_controller *hose;
148 resource_size_t size;
149 unsigned long ret = ~0;
151 spin_lock(&hose_spinlock);
152 list_for_each_entry(hose, &hose_list, list_node) {
153 size = pcibios_io_size(hose);
154 if (address >= hose->io_base_phys &&
155 address < (hose->io_base_phys + size)) {
157 (unsigned long)hose->io_base_virt - _IO_BASE;
158 ret = base + (address - hose->io_base_phys);
162 spin_unlock(&hose_spinlock);
166 EXPORT_SYMBOL_GPL(pci_address_to_pio);
169 * Return the domain number for this bus.
171 int pci_domain_nr(struct pci_bus *bus)
173 struct pci_controller *hose = pci_bus_to_host(bus);
175 return hose->global_number;
177 EXPORT_SYMBOL(pci_domain_nr);
179 /* This routine is meant to be used early during boot, when the
180 * PCI bus numbers have not yet been assigned, and you need to
181 * issue PCI config cycles to an OF device.
182 * It could also be used to "fix" RTAS config cycles if you want
183 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
186 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
189 struct pci_controller *hose, *tmp;
190 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
191 if (hose->dn == node)
198 static ssize_t pci_show_devspec(struct device *dev,
199 struct device_attribute *attr, char *buf)
201 struct pci_dev *pdev;
202 struct device_node *np;
204 pdev = to_pci_dev (dev);
205 np = pci_device_to_OF_node(pdev);
206 if (np == NULL || np->full_name == NULL)
208 return sprintf(buf, "%s", np->full_name);
210 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
212 /* Add sysfs properties */
213 int pcibios_add_platform_entries(struct pci_dev *pdev)
215 return device_create_file(&pdev->dev, &dev_attr_devspec);
218 char __devinit *pcibios_setup(char *str)
224 * Reads the interrupt pin to determine if interrupt is use by card.
225 * If the interrupt is used, then gets the interrupt line from the
226 * openfirmware and sets it in the pci_dev and pci_config line.
228 int pci_read_irq_line(struct pci_dev *pci_dev)
233 /* The current device-tree that iSeries generates from the HV
234 * PCI informations doesn't contain proper interrupt routing,
235 * and all the fallback would do is print out crap, so we
236 * don't attempt to resolve the interrupts here at all, some
237 * iSeries specific fixup does it.
239 * In the long run, we will hopefully fix the generated device-tree
242 #ifdef CONFIG_PPC_ISERIES
243 if (firmware_has_feature(FW_FEATURE_ISERIES))
247 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
250 memset(&oirq, 0xff, sizeof(oirq));
252 /* Try to get a mapping from the device-tree */
253 if (of_irq_map_pci(pci_dev, &oirq)) {
256 /* If that fails, lets fallback to what is in the config
257 * space and map that through the default controller. We
258 * also set the type to level low since that's what PCI
259 * interrupts are. If your platform does differently, then
260 * either provide a proper interrupt tree or don't use this
263 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
267 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
268 line == 0xff || line == 0) {
271 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
274 virq = irq_create_mapping(NULL, line);
276 set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
278 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
279 oirq.size, oirq.specifier[0], oirq.specifier[1],
280 oirq.controller ? oirq.controller->full_name :
283 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
287 pr_debug(" Failed to map !\n");
291 pr_debug(" Mapped to linux irq %d\n", virq);
297 EXPORT_SYMBOL(pci_read_irq_line);
300 * Platform support for /proc/bus/pci/X/Y mmap()s,
301 * modelled on the sparc64 implementation by Dave Miller.
306 * Adjust vm_pgoff of VMA such that it is the physical page offset
307 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
309 * Basically, the user finds the base address for his device which he wishes
310 * to mmap. They read the 32-bit value from the config space base register,
311 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
312 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
314 * Returns negative error code on failure, zero on success.
316 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
317 resource_size_t *offset,
318 enum pci_mmap_state mmap_state)
320 struct pci_controller *hose = pci_bus_to_host(dev->bus);
321 unsigned long io_offset = 0;
325 return NULL; /* should never happen */
327 /* If memory, add on the PCI bridge address offset */
328 if (mmap_state == pci_mmap_mem) {
329 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
330 *offset += hose->pci_mem_offset;
332 res_bit = IORESOURCE_MEM;
334 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
335 *offset += io_offset;
336 res_bit = IORESOURCE_IO;
340 * Check that the offset requested corresponds to one of the
341 * resources of the device.
343 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
344 struct resource *rp = &dev->resource[i];
345 int flags = rp->flags;
347 /* treat ROM as memory (should be already) */
348 if (i == PCI_ROM_RESOURCE)
349 flags |= IORESOURCE_MEM;
351 /* Active and same type? */
352 if ((flags & res_bit) == 0)
355 /* In the range of this resource? */
356 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
359 /* found it! construct the final physical address */
360 if (mmap_state == pci_mmap_io)
361 *offset += hose->io_base_phys - io_offset;
369 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
372 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
374 enum pci_mmap_state mmap_state,
377 unsigned long prot = pgprot_val(protection);
379 /* Write combine is always 0 on non-memory space mappings. On
380 * memory space, if the user didn't pass 1, we check for a
381 * "prefetchable" resource. This is a bit hackish, but we use
382 * this to workaround the inability of /sysfs to provide a write
385 if (mmap_state != pci_mmap_mem)
387 else if (write_combine == 0) {
388 if (rp->flags & IORESOURCE_PREFETCH)
392 /* XXX would be nice to have a way to ask for write-through */
394 return pgprot_noncached_wc(prot);
396 return pgprot_noncached(prot);
400 * This one is used by /dev/mem and fbdev who have no clue about the
401 * PCI device, it tries to find the PCI device first and calls the
404 pgprot_t pci_phys_mem_access_prot(struct file *file,
409 struct pci_dev *pdev = NULL;
410 struct resource *found = NULL;
411 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
414 if (page_is_ram(pfn))
417 prot = pgprot_noncached(prot);
418 for_each_pci_dev(pdev) {
419 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
420 struct resource *rp = &pdev->resource[i];
421 int flags = rp->flags;
423 /* Active and same type? */
424 if ((flags & IORESOURCE_MEM) == 0)
426 /* In the range of this resource? */
427 if (offset < (rp->start & PAGE_MASK) ||
437 if (found->flags & IORESOURCE_PREFETCH)
438 prot = pgprot_noncached_wc(prot);
442 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
443 (unsigned long long)offset, pgprot_val(prot));
450 * Perform the actual remap of the pages for a PCI device mapping, as
451 * appropriate for this architecture. The region in the process to map
452 * is described by vm_start and vm_end members of VMA, the base physical
453 * address is found in vm_pgoff.
454 * The pci device structure is provided so that architectures may make mapping
455 * decisions on a per-device or per-bus basis.
457 * Returns a negative error code on failure, zero on success.
459 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
460 enum pci_mmap_state mmap_state, int write_combine)
462 resource_size_t offset =
463 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
467 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
471 vma->vm_pgoff = offset >> PAGE_SHIFT;
472 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
474 mmap_state, write_combine);
476 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
477 vma->vm_end - vma->vm_start, vma->vm_page_prot);
482 /* This provides legacy IO read access on a bus */
483 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
485 unsigned long offset;
486 struct pci_controller *hose = pci_bus_to_host(bus);
487 struct resource *rp = &hose->io_resource;
490 /* Check if port can be supported by that bus. We only check
491 * the ranges of the PHB though, not the bus itself as the rules
492 * for forwarding legacy cycles down bridges are not our problem
493 * here. So if the host bridge supports it, we do it.
495 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
498 if (!(rp->flags & IORESOURCE_IO))
500 if (offset < rp->start || (offset + size) > rp->end)
502 addr = hose->io_base_virt + port;
506 *((u8 *)val) = in_8(addr);
511 *((u16 *)val) = in_le16(addr);
516 *((u32 *)val) = in_le32(addr);
522 /* This provides legacy IO write access on a bus */
523 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
525 unsigned long offset;
526 struct pci_controller *hose = pci_bus_to_host(bus);
527 struct resource *rp = &hose->io_resource;
530 /* Check if port can be supported by that bus. We only check
531 * the ranges of the PHB though, not the bus itself as the rules
532 * for forwarding legacy cycles down bridges are not our problem
533 * here. So if the host bridge supports it, we do it.
535 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
538 if (!(rp->flags & IORESOURCE_IO))
540 if (offset < rp->start || (offset + size) > rp->end)
542 addr = hose->io_base_virt + port;
544 /* WARNING: The generic code is idiotic. It gets passed a pointer
545 * to what can be a 1, 2 or 4 byte quantity and always reads that
546 * as a u32, which means that we have to correct the location of
547 * the data read within those 32 bits for size 1 and 2
551 out_8(addr, val >> 24);
556 out_le16(addr, val >> 16);
567 /* This provides legacy IO or memory mmap access on a bus */
568 int pci_mmap_legacy_page_range(struct pci_bus *bus,
569 struct vm_area_struct *vma,
570 enum pci_mmap_state mmap_state)
572 struct pci_controller *hose = pci_bus_to_host(bus);
573 resource_size_t offset =
574 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
575 resource_size_t size = vma->vm_end - vma->vm_start;
578 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
579 pci_domain_nr(bus), bus->number,
580 mmap_state == pci_mmap_mem ? "MEM" : "IO",
581 (unsigned long long)offset,
582 (unsigned long long)(offset + size - 1));
584 if (mmap_state == pci_mmap_mem) {
587 * Because X is lame and can fail starting if it gets an error trying
588 * to mmap legacy_mem (instead of just moving on without legacy memory
589 * access) we fake it here by giving it anonymous memory, effectively
590 * behaving just like /dev/zero
592 if ((offset + size) > hose->isa_mem_size) {
594 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
595 current->comm, current->pid, pci_domain_nr(bus), bus->number);
596 if (vma->vm_flags & VM_SHARED)
597 return shmem_zero_setup(vma);
600 offset += hose->isa_mem_phys;
602 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
603 unsigned long roffset = offset + io_offset;
604 rp = &hose->io_resource;
605 if (!(rp->flags & IORESOURCE_IO))
607 if (roffset < rp->start || (roffset + size) > rp->end)
609 offset += hose->io_base_phys;
611 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
613 vma->vm_pgoff = offset >> PAGE_SHIFT;
614 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
615 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
616 vma->vm_end - vma->vm_start,
620 void pci_resource_to_user(const struct pci_dev *dev, int bar,
621 const struct resource *rsrc,
622 resource_size_t *start, resource_size_t *end)
624 struct pci_controller *hose = pci_bus_to_host(dev->bus);
625 resource_size_t offset = 0;
630 if (rsrc->flags & IORESOURCE_IO)
631 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
633 /* We pass a fully fixed up address to userland for MMIO instead of
634 * a BAR value because X is lame and expects to be able to use that
635 * to pass to /dev/mem !
637 * That means that we'll have potentially 64 bits values where some
638 * userland apps only expect 32 (like X itself since it thinks only
639 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
642 * Hopefully, the sysfs insterface is immune to that gunk. Once X
643 * has been fixed (and the fix spread enough), we can re-enable the
644 * 2 lines below and pass down a BAR value to userland. In that case
645 * we'll also have to re-enable the matching code in
646 * __pci_mmap_make_offset().
651 else if (rsrc->flags & IORESOURCE_MEM)
652 offset = hose->pci_mem_offset;
655 *start = rsrc->start - offset;
656 *end = rsrc->end - offset;
660 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
661 * @hose: newly allocated pci_controller to be setup
662 * @dev: device node of the host bridge
663 * @primary: set if primary bus (32 bits only, soon to be deprecated)
665 * This function will parse the "ranges" property of a PCI host bridge device
666 * node and setup the resource mapping of a pci controller based on its
669 * Life would be boring if it wasn't for a few issues that we have to deal
672 * - We can only cope with one IO space range and up to 3 Memory space
673 * ranges. However, some machines (thanks Apple !) tend to split their
674 * space into lots of small contiguous ranges. So we have to coalesce.
676 * - We can only cope with all memory ranges having the same offset
677 * between CPU addresses and PCI addresses. Unfortunately, some bridges
678 * are setup for a large 1:1 mapping along with a small "window" which
679 * maps PCI address 0 to some arbitrary high address of the CPU space in
680 * order to give access to the ISA memory hole.
681 * The way out of here that I've chosen for now is to always set the
682 * offset based on the first resource found, then override it if we
683 * have a different offset and the previous was set by an ISA hole.
685 * - Some busses have IO space not starting at 0, which causes trouble with
686 * the way we do our IO resource renumbering. The code somewhat deals with
687 * it for 64 bits but I would expect problems on 32 bits.
689 * - Some 32 bits platforms such as 4xx can have physical space larger than
690 * 32 bits so we need to use 64 bits values for the parsing
692 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
693 struct device_node *dev,
698 int pna = of_n_addr_cells(dev);
700 int memno = 0, isa_hole = -1;
702 unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size;
703 unsigned long long isa_mb = 0;
704 struct resource *res;
706 printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
707 dev->full_name, primary ? "(primary)" : "");
709 /* Get ranges property */
710 ranges = of_get_property(dev, "ranges", &rlen);
715 while ((rlen -= np * 4) >= 0) {
716 /* Read next ranges element */
717 pci_space = ranges[0];
718 pci_addr = of_read_number(ranges + 1, 2);
719 cpu_addr = of_translate_address(dev, ranges + 3);
720 size = of_read_number(ranges + pna + 3, 2);
723 /* If we failed translation or got a zero-sized region
724 * (some FW try to feed us with non sensical zero sized regions
725 * such as power3 which look like some kind of attempt at exposing
726 * the VGA memory hole)
728 if (cpu_addr == OF_BAD_ADDR || size == 0)
731 /* Now consume following elements while they are contiguous */
732 for (; rlen >= np * sizeof(u32);
733 ranges += np, rlen -= np * 4) {
734 if (ranges[0] != pci_space)
736 pci_next = of_read_number(ranges + 1, 2);
737 cpu_next = of_translate_address(dev, ranges + 3);
738 if (pci_next != pci_addr + size ||
739 cpu_next != cpu_addr + size)
741 size += of_read_number(ranges + pna + 3, 2);
744 /* Act based on address space type */
746 switch ((pci_space >> 24) & 0x3) {
747 case 1: /* PCI IO space */
749 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
750 cpu_addr, cpu_addr + size - 1, pci_addr);
752 /* We support only one IO range */
753 if (hose->pci_io_size) {
755 " \\--> Skipped (too many) !\n");
759 /* On 32 bits, limit I/O space to 16MB */
760 if (size > 0x01000000)
763 /* 32 bits needs to map IOs here */
764 hose->io_base_virt = ioremap(cpu_addr, size);
766 /* Expect trouble if pci_addr is not 0 */
769 (unsigned long)hose->io_base_virt;
770 #endif /* CONFIG_PPC32 */
771 /* pci_io_size and io_base_phys always represent IO
772 * space starting at 0 so we factor in pci_addr
774 hose->pci_io_size = pci_addr + size;
775 hose->io_base_phys = cpu_addr - pci_addr;
778 res = &hose->io_resource;
779 res->flags = IORESOURCE_IO;
780 res->start = pci_addr;
782 case 2: /* PCI Memory space */
783 case 3: /* PCI 64 bits Memory space */
785 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
786 cpu_addr, cpu_addr + size - 1, pci_addr,
787 (pci_space & 0x40000000) ? "Prefetch" : "");
789 /* We support only 3 memory ranges */
792 " \\--> Skipped (too many) !\n");
795 /* Handles ISA memory hole space here */
799 if (primary || isa_mem_base == 0)
800 isa_mem_base = cpu_addr;
801 hose->isa_mem_phys = cpu_addr;
802 hose->isa_mem_size = size;
805 /* We get the PCI/Mem offset from the first range or
806 * the, current one if the offset came from an ISA
807 * hole. If they don't match, bugger.
810 (isa_hole >= 0 && pci_addr != 0 &&
811 hose->pci_mem_offset == isa_mb))
812 hose->pci_mem_offset = cpu_addr - pci_addr;
813 else if (pci_addr != 0 &&
814 hose->pci_mem_offset != cpu_addr - pci_addr) {
816 " \\--> Skipped (offset mismatch) !\n");
821 res = &hose->mem_resources[memno++];
822 res->flags = IORESOURCE_MEM;
823 if (pci_space & 0x40000000)
824 res->flags |= IORESOURCE_PREFETCH;
825 res->start = cpu_addr;
829 res->name = dev->full_name;
830 res->end = res->start + size - 1;
837 /* If there's an ISA hole and the pci_mem_offset is -not- matching
838 * the ISA hole offset, then we need to remove the ISA hole from
839 * the resource list for that brige
841 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
842 unsigned int next = isa_hole + 1;
843 printk(KERN_INFO " Removing ISA hole at 0x%016llx\n", isa_mb);
845 memmove(&hose->mem_resources[isa_hole],
846 &hose->mem_resources[next],
847 sizeof(struct resource) * (memno - next));
848 hose->mem_resources[--memno].flags = 0;
852 /* Decide whether to display the domain number in /proc */
853 int pci_proc_domain(struct pci_bus *bus)
855 struct pci_controller *hose = pci_bus_to_host(bus);
857 if (!(ppc_pci_flags & PPC_PCI_ENABLE_PROC_DOMAINS))
859 if (ppc_pci_flags & PPC_PCI_COMPAT_DOMAIN_0)
860 return hose->global_number != 0;
864 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
865 struct resource *res)
867 resource_size_t offset = 0, mask = (resource_size_t)-1;
868 struct pci_controller *hose = pci_bus_to_host(dev->bus);
872 if (res->flags & IORESOURCE_IO) {
873 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
875 } else if (res->flags & IORESOURCE_MEM)
876 offset = hose->pci_mem_offset;
878 region->start = (res->start - offset) & mask;
879 region->end = (res->end - offset) & mask;
881 EXPORT_SYMBOL(pcibios_resource_to_bus);
883 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
884 struct pci_bus_region *region)
886 resource_size_t offset = 0, mask = (resource_size_t)-1;
887 struct pci_controller *hose = pci_bus_to_host(dev->bus);
891 if (res->flags & IORESOURCE_IO) {
892 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
894 } else if (res->flags & IORESOURCE_MEM)
895 offset = hose->pci_mem_offset;
896 res->start = (region->start + offset) & mask;
897 res->end = (region->end + offset) & mask;
899 EXPORT_SYMBOL(pcibios_bus_to_resource);
901 /* Fixup a bus resource into a linux resource */
902 static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
904 struct pci_controller *hose = pci_bus_to_host(dev->bus);
905 resource_size_t offset = 0, mask = (resource_size_t)-1;
907 if (res->flags & IORESOURCE_IO) {
908 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
910 } else if (res->flags & IORESOURCE_MEM)
911 offset = hose->pci_mem_offset;
913 res->start = (res->start + offset) & mask;
914 res->end = (res->end + offset) & mask;
918 /* This header fixup will do the resource fixup for all devices as they are
919 * probed, but not for bridge ranges
921 static void __devinit pcibios_fixup_resources(struct pci_dev *dev)
923 struct pci_controller *hose = pci_bus_to_host(dev->bus);
927 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
931 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
932 struct resource *res = dev->resource + i;
935 /* On platforms that have PPC_PCI_PROBE_ONLY set, we don't
936 * consider 0 as an unassigned BAR value. It's technically
937 * a valid value, but linux doesn't like it... so when we can
938 * re-assign things, we do so, but if we can't, we keep it
939 * around and hope for the best...
941 if (res->start == 0 && !(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) {
942 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] is unassigned\n",
944 (unsigned long long)res->start,
945 (unsigned long long)res->end,
946 (unsigned int)res->flags);
947 res->end -= res->start;
949 res->flags |= IORESOURCE_UNSET;
953 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n",
955 (unsigned long long)res->start,\
956 (unsigned long long)res->end,
957 (unsigned int)res->flags);
959 fixup_resource(res, dev);
961 pr_debug("PCI:%s %016llx-%016llx\n",
963 (unsigned long long)res->start,
964 (unsigned long long)res->end);
967 /* Call machine specific resource fixup */
968 if (ppc_md.pcibios_fixup_resources)
969 ppc_md.pcibios_fixup_resources(dev);
971 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
973 /* This function tries to figure out if a bridge resource has been initialized
974 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
975 * things go more smoothly when it gets it right. It should covers cases such
976 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
978 static int __devinit pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
979 struct resource *res)
981 struct pci_controller *hose = pci_bus_to_host(bus);
982 struct pci_dev *dev = bus->self;
983 resource_size_t offset;
987 /* We don't do anything if PCI_PROBE_ONLY is set */
988 if (ppc_pci_flags & PPC_PCI_PROBE_ONLY)
991 /* Job is a bit different between memory and IO */
992 if (res->flags & IORESOURCE_MEM) {
993 /* If the BAR is non-0 (res != pci_mem_offset) then it's probably been
994 * initialized by somebody
996 if (res->start != hose->pci_mem_offset)
999 /* The BAR is 0, let's check if memory decoding is enabled on
1000 * the bridge. If not, we consider it unassigned
1002 pci_read_config_word(dev, PCI_COMMAND, &command);
1003 if ((command & PCI_COMMAND_MEMORY) == 0)
1006 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
1007 * resources covers that starting address (0 then it's good enough for
1010 for (i = 0; i < 3; i++) {
1011 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
1012 hose->mem_resources[i].start == hose->pci_mem_offset)
1016 /* Well, it starts at 0 and we know it will collide so we may as
1017 * well consider it as unassigned. That covers the Apple case.
1021 /* If the BAR is non-0, then we consider it assigned */
1022 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1023 if (((res->start - offset) & 0xfffffffful) != 0)
1026 /* Here, we are a bit different than memory as typically IO space
1027 * starting at low addresses -is- valid. What we do instead if that
1028 * we consider as unassigned anything that doesn't have IO enabled
1029 * in the PCI command register, and that's it.
1031 pci_read_config_word(dev, PCI_COMMAND, &command);
1032 if (command & PCI_COMMAND_IO)
1035 /* It's starting at 0 and IO is disabled in the bridge, consider
1042 /* Fixup resources of a PCI<->PCI bridge */
1043 static void __devinit pcibios_fixup_bridge(struct pci_bus *bus)
1045 struct resource *res;
1048 struct pci_dev *dev = bus->self;
1050 pci_bus_for_each_resource(bus, res, i) {
1051 if (!res || !res->flags)
1053 if (i >= 3 && bus->self->transparent)
1056 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
1058 (unsigned long long)res->start,\
1059 (unsigned long long)res->end,
1060 (unsigned int)res->flags);
1063 fixup_resource(res, dev);
1065 /* Try to detect uninitialized P2P bridge resources,
1066 * and clear them out so they get re-assigned later
1068 if (pcibios_uninitialized_bridge_resource(bus, res)) {
1070 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
1073 pr_debug("PCI:%s %016llx-%016llx\n",
1075 (unsigned long long)res->start,
1076 (unsigned long long)res->end);
1081 void __devinit pcibios_setup_bus_self(struct pci_bus *bus)
1083 /* Fix up the bus resources for P2P bridges */
1084 if (bus->self != NULL)
1085 pcibios_fixup_bridge(bus);
1087 /* Platform specific bus fixups. This is currently only used
1088 * by fsl_pci and I'm hoping to get rid of it at some point
1090 if (ppc_md.pcibios_fixup_bus)
1091 ppc_md.pcibios_fixup_bus(bus);
1093 /* Setup bus DMA mappings */
1094 if (ppc_md.pci_dma_bus_setup)
1095 ppc_md.pci_dma_bus_setup(bus);
1098 void __devinit pcibios_setup_bus_devices(struct pci_bus *bus)
1100 struct pci_dev *dev;
1102 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1103 bus->number, bus->self ? pci_name(bus->self) : "PHB");
1105 list_for_each_entry(dev, &bus->devices, bus_list) {
1106 struct dev_archdata *sd = &dev->dev.archdata;
1108 /* Cardbus can call us to add new devices to a bus, so ignore
1109 * those who are already fully discovered
1114 /* Setup OF node pointer in archdata */
1115 sd->of_node = pci_device_to_OF_node(dev);
1117 /* Fixup NUMA node as it may not be setup yet by the generic
1118 * code and is needed by the DMA init
1120 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
1122 /* Hook up default DMA ops */
1123 sd->dma_ops = pci_dma_ops;
1124 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
1126 /* Additional platform DMA/iommu setup */
1127 if (ppc_md.pci_dma_dev_setup)
1128 ppc_md.pci_dma_dev_setup(dev);
1130 /* Read default IRQs and fixup if necessary */
1131 pci_read_irq_line(dev);
1132 if (ppc_md.pci_irq_fixup)
1133 ppc_md.pci_irq_fixup(dev);
1137 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
1139 /* When called from the generic PCI probe, read PCI<->PCI bridge
1140 * bases. This is -not- called when generating the PCI tree from
1141 * the OF device-tree.
1143 if (bus->self != NULL)
1144 pci_read_bridge_bases(bus);
1146 /* Now fixup the bus bus */
1147 pcibios_setup_bus_self(bus);
1149 /* Now fixup devices on that bus */
1150 pcibios_setup_bus_devices(bus);
1152 EXPORT_SYMBOL(pcibios_fixup_bus);
1154 void __devinit pci_fixup_cardbus(struct pci_bus *bus)
1156 /* Now fixup devices on that bus */
1157 pcibios_setup_bus_devices(bus);
1161 static int skip_isa_ioresource_align(struct pci_dev *dev)
1163 if ((ppc_pci_flags & PPC_PCI_CAN_SKIP_ISA_ALIGN) &&
1164 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1170 * We need to avoid collisions with `mirrored' VGA ports
1171 * and other strange ISA hardware, so we always want the
1172 * addresses to be allocated in the 0x000-0x0ff region
1175 * Why? Because some silly external IO cards only decode
1176 * the low 10 bits of the IO address. The 0x00-0xff region
1177 * is reserved for motherboard devices that decode all 16
1178 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1179 * but we want to try to avoid allocating at 0x2900-0x2bff
1180 * which might have be mirrored at 0x0100-0x03ff..
1182 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1183 resource_size_t size, resource_size_t align)
1185 struct pci_dev *dev = data;
1186 resource_size_t start = res->start;
1188 if (res->flags & IORESOURCE_IO) {
1189 if (skip_isa_ioresource_align(dev))
1192 start = (start + 0x3ff) & ~0x3ff;
1197 EXPORT_SYMBOL(pcibios_align_resource);
1200 * Reparent resource children of pr that conflict with res
1201 * under res, and make res replace those children.
1203 static int reparent_resources(struct resource *parent,
1204 struct resource *res)
1206 struct resource *p, **pp;
1207 struct resource **firstpp = NULL;
1209 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1210 if (p->end < res->start)
1212 if (res->end < p->start)
1214 if (p->start < res->start || p->end > res->end)
1215 return -1; /* not completely contained */
1216 if (firstpp == NULL)
1219 if (firstpp == NULL)
1220 return -1; /* didn't find any conflicting entries? */
1221 res->parent = parent;
1222 res->child = *firstpp;
1226 for (p = res->child; p != NULL; p = p->sibling) {
1228 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1230 (unsigned long long)p->start,
1231 (unsigned long long)p->end, res->name);
1237 * Handle resources of PCI devices. If the world were perfect, we could
1238 * just allocate all the resource regions and do nothing more. It isn't.
1239 * On the other hand, we cannot just re-allocate all devices, as it would
1240 * require us to know lots of host bridge internals. So we attempt to
1241 * keep as much of the original configuration as possible, but tweak it
1242 * when it's found to be wrong.
1244 * Known BIOS problems we have to work around:
1245 * - I/O or memory regions not configured
1246 * - regions configured, but not enabled in the command register
1247 * - bogus I/O addresses above 64K used
1248 * - expansion ROMs left enabled (this may sound harmless, but given
1249 * the fact the PCI specs explicitly allow address decoders to be
1250 * shared between expansion ROMs and other resource regions, it's
1251 * at least dangerous)
1254 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1255 * This gives us fixed barriers on where we can allocate.
1256 * (2) Allocate resources for all enabled devices. If there is
1257 * a collision, just mark the resource as unallocated. Also
1258 * disable expansion ROMs during this step.
1259 * (3) Try to allocate resources for disabled devices. If the
1260 * resources were assigned correctly, everything goes well,
1261 * if they weren't, they won't disturb allocation of other
1263 * (4) Assign new addresses to resources which were either
1264 * not configured at all or misconfigured. If explicitly
1265 * requested by the user, configure expansion ROM address
1269 void pcibios_allocate_bus_resources(struct pci_bus *bus)
1273 struct resource *res, *pr;
1275 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1276 pci_domain_nr(bus), bus->number);
1278 pci_bus_for_each_resource(bus, res, i) {
1279 if (!res || !res->flags || res->start > res->end || res->parent)
1281 if (bus->parent == NULL)
1282 pr = (res->flags & IORESOURCE_IO) ?
1283 &ioport_resource : &iomem_resource;
1285 /* Don't bother with non-root busses when
1286 * re-assigning all resources. We clear the
1287 * resource flags as if they were colliding
1288 * and as such ensure proper re-allocation
1291 if (ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC)
1292 goto clear_resource;
1293 pr = pci_find_parent_resource(bus->self, res);
1295 /* this happens when the generic PCI
1296 * code (wrongly) decides that this
1297 * bridge is transparent -- paulus
1303 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1304 "[0x%x], parent %p (%s)\n",
1305 bus->self ? pci_name(bus->self) : "PHB",
1307 (unsigned long long)res->start,
1308 (unsigned long long)res->end,
1309 (unsigned int)res->flags,
1310 pr, (pr && pr->name) ? pr->name : "nil");
1312 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1313 if (request_resource(pr, res) == 0)
1316 * Must be a conflict with an existing entry.
1317 * Move that entry (or entries) under the
1318 * bridge resource and try again.
1320 if (reparent_resources(pr, res) == 0)
1323 printk(KERN_WARNING "PCI: Cannot allocate resource region "
1324 "%d of PCI bridge %d, will remap\n", i, bus->number);
1329 list_for_each_entry(b, &bus->children, node)
1330 pcibios_allocate_bus_resources(b);
1333 static inline void __devinit alloc_resource(struct pci_dev *dev, int idx)
1335 struct resource *pr, *r = &dev->resource[idx];
1337 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1339 (unsigned long long)r->start,
1340 (unsigned long long)r->end,
1341 (unsigned int)r->flags);
1343 pr = pci_find_parent_resource(dev, r);
1344 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1345 request_resource(pr, r) < 0) {
1346 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1347 " of device %s, will remap\n", idx, pci_name(dev));
1349 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1351 (unsigned long long)pr->start,
1352 (unsigned long long)pr->end,
1353 (unsigned int)pr->flags);
1354 /* We'll assign a new address later */
1355 r->flags |= IORESOURCE_UNSET;
1361 static void __init pcibios_allocate_resources(int pass)
1363 struct pci_dev *dev = NULL;
1368 for_each_pci_dev(dev) {
1369 pci_read_config_word(dev, PCI_COMMAND, &command);
1370 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1371 r = &dev->resource[idx];
1372 if (r->parent) /* Already allocated */
1374 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1375 continue; /* Not assigned at all */
1376 /* We only allocate ROMs on pass 1 just in case they
1377 * have been screwed up by firmware
1379 if (idx == PCI_ROM_RESOURCE )
1381 if (r->flags & IORESOURCE_IO)
1382 disabled = !(command & PCI_COMMAND_IO);
1384 disabled = !(command & PCI_COMMAND_MEMORY);
1385 if (pass == disabled)
1386 alloc_resource(dev, idx);
1390 r = &dev->resource[PCI_ROM_RESOURCE];
1392 /* Turn the ROM off, leave the resource region,
1393 * but keep it unregistered.
1396 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1397 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1398 pr_debug("PCI: Switching off ROM of %s\n",
1400 r->flags &= ~IORESOURCE_ROM_ENABLE;
1401 pci_write_config_dword(dev, dev->rom_base_reg,
1402 reg & ~PCI_ROM_ADDRESS_ENABLE);
1408 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1410 struct pci_controller *hose = pci_bus_to_host(bus);
1411 resource_size_t offset;
1412 struct resource *res, *pres;
1415 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1418 if (!(hose->io_resource.flags & IORESOURCE_IO))
1420 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1421 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1422 BUG_ON(res == NULL);
1423 res->name = "Legacy IO";
1424 res->flags = IORESOURCE_IO;
1425 res->start = offset;
1426 res->end = (offset + 0xfff) & 0xfffffffful;
1427 pr_debug("Candidate legacy IO: %pR\n", res);
1428 if (request_resource(&hose->io_resource, res)) {
1430 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1431 pci_domain_nr(bus), bus->number, res);
1436 /* Check for memory */
1437 offset = hose->pci_mem_offset;
1438 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
1439 for (i = 0; i < 3; i++) {
1440 pres = &hose->mem_resources[i];
1441 if (!(pres->flags & IORESOURCE_MEM))
1443 pr_debug("hose mem res: %pR\n", pres);
1444 if ((pres->start - offset) <= 0xa0000 &&
1445 (pres->end - offset) >= 0xbffff)
1450 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1451 BUG_ON(res == NULL);
1452 res->name = "Legacy VGA memory";
1453 res->flags = IORESOURCE_MEM;
1454 res->start = 0xa0000 + offset;
1455 res->end = 0xbffff + offset;
1456 pr_debug("Candidate VGA memory: %pR\n", res);
1457 if (request_resource(pres, res)) {
1459 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1460 pci_domain_nr(bus), bus->number, res);
1465 void __init pcibios_resource_survey(void)
1469 /* Allocate and assign resources. If we re-assign everything, then
1470 * we skip the allocate phase
1472 list_for_each_entry(b, &pci_root_buses, node)
1473 pcibios_allocate_bus_resources(b);
1475 if (!(ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC)) {
1476 pcibios_allocate_resources(0);
1477 pcibios_allocate_resources(1);
1480 /* Before we start assigning unassigned resource, we try to reserve
1481 * the low IO area and the VGA memory area if they intersect the
1482 * bus available resources to avoid allocating things on top of them
1484 if (!(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) {
1485 list_for_each_entry(b, &pci_root_buses, node)
1486 pcibios_reserve_legacy_regions(b);
1489 /* Now, if the platform didn't decide to blindly trust the firmware,
1490 * we proceed to assigning things that were left unassigned
1492 if (!(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) {
1493 pr_debug("PCI: Assigning unassigned resources...\n");
1494 pci_assign_unassigned_resources();
1497 /* Call machine dependent fixup */
1498 if (ppc_md.pcibios_fixup)
1499 ppc_md.pcibios_fixup();
1502 #ifdef CONFIG_HOTPLUG
1504 /* This is used by the PCI hotplug driver to allocate resource
1505 * of newly plugged busses. We can try to consolidate with the
1506 * rest of the code later, for now, keep it as-is as our main
1507 * resource allocation function doesn't deal with sub-trees yet.
1509 void pcibios_claim_one_bus(struct pci_bus *bus)
1511 struct pci_dev *dev;
1512 struct pci_bus *child_bus;
1514 list_for_each_entry(dev, &bus->devices, bus_list) {
1517 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1518 struct resource *r = &dev->resource[i];
1520 if (r->parent || !r->start || !r->flags)
1523 pr_debug("PCI: Claiming %s: "
1524 "Resource %d: %016llx..%016llx [%x]\n",
1526 (unsigned long long)r->start,
1527 (unsigned long long)r->end,
1528 (unsigned int)r->flags);
1530 pci_claim_resource(dev, i);
1534 list_for_each_entry(child_bus, &bus->children, node)
1535 pcibios_claim_one_bus(child_bus);
1539 /* pcibios_finish_adding_to_bus
1541 * This is to be called by the hotplug code after devices have been
1542 * added to a bus, this include calling it for a PHB that is just
1545 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1547 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1548 pci_domain_nr(bus), bus->number);
1550 /* Allocate bus and devices resources */
1551 pcibios_allocate_bus_resources(bus);
1552 pcibios_claim_one_bus(bus);
1554 /* Add new devices to global lists. Register in proc, sysfs. */
1555 pci_bus_add_devices(bus);
1558 eeh_add_device_tree_late(bus);
1560 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1562 #endif /* CONFIG_HOTPLUG */
1564 int pcibios_enable_device(struct pci_dev *dev, int mask)
1566 if (ppc_md.pcibios_enable_device_hook)
1567 if (ppc_md.pcibios_enable_device_hook(dev))
1570 return pci_enable_resources(dev, mask);
1573 void __devinit pcibios_setup_phb_resources(struct pci_controller *hose)
1575 struct pci_bus *bus = hose->bus;
1576 struct resource *res;
1579 /* Hookup PHB IO resource */
1580 bus->resource[0] = res = &hose->io_resource;
1583 printk(KERN_WARNING "PCI: I/O resource not set for host"
1584 " bridge %s (domain %d)\n",
1585 hose->dn->full_name, hose->global_number);
1587 /* Workaround for lack of IO resource only on 32-bit */
1588 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
1589 res->end = res->start + IO_SPACE_LIMIT;
1590 res->flags = IORESOURCE_IO;
1591 #endif /* CONFIG_PPC32 */
1594 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1595 (unsigned long long)res->start,
1596 (unsigned long long)res->end,
1597 (unsigned long)res->flags);
1599 /* Hookup PHB Memory resources */
1600 for (i = 0; i < 3; ++i) {
1601 res = &hose->mem_resources[i];
1605 printk(KERN_ERR "PCI: Memory resource 0 not set for "
1606 "host bridge %s (domain %d)\n",
1607 hose->dn->full_name, hose->global_number);
1609 /* Workaround for lack of MEM resource only on 32-bit */
1610 res->start = hose->pci_mem_offset;
1611 res->end = (resource_size_t)-1LL;
1612 res->flags = IORESOURCE_MEM;
1613 #endif /* CONFIG_PPC32 */
1615 bus->resource[i+1] = res;
1617 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", i,
1618 (unsigned long long)res->start,
1619 (unsigned long long)res->end,
1620 (unsigned long)res->flags);
1623 pr_debug("PCI: PHB MEM offset = %016llx\n",
1624 (unsigned long long)hose->pci_mem_offset);
1625 pr_debug("PCI: PHB IO offset = %08lx\n",
1626 (unsigned long)hose->io_base_virt - _IO_BASE);
1631 * Null PCI config access functions, for the case when we can't
1634 #define NULL_PCI_OP(rw, size, type) \
1636 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1638 return PCIBIOS_DEVICE_NOT_FOUND; \
1642 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1645 return PCIBIOS_DEVICE_NOT_FOUND;
1649 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1652 return PCIBIOS_DEVICE_NOT_FOUND;
1655 static struct pci_ops null_pci_ops =
1657 .read = null_read_config,
1658 .write = null_write_config,
1662 * These functions are used early on before PCI scanning is done
1663 * and all of the pci_dev and pci_bus structures have been created.
1665 static struct pci_bus *
1666 fake_pci_bus(struct pci_controller *hose, int busnr)
1668 static struct pci_bus bus;
1671 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1675 bus.ops = hose? hose->ops: &null_pci_ops;
1679 #define EARLY_PCI_OP(rw, size, type) \
1680 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1681 int devfn, int offset, type value) \
1683 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1684 devfn, offset, value); \
1687 EARLY_PCI_OP(read, byte, u8 *)
1688 EARLY_PCI_OP(read, word, u16 *)
1689 EARLY_PCI_OP(read, dword, u32 *)
1690 EARLY_PCI_OP(write, byte, u8)
1691 EARLY_PCI_OP(write, word, u16)
1692 EARLY_PCI_OP(write, dword, u32)
1694 extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap);
1695 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1698 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1702 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1703 * @hose: Pointer to the PCI host controller instance structure
1704 * @sysdata: value to use for sysdata pointer. ppc32 and ppc64 differ here
1706 * Note: the 'data' pointer is a temporary measure. As 32 and 64 bit
1707 * pci code gets merged, this parameter should become unnecessary because
1708 * both will use the same value.
1710 void __devinit pcibios_scan_phb(struct pci_controller *hose, void *sysdata)
1712 struct pci_bus *bus;
1713 struct device_node *node = hose->dn;
1716 pr_debug("PCI: Scanning PHB %s\n",
1717 node ? node->full_name : "<NO NAME>");
1719 /* Create an empty bus for the toplevel */
1720 bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops,
1723 pr_err("Failed to create bus for PCI domain %04x\n",
1724 hose->global_number);
1727 bus->secondary = hose->first_busno;
1730 /* Get some IO space for the new PHB */
1731 pcibios_setup_phb_io_space(hose);
1733 /* Wire up PHB bus resources */
1734 pcibios_setup_phb_resources(hose);
1736 /* Get probe mode and perform scan */
1737 mode = PCI_PROBE_NORMAL;
1738 if (node && ppc_md.pci_probe_mode)
1739 mode = ppc_md.pci_probe_mode(bus);
1740 pr_debug(" probe mode: %d\n", mode);
1741 if (mode == PCI_PROBE_DEVTREE) {
1742 bus->subordinate = hose->last_busno;
1743 of_scan_bus(node, bus);
1746 if (mode == PCI_PROBE_NORMAL)
1747 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);