2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
24 #include <linux/export.h>
25 #include <linux/of_address.h>
26 #include <linux/of_pci.h>
28 #include <linux/list.h>
29 #include <linux/syscalls.h>
30 #include <linux/irq.h>
31 #include <linux/vmalloc.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
35 #include <asm/processor.h>
38 #include <asm/pci-bridge.h>
39 #include <asm/byteorder.h>
40 #include <asm/machdep.h>
41 #include <asm/ppc-pci.h>
44 static DEFINE_SPINLOCK(hose_spinlock);
47 /* XXX kill that some day ... */
48 static int global_phb_number; /* Global phb counter */
50 /* ISA Memory physical address */
51 resource_size_t isa_mem_base;
54 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
56 void set_pci_dma_ops(struct dma_map_ops *dma_ops)
58 pci_dma_ops = dma_ops;
61 struct dma_map_ops *get_pci_dma_ops(void)
65 EXPORT_SYMBOL(get_pci_dma_ops);
67 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
69 struct pci_controller *phb;
71 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
74 spin_lock(&hose_spinlock);
75 phb->global_number = global_phb_number++;
76 list_add_tail(&phb->list_node, &hose_list);
77 spin_unlock(&hose_spinlock);
79 phb->is_dynamic = mem_init_done;
82 int nid = of_node_to_nid(dev);
84 if (nid < 0 || !node_online(nid))
87 PHB_SET_NODE(phb, nid);
93 void pcibios_free_controller(struct pci_controller *phb)
95 spin_lock(&hose_spinlock);
96 list_del(&phb->list_node);
97 spin_unlock(&hose_spinlock);
104 * The function is used to return the minimal alignment
105 * for memory or I/O windows of the associated P2P bridge.
106 * By default, 4KiB alignment for I/O windows and 1MiB for
109 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
112 if (ppc_md.pcibios_window_alignment)
113 return ppc_md.pcibios_window_alignment(bus, type);
116 * PCI core will figure out the default
117 * alignment: 4KiB for I/O and 1MiB for
123 void pcibios_reset_secondary_bus(struct pci_dev *dev)
125 if (ppc_md.pcibios_reset_secondary_bus) {
126 ppc_md.pcibios_reset_secondary_bus(dev);
130 pci_reset_secondary_bus(dev);
133 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
136 return hose->pci_io_size;
138 return resource_size(&hose->io_resource);
142 int pcibios_vaddr_is_ioport(void __iomem *address)
145 struct pci_controller *hose;
146 resource_size_t size;
148 spin_lock(&hose_spinlock);
149 list_for_each_entry(hose, &hose_list, list_node) {
150 size = pcibios_io_size(hose);
151 if (address >= hose->io_base_virt &&
152 address < (hose->io_base_virt + size)) {
157 spin_unlock(&hose_spinlock);
161 unsigned long pci_address_to_pio(phys_addr_t address)
163 struct pci_controller *hose;
164 resource_size_t size;
165 unsigned long ret = ~0;
167 spin_lock(&hose_spinlock);
168 list_for_each_entry(hose, &hose_list, list_node) {
169 size = pcibios_io_size(hose);
170 if (address >= hose->io_base_phys &&
171 address < (hose->io_base_phys + size)) {
173 (unsigned long)hose->io_base_virt - _IO_BASE;
174 ret = base + (address - hose->io_base_phys);
178 spin_unlock(&hose_spinlock);
182 EXPORT_SYMBOL_GPL(pci_address_to_pio);
185 * Return the domain number for this bus.
187 int pci_domain_nr(struct pci_bus *bus)
189 struct pci_controller *hose = pci_bus_to_host(bus);
191 return hose->global_number;
193 EXPORT_SYMBOL(pci_domain_nr);
195 /* This routine is meant to be used early during boot, when the
196 * PCI bus numbers have not yet been assigned, and you need to
197 * issue PCI config cycles to an OF device.
198 * It could also be used to "fix" RTAS config cycles if you want
199 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
202 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
205 struct pci_controller *hose, *tmp;
206 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
207 if (hose->dn == node)
215 * Reads the interrupt pin to determine if interrupt is use by card.
216 * If the interrupt is used, then gets the interrupt line from the
217 * openfirmware and sets it in the pci_dev and pci_config line.
219 static int pci_read_irq_line(struct pci_dev *pci_dev)
221 struct of_phandle_args oirq;
224 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
227 memset(&oirq, 0xff, sizeof(oirq));
229 /* Try to get a mapping from the device-tree */
230 if (of_irq_parse_pci(pci_dev, &oirq)) {
233 /* If that fails, lets fallback to what is in the config
234 * space and map that through the default controller. We
235 * also set the type to level low since that's what PCI
236 * interrupts are. If your platform does differently, then
237 * either provide a proper interrupt tree or don't use this
240 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
244 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
245 line == 0xff || line == 0) {
248 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
251 virq = irq_create_mapping(NULL, line);
253 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
255 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
256 oirq.args_count, oirq.args[0], oirq.args[1],
257 of_node_full_name(oirq.np));
259 virq = irq_create_of_mapping(&oirq);
262 pr_debug(" Failed to map !\n");
266 pr_debug(" Mapped to linux irq %d\n", virq);
274 * Platform support for /proc/bus/pci/X/Y mmap()s,
275 * modelled on the sparc64 implementation by Dave Miller.
280 * Adjust vm_pgoff of VMA such that it is the physical page offset
281 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
283 * Basically, the user finds the base address for his device which he wishes
284 * to mmap. They read the 32-bit value from the config space base register,
285 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
286 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
288 * Returns negative error code on failure, zero on success.
290 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
291 resource_size_t *offset,
292 enum pci_mmap_state mmap_state)
294 struct pci_controller *hose = pci_bus_to_host(dev->bus);
295 unsigned long io_offset = 0;
299 return NULL; /* should never happen */
301 /* If memory, add on the PCI bridge address offset */
302 if (mmap_state == pci_mmap_mem) {
303 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
304 *offset += hose->pci_mem_offset;
306 res_bit = IORESOURCE_MEM;
308 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
309 *offset += io_offset;
310 res_bit = IORESOURCE_IO;
314 * Check that the offset requested corresponds to one of the
315 * resources of the device.
317 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
318 struct resource *rp = &dev->resource[i];
319 int flags = rp->flags;
321 /* treat ROM as memory (should be already) */
322 if (i == PCI_ROM_RESOURCE)
323 flags |= IORESOURCE_MEM;
325 /* Active and same type? */
326 if ((flags & res_bit) == 0)
329 /* In the range of this resource? */
330 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
333 /* found it! construct the final physical address */
334 if (mmap_state == pci_mmap_io)
335 *offset += hose->io_base_phys - io_offset;
343 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
346 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
348 enum pci_mmap_state mmap_state,
352 /* Write combine is always 0 on non-memory space mappings. On
353 * memory space, if the user didn't pass 1, we check for a
354 * "prefetchable" resource. This is a bit hackish, but we use
355 * this to workaround the inability of /sysfs to provide a write
358 if (mmap_state != pci_mmap_mem)
360 else if (write_combine == 0) {
361 if (rp->flags & IORESOURCE_PREFETCH)
365 /* XXX would be nice to have a way to ask for write-through */
367 return pgprot_noncached_wc(protection);
369 return pgprot_noncached(protection);
373 * This one is used by /dev/mem and fbdev who have no clue about the
374 * PCI device, it tries to find the PCI device first and calls the
377 pgprot_t pci_phys_mem_access_prot(struct file *file,
382 struct pci_dev *pdev = NULL;
383 struct resource *found = NULL;
384 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
387 if (page_is_ram(pfn))
390 prot = pgprot_noncached(prot);
391 for_each_pci_dev(pdev) {
392 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
393 struct resource *rp = &pdev->resource[i];
394 int flags = rp->flags;
396 /* Active and same type? */
397 if ((flags & IORESOURCE_MEM) == 0)
399 /* In the range of this resource? */
400 if (offset < (rp->start & PAGE_MASK) ||
410 if (found->flags & IORESOURCE_PREFETCH)
411 prot = pgprot_noncached_wc(prot);
415 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
416 (unsigned long long)offset, pgprot_val(prot));
423 * Perform the actual remap of the pages for a PCI device mapping, as
424 * appropriate for this architecture. The region in the process to map
425 * is described by vm_start and vm_end members of VMA, the base physical
426 * address is found in vm_pgoff.
427 * The pci device structure is provided so that architectures may make mapping
428 * decisions on a per-device or per-bus basis.
430 * Returns a negative error code on failure, zero on success.
432 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
433 enum pci_mmap_state mmap_state, int write_combine)
435 resource_size_t offset =
436 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
440 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
444 vma->vm_pgoff = offset >> PAGE_SHIFT;
445 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
447 mmap_state, write_combine);
449 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
450 vma->vm_end - vma->vm_start, vma->vm_page_prot);
455 /* This provides legacy IO read access on a bus */
456 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
458 unsigned long offset;
459 struct pci_controller *hose = pci_bus_to_host(bus);
460 struct resource *rp = &hose->io_resource;
463 /* Check if port can be supported by that bus. We only check
464 * the ranges of the PHB though, not the bus itself as the rules
465 * for forwarding legacy cycles down bridges are not our problem
466 * here. So if the host bridge supports it, we do it.
468 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
471 if (!(rp->flags & IORESOURCE_IO))
473 if (offset < rp->start || (offset + size) > rp->end)
475 addr = hose->io_base_virt + port;
479 *((u8 *)val) = in_8(addr);
484 *((u16 *)val) = in_le16(addr);
489 *((u32 *)val) = in_le32(addr);
495 /* This provides legacy IO write access on a bus */
496 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
498 unsigned long offset;
499 struct pci_controller *hose = pci_bus_to_host(bus);
500 struct resource *rp = &hose->io_resource;
503 /* Check if port can be supported by that bus. We only check
504 * the ranges of the PHB though, not the bus itself as the rules
505 * for forwarding legacy cycles down bridges are not our problem
506 * here. So if the host bridge supports it, we do it.
508 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
511 if (!(rp->flags & IORESOURCE_IO))
513 if (offset < rp->start || (offset + size) > rp->end)
515 addr = hose->io_base_virt + port;
517 /* WARNING: The generic code is idiotic. It gets passed a pointer
518 * to what can be a 1, 2 or 4 byte quantity and always reads that
519 * as a u32, which means that we have to correct the location of
520 * the data read within those 32 bits for size 1 and 2
524 out_8(addr, val >> 24);
529 out_le16(addr, val >> 16);
540 /* This provides legacy IO or memory mmap access on a bus */
541 int pci_mmap_legacy_page_range(struct pci_bus *bus,
542 struct vm_area_struct *vma,
543 enum pci_mmap_state mmap_state)
545 struct pci_controller *hose = pci_bus_to_host(bus);
546 resource_size_t offset =
547 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
548 resource_size_t size = vma->vm_end - vma->vm_start;
551 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
552 pci_domain_nr(bus), bus->number,
553 mmap_state == pci_mmap_mem ? "MEM" : "IO",
554 (unsigned long long)offset,
555 (unsigned long long)(offset + size - 1));
557 if (mmap_state == pci_mmap_mem) {
560 * Because X is lame and can fail starting if it gets an error trying
561 * to mmap legacy_mem (instead of just moving on without legacy memory
562 * access) we fake it here by giving it anonymous memory, effectively
563 * behaving just like /dev/zero
565 if ((offset + size) > hose->isa_mem_size) {
567 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
568 current->comm, current->pid, pci_domain_nr(bus), bus->number);
569 if (vma->vm_flags & VM_SHARED)
570 return shmem_zero_setup(vma);
573 offset += hose->isa_mem_phys;
575 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
576 unsigned long roffset = offset + io_offset;
577 rp = &hose->io_resource;
578 if (!(rp->flags & IORESOURCE_IO))
580 if (roffset < rp->start || (roffset + size) > rp->end)
582 offset += hose->io_base_phys;
584 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
586 vma->vm_pgoff = offset >> PAGE_SHIFT;
587 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
588 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
589 vma->vm_end - vma->vm_start,
593 void pci_resource_to_user(const struct pci_dev *dev, int bar,
594 const struct resource *rsrc,
595 resource_size_t *start, resource_size_t *end)
597 struct pci_controller *hose = pci_bus_to_host(dev->bus);
598 resource_size_t offset = 0;
603 if (rsrc->flags & IORESOURCE_IO)
604 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
606 /* We pass a fully fixed up address to userland for MMIO instead of
607 * a BAR value because X is lame and expects to be able to use that
608 * to pass to /dev/mem !
610 * That means that we'll have potentially 64 bits values where some
611 * userland apps only expect 32 (like X itself since it thinks only
612 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
615 * Hopefully, the sysfs insterface is immune to that gunk. Once X
616 * has been fixed (and the fix spread enough), we can re-enable the
617 * 2 lines below and pass down a BAR value to userland. In that case
618 * we'll also have to re-enable the matching code in
619 * __pci_mmap_make_offset().
624 else if (rsrc->flags & IORESOURCE_MEM)
625 offset = hose->pci_mem_offset;
628 *start = rsrc->start - offset;
629 *end = rsrc->end - offset;
633 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
634 * @hose: newly allocated pci_controller to be setup
635 * @dev: device node of the host bridge
636 * @primary: set if primary bus (32 bits only, soon to be deprecated)
638 * This function will parse the "ranges" property of a PCI host bridge device
639 * node and setup the resource mapping of a pci controller based on its
642 * Life would be boring if it wasn't for a few issues that we have to deal
645 * - We can only cope with one IO space range and up to 3 Memory space
646 * ranges. However, some machines (thanks Apple !) tend to split their
647 * space into lots of small contiguous ranges. So we have to coalesce.
649 * - Some busses have IO space not starting at 0, which causes trouble with
650 * the way we do our IO resource renumbering. The code somewhat deals with
651 * it for 64 bits but I would expect problems on 32 bits.
653 * - Some 32 bits platforms such as 4xx can have physical space larger than
654 * 32 bits so we need to use 64 bits values for the parsing
656 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
657 struct device_node *dev, int primary)
660 struct resource *res;
661 struct of_pci_range range;
662 struct of_pci_range_parser parser;
664 printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
665 dev->full_name, primary ? "(primary)" : "");
667 /* Check for ranges property */
668 if (of_pci_range_parser_init(&parser, dev))
672 for_each_of_pci_range(&parser, &range) {
673 /* If we failed translation or got a zero-sized region
674 * (some FW try to feed us with non sensical zero sized regions
675 * such as power3 which look like some kind of attempt at exposing
676 * the VGA memory hole)
678 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
681 /* Act based on address space type */
683 switch (range.flags & IORESOURCE_TYPE_BITS) {
686 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
687 range.cpu_addr, range.cpu_addr + range.size - 1,
690 /* We support only one IO range */
691 if (hose->pci_io_size) {
693 " \\--> Skipped (too many) !\n");
697 /* On 32 bits, limit I/O space to 16MB */
698 if (range.size > 0x01000000)
699 range.size = 0x01000000;
701 /* 32 bits needs to map IOs here */
702 hose->io_base_virt = ioremap(range.cpu_addr,
705 /* Expect trouble if pci_addr is not 0 */
708 (unsigned long)hose->io_base_virt;
709 #endif /* CONFIG_PPC32 */
710 /* pci_io_size and io_base_phys always represent IO
711 * space starting at 0 so we factor in pci_addr
713 hose->pci_io_size = range.pci_addr + range.size;
714 hose->io_base_phys = range.cpu_addr - range.pci_addr;
717 res = &hose->io_resource;
718 range.cpu_addr = range.pci_addr;
722 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
723 range.cpu_addr, range.cpu_addr + range.size - 1,
725 (range.pci_space & 0x40000000) ?
728 /* We support only 3 memory ranges */
731 " \\--> Skipped (too many) !\n");
734 /* Handles ISA memory hole space here */
735 if (range.pci_addr == 0) {
736 if (primary || isa_mem_base == 0)
737 isa_mem_base = range.cpu_addr;
738 hose->isa_mem_phys = range.cpu_addr;
739 hose->isa_mem_size = range.size;
743 hose->mem_offset[memno] = range.cpu_addr -
745 res = &hose->mem_resources[memno++];
749 res->name = dev->full_name;
750 res->flags = range.flags;
751 res->start = range.cpu_addr;
752 res->end = range.cpu_addr + range.size - 1;
753 res->parent = res->child = res->sibling = NULL;
758 /* Decide whether to display the domain number in /proc */
759 int pci_proc_domain(struct pci_bus *bus)
761 struct pci_controller *hose = pci_bus_to_host(bus);
763 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
765 if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
766 return hose->global_number != 0;
770 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
772 if (ppc_md.pcibios_root_bridge_prepare)
773 return ppc_md.pcibios_root_bridge_prepare(bridge);
778 /* This header fixup will do the resource fixup for all devices as they are
779 * probed, but not for bridge ranges
781 static void pcibios_fixup_resources(struct pci_dev *dev)
783 struct pci_controller *hose = pci_bus_to_host(dev->bus);
787 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
791 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
792 struct resource *res = dev->resource + i;
793 struct pci_bus_region reg;
797 /* If we're going to re-assign everything, we mark all resources
798 * as unset (and 0-base them). In addition, we mark BARs starting
799 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
800 * since in that case, we don't want to re-assign anything
802 pcibios_resource_to_bus(dev->bus, ®, res);
803 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
804 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
805 /* Only print message if not re-assigning */
806 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
807 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] "
810 (unsigned long long)res->start,
811 (unsigned long long)res->end,
812 (unsigned int)res->flags);
813 res->end -= res->start;
815 res->flags |= IORESOURCE_UNSET;
819 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
821 (unsigned long long)res->start,\
822 (unsigned long long)res->end,
823 (unsigned int)res->flags);
826 /* Call machine specific resource fixup */
827 if (ppc_md.pcibios_fixup_resources)
828 ppc_md.pcibios_fixup_resources(dev);
830 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
832 /* This function tries to figure out if a bridge resource has been initialized
833 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
834 * things go more smoothly when it gets it right. It should covers cases such
835 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
837 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
838 struct resource *res)
840 struct pci_controller *hose = pci_bus_to_host(bus);
841 struct pci_dev *dev = bus->self;
842 resource_size_t offset;
843 struct pci_bus_region region;
847 /* We don't do anything if PCI_PROBE_ONLY is set */
848 if (pci_has_flag(PCI_PROBE_ONLY))
851 /* Job is a bit different between memory and IO */
852 if (res->flags & IORESOURCE_MEM) {
853 pcibios_resource_to_bus(dev->bus, ®ion, res);
855 /* If the BAR is non-0 then it's probably been initialized */
856 if (region.start != 0)
859 /* The BAR is 0, let's check if memory decoding is enabled on
860 * the bridge. If not, we consider it unassigned
862 pci_read_config_word(dev, PCI_COMMAND, &command);
863 if ((command & PCI_COMMAND_MEMORY) == 0)
866 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
867 * resources covers that starting address (0 then it's good enough for
868 * us for memory space)
870 for (i = 0; i < 3; i++) {
871 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
872 hose->mem_resources[i].start == hose->mem_offset[i])
876 /* Well, it starts at 0 and we know it will collide so we may as
877 * well consider it as unassigned. That covers the Apple case.
881 /* If the BAR is non-0, then we consider it assigned */
882 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
883 if (((res->start - offset) & 0xfffffffful) != 0)
886 /* Here, we are a bit different than memory as typically IO space
887 * starting at low addresses -is- valid. What we do instead if that
888 * we consider as unassigned anything that doesn't have IO enabled
889 * in the PCI command register, and that's it.
891 pci_read_config_word(dev, PCI_COMMAND, &command);
892 if (command & PCI_COMMAND_IO)
895 /* It's starting at 0 and IO is disabled in the bridge, consider
902 /* Fixup resources of a PCI<->PCI bridge */
903 static void pcibios_fixup_bridge(struct pci_bus *bus)
905 struct resource *res;
908 struct pci_dev *dev = bus->self;
910 pci_bus_for_each_resource(bus, res, i) {
911 if (!res || !res->flags)
913 if (i >= 3 && bus->self->transparent)
916 /* If we're going to reassign everything, we can
917 * shrink the P2P resource to have size as being
918 * of 0 in order to save space.
920 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
921 res->flags |= IORESOURCE_UNSET;
927 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x]\n",
929 (unsigned long long)res->start,\
930 (unsigned long long)res->end,
931 (unsigned int)res->flags);
933 /* Try to detect uninitialized P2P bridge resources,
934 * and clear them out so they get re-assigned later
936 if (pcibios_uninitialized_bridge_resource(bus, res)) {
938 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
943 void pcibios_setup_bus_self(struct pci_bus *bus)
945 /* Fix up the bus resources for P2P bridges */
946 if (bus->self != NULL)
947 pcibios_fixup_bridge(bus);
949 /* Platform specific bus fixups. This is currently only used
950 * by fsl_pci and I'm hoping to get rid of it at some point
952 if (ppc_md.pcibios_fixup_bus)
953 ppc_md.pcibios_fixup_bus(bus);
955 /* Setup bus DMA mappings */
956 if (ppc_md.pci_dma_bus_setup)
957 ppc_md.pci_dma_bus_setup(bus);
960 static void pcibios_setup_device(struct pci_dev *dev)
962 /* Fixup NUMA node as it may not be setup yet by the generic
963 * code and is needed by the DMA init
965 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
967 /* Hook up default DMA ops */
968 set_dma_ops(&dev->dev, pci_dma_ops);
969 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
971 /* Additional platform DMA/iommu setup */
972 if (ppc_md.pci_dma_dev_setup)
973 ppc_md.pci_dma_dev_setup(dev);
975 /* Read default IRQs and fixup if necessary */
976 pci_read_irq_line(dev);
977 if (ppc_md.pci_irq_fixup)
978 ppc_md.pci_irq_fixup(dev);
981 int pcibios_add_device(struct pci_dev *dev)
984 * We can only call pcibios_setup_device() after bus setup is complete,
985 * since some of the platform specific DMA setup code depends on it.
987 if (dev->bus->is_added)
988 pcibios_setup_device(dev);
992 void pcibios_setup_bus_devices(struct pci_bus *bus)
996 pr_debug("PCI: Fixup bus devices %d (%s)\n",
997 bus->number, bus->self ? pci_name(bus->self) : "PHB");
999 list_for_each_entry(dev, &bus->devices, bus_list) {
1000 /* Cardbus can call us to add new devices to a bus, so ignore
1001 * those who are already fully discovered
1006 pcibios_setup_device(dev);
1010 void pcibios_set_master(struct pci_dev *dev)
1012 /* No special bus mastering setup handling */
1015 void pcibios_fixup_bus(struct pci_bus *bus)
1017 /* When called from the generic PCI probe, read PCI<->PCI bridge
1018 * bases. This is -not- called when generating the PCI tree from
1019 * the OF device-tree.
1021 pci_read_bridge_bases(bus);
1023 /* Now fixup the bus bus */
1024 pcibios_setup_bus_self(bus);
1026 /* Now fixup devices on that bus */
1027 pcibios_setup_bus_devices(bus);
1029 EXPORT_SYMBOL(pcibios_fixup_bus);
1031 void pci_fixup_cardbus(struct pci_bus *bus)
1033 /* Now fixup devices on that bus */
1034 pcibios_setup_bus_devices(bus);
1038 static int skip_isa_ioresource_align(struct pci_dev *dev)
1040 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
1041 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1047 * We need to avoid collisions with `mirrored' VGA ports
1048 * and other strange ISA hardware, so we always want the
1049 * addresses to be allocated in the 0x000-0x0ff region
1052 * Why? Because some silly external IO cards only decode
1053 * the low 10 bits of the IO address. The 0x00-0xff region
1054 * is reserved for motherboard devices that decode all 16
1055 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1056 * but we want to try to avoid allocating at 0x2900-0x2bff
1057 * which might have be mirrored at 0x0100-0x03ff..
1059 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1060 resource_size_t size, resource_size_t align)
1062 struct pci_dev *dev = data;
1063 resource_size_t start = res->start;
1065 if (res->flags & IORESOURCE_IO) {
1066 if (skip_isa_ioresource_align(dev))
1069 start = (start + 0x3ff) & ~0x3ff;
1074 EXPORT_SYMBOL(pcibios_align_resource);
1077 * Reparent resource children of pr that conflict with res
1078 * under res, and make res replace those children.
1080 static int reparent_resources(struct resource *parent,
1081 struct resource *res)
1083 struct resource *p, **pp;
1084 struct resource **firstpp = NULL;
1086 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1087 if (p->end < res->start)
1089 if (res->end < p->start)
1091 if (p->start < res->start || p->end > res->end)
1092 return -1; /* not completely contained */
1093 if (firstpp == NULL)
1096 if (firstpp == NULL)
1097 return -1; /* didn't find any conflicting entries? */
1098 res->parent = parent;
1099 res->child = *firstpp;
1103 for (p = res->child; p != NULL; p = p->sibling) {
1105 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1107 (unsigned long long)p->start,
1108 (unsigned long long)p->end, res->name);
1114 * Handle resources of PCI devices. If the world were perfect, we could
1115 * just allocate all the resource regions and do nothing more. It isn't.
1116 * On the other hand, we cannot just re-allocate all devices, as it would
1117 * require us to know lots of host bridge internals. So we attempt to
1118 * keep as much of the original configuration as possible, but tweak it
1119 * when it's found to be wrong.
1121 * Known BIOS problems we have to work around:
1122 * - I/O or memory regions not configured
1123 * - regions configured, but not enabled in the command register
1124 * - bogus I/O addresses above 64K used
1125 * - expansion ROMs left enabled (this may sound harmless, but given
1126 * the fact the PCI specs explicitly allow address decoders to be
1127 * shared between expansion ROMs and other resource regions, it's
1128 * at least dangerous)
1131 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1132 * This gives us fixed barriers on where we can allocate.
1133 * (2) Allocate resources for all enabled devices. If there is
1134 * a collision, just mark the resource as unallocated. Also
1135 * disable expansion ROMs during this step.
1136 * (3) Try to allocate resources for disabled devices. If the
1137 * resources were assigned correctly, everything goes well,
1138 * if they weren't, they won't disturb allocation of other
1140 * (4) Assign new addresses to resources which were either
1141 * not configured at all or misconfigured. If explicitly
1142 * requested by the user, configure expansion ROM address
1146 static void pcibios_allocate_bus_resources(struct pci_bus *bus)
1150 struct resource *res, *pr;
1152 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1153 pci_domain_nr(bus), bus->number);
1155 pci_bus_for_each_resource(bus, res, i) {
1156 if (!res || !res->flags || res->start > res->end || res->parent)
1159 /* If the resource was left unset at this point, we clear it */
1160 if (res->flags & IORESOURCE_UNSET)
1161 goto clear_resource;
1163 if (bus->parent == NULL)
1164 pr = (res->flags & IORESOURCE_IO) ?
1165 &ioport_resource : &iomem_resource;
1167 pr = pci_find_parent_resource(bus->self, res);
1169 /* this happens when the generic PCI
1170 * code (wrongly) decides that this
1171 * bridge is transparent -- paulus
1177 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1178 "[0x%x], parent %p (%s)\n",
1179 bus->self ? pci_name(bus->self) : "PHB",
1181 (unsigned long long)res->start,
1182 (unsigned long long)res->end,
1183 (unsigned int)res->flags,
1184 pr, (pr && pr->name) ? pr->name : "nil");
1186 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1187 if (request_resource(pr, res) == 0)
1190 * Must be a conflict with an existing entry.
1191 * Move that entry (or entries) under the
1192 * bridge resource and try again.
1194 if (reparent_resources(pr, res) == 0)
1197 pr_warning("PCI: Cannot allocate resource region "
1198 "%d of PCI bridge %d, will remap\n", i, bus->number);
1200 /* The resource might be figured out when doing
1201 * reassignment based on the resources required
1202 * by the downstream PCI devices. Here we set
1203 * the size of the resource to be 0 in order to
1211 list_for_each_entry(b, &bus->children, node)
1212 pcibios_allocate_bus_resources(b);
1215 static inline void alloc_resource(struct pci_dev *dev, int idx)
1217 struct resource *pr, *r = &dev->resource[idx];
1219 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1221 (unsigned long long)r->start,
1222 (unsigned long long)r->end,
1223 (unsigned int)r->flags);
1225 pr = pci_find_parent_resource(dev, r);
1226 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1227 request_resource(pr, r) < 0) {
1228 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1229 " of device %s, will remap\n", idx, pci_name(dev));
1231 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1233 (unsigned long long)pr->start,
1234 (unsigned long long)pr->end,
1235 (unsigned int)pr->flags);
1236 /* We'll assign a new address later */
1237 r->flags |= IORESOURCE_UNSET;
1243 static void __init pcibios_allocate_resources(int pass)
1245 struct pci_dev *dev = NULL;
1250 for_each_pci_dev(dev) {
1251 pci_read_config_word(dev, PCI_COMMAND, &command);
1252 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1253 r = &dev->resource[idx];
1254 if (r->parent) /* Already allocated */
1256 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1257 continue; /* Not assigned at all */
1258 /* We only allocate ROMs on pass 1 just in case they
1259 * have been screwed up by firmware
1261 if (idx == PCI_ROM_RESOURCE )
1263 if (r->flags & IORESOURCE_IO)
1264 disabled = !(command & PCI_COMMAND_IO);
1266 disabled = !(command & PCI_COMMAND_MEMORY);
1267 if (pass == disabled)
1268 alloc_resource(dev, idx);
1272 r = &dev->resource[PCI_ROM_RESOURCE];
1274 /* Turn the ROM off, leave the resource region,
1275 * but keep it unregistered.
1278 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1279 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1280 pr_debug("PCI: Switching off ROM of %s\n",
1282 r->flags &= ~IORESOURCE_ROM_ENABLE;
1283 pci_write_config_dword(dev, dev->rom_base_reg,
1284 reg & ~PCI_ROM_ADDRESS_ENABLE);
1290 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1292 struct pci_controller *hose = pci_bus_to_host(bus);
1293 resource_size_t offset;
1294 struct resource *res, *pres;
1297 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1300 if (!(hose->io_resource.flags & IORESOURCE_IO))
1302 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1303 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1304 BUG_ON(res == NULL);
1305 res->name = "Legacy IO";
1306 res->flags = IORESOURCE_IO;
1307 res->start = offset;
1308 res->end = (offset + 0xfff) & 0xfffffffful;
1309 pr_debug("Candidate legacy IO: %pR\n", res);
1310 if (request_resource(&hose->io_resource, res)) {
1312 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1313 pci_domain_nr(bus), bus->number, res);
1318 /* Check for memory */
1319 for (i = 0; i < 3; i++) {
1320 pres = &hose->mem_resources[i];
1321 offset = hose->mem_offset[i];
1322 if (!(pres->flags & IORESOURCE_MEM))
1324 pr_debug("hose mem res: %pR\n", pres);
1325 if ((pres->start - offset) <= 0xa0000 &&
1326 (pres->end - offset) >= 0xbffff)
1331 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1332 BUG_ON(res == NULL);
1333 res->name = "Legacy VGA memory";
1334 res->flags = IORESOURCE_MEM;
1335 res->start = 0xa0000 + offset;
1336 res->end = 0xbffff + offset;
1337 pr_debug("Candidate VGA memory: %pR\n", res);
1338 if (request_resource(pres, res)) {
1340 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1341 pci_domain_nr(bus), bus->number, res);
1346 void __init pcibios_resource_survey(void)
1350 /* Allocate and assign resources */
1351 list_for_each_entry(b, &pci_root_buses, node)
1352 pcibios_allocate_bus_resources(b);
1353 pcibios_allocate_resources(0);
1354 pcibios_allocate_resources(1);
1356 /* Before we start assigning unassigned resource, we try to reserve
1357 * the low IO area and the VGA memory area if they intersect the
1358 * bus available resources to avoid allocating things on top of them
1360 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1361 list_for_each_entry(b, &pci_root_buses, node)
1362 pcibios_reserve_legacy_regions(b);
1365 /* Now, if the platform didn't decide to blindly trust the firmware,
1366 * we proceed to assigning things that were left unassigned
1368 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1369 pr_debug("PCI: Assigning unassigned resources...\n");
1370 pci_assign_unassigned_resources();
1373 /* Call machine dependent fixup */
1374 if (ppc_md.pcibios_fixup)
1375 ppc_md.pcibios_fixup();
1378 /* This is used by the PCI hotplug driver to allocate resource
1379 * of newly plugged busses. We can try to consolidate with the
1380 * rest of the code later, for now, keep it as-is as our main
1381 * resource allocation function doesn't deal with sub-trees yet.
1383 void pcibios_claim_one_bus(struct pci_bus *bus)
1385 struct pci_dev *dev;
1386 struct pci_bus *child_bus;
1388 list_for_each_entry(dev, &bus->devices, bus_list) {
1391 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1392 struct resource *r = &dev->resource[i];
1394 if (r->parent || !r->start || !r->flags)
1397 pr_debug("PCI: Claiming %s: "
1398 "Resource %d: %016llx..%016llx [%x]\n",
1400 (unsigned long long)r->start,
1401 (unsigned long long)r->end,
1402 (unsigned int)r->flags);
1404 pci_claim_resource(dev, i);
1408 list_for_each_entry(child_bus, &bus->children, node)
1409 pcibios_claim_one_bus(child_bus);
1413 /* pcibios_finish_adding_to_bus
1415 * This is to be called by the hotplug code after devices have been
1416 * added to a bus, this include calling it for a PHB that is just
1419 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1421 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1422 pci_domain_nr(bus), bus->number);
1424 /* Allocate bus and devices resources */
1425 pcibios_allocate_bus_resources(bus);
1426 pcibios_claim_one_bus(bus);
1427 if (!pci_has_flag(PCI_PROBE_ONLY))
1428 pci_assign_unassigned_bus_resources(bus);
1431 eeh_add_device_tree_late(bus);
1433 /* Add new devices to global lists. Register in proc, sysfs. */
1434 pci_bus_add_devices(bus);
1436 /* sysfs files should only be added after devices are added */
1437 eeh_add_sysfs_files(bus);
1439 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1441 int pcibios_enable_device(struct pci_dev *dev, int mask)
1443 if (ppc_md.pcibios_enable_device_hook)
1444 if (ppc_md.pcibios_enable_device_hook(dev))
1447 return pci_enable_resources(dev, mask);
1450 resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
1452 return (unsigned long) hose->io_base_virt - _IO_BASE;
1455 static void pcibios_setup_phb_resources(struct pci_controller *hose,
1456 struct list_head *resources)
1458 struct resource *res;
1459 resource_size_t offset;
1462 /* Hookup PHB IO resource */
1463 res = &hose->io_resource;
1466 pr_info("PCI: I/O resource not set for host"
1467 " bridge %s (domain %d)\n",
1468 hose->dn->full_name, hose->global_number);
1470 offset = pcibios_io_space_offset(hose);
1472 pr_debug("PCI: PHB IO resource = %08llx-%08llx [%lx] off 0x%08llx\n",
1473 (unsigned long long)res->start,
1474 (unsigned long long)res->end,
1475 (unsigned long)res->flags,
1476 (unsigned long long)offset);
1477 pci_add_resource_offset(resources, res, offset);
1480 /* Hookup PHB Memory resources */
1481 for (i = 0; i < 3; ++i) {
1482 res = &hose->mem_resources[i];
1485 printk(KERN_ERR "PCI: Memory resource 0 not set for "
1486 "host bridge %s (domain %d)\n",
1487 hose->dn->full_name, hose->global_number);
1490 offset = hose->mem_offset[i];
1493 pr_debug("PCI: PHB MEM resource %d = %08llx-%08llx [%lx] off 0x%08llx\n", i,
1494 (unsigned long long)res->start,
1495 (unsigned long long)res->end,
1496 (unsigned long)res->flags,
1497 (unsigned long long)offset);
1499 pci_add_resource_offset(resources, res, offset);
1504 * Null PCI config access functions, for the case when we can't
1507 #define NULL_PCI_OP(rw, size, type) \
1509 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1511 return PCIBIOS_DEVICE_NOT_FOUND; \
1515 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1518 return PCIBIOS_DEVICE_NOT_FOUND;
1522 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1525 return PCIBIOS_DEVICE_NOT_FOUND;
1528 static struct pci_ops null_pci_ops =
1530 .read = null_read_config,
1531 .write = null_write_config,
1535 * These functions are used early on before PCI scanning is done
1536 * and all of the pci_dev and pci_bus structures have been created.
1538 static struct pci_bus *
1539 fake_pci_bus(struct pci_controller *hose, int busnr)
1541 static struct pci_bus bus;
1544 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1548 bus.ops = hose? hose->ops: &null_pci_ops;
1552 #define EARLY_PCI_OP(rw, size, type) \
1553 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1554 int devfn, int offset, type value) \
1556 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1557 devfn, offset, value); \
1560 EARLY_PCI_OP(read, byte, u8 *)
1561 EARLY_PCI_OP(read, word, u16 *)
1562 EARLY_PCI_OP(read, dword, u32 *)
1563 EARLY_PCI_OP(write, byte, u8)
1564 EARLY_PCI_OP(write, word, u16)
1565 EARLY_PCI_OP(write, dword, u32)
1567 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1570 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1573 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1575 struct pci_controller *hose = bus->sysdata;
1577 return of_node_get(hose->dn);
1581 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1582 * @hose: Pointer to the PCI host controller instance structure
1584 void pcibios_scan_phb(struct pci_controller *hose)
1586 LIST_HEAD(resources);
1587 struct pci_bus *bus;
1588 struct device_node *node = hose->dn;
1591 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node));
1593 /* Get some IO space for the new PHB */
1594 pcibios_setup_phb_io_space(hose);
1596 /* Wire up PHB bus resources */
1597 pcibios_setup_phb_resources(hose, &resources);
1599 hose->busn.start = hose->first_busno;
1600 hose->busn.end = hose->last_busno;
1601 hose->busn.flags = IORESOURCE_BUS;
1602 pci_add_resource(&resources, &hose->busn);
1604 /* Create an empty bus for the toplevel */
1605 bus = pci_create_root_bus(hose->parent, hose->first_busno,
1606 hose->ops, hose, &resources);
1608 pr_err("Failed to create bus for PCI domain %04x\n",
1609 hose->global_number);
1610 pci_free_resource_list(&resources);
1615 /* Get probe mode and perform scan */
1616 mode = PCI_PROBE_NORMAL;
1617 if (node && ppc_md.pci_probe_mode)
1618 mode = ppc_md.pci_probe_mode(bus);
1619 pr_debug(" probe mode: %d\n", mode);
1620 if (mode == PCI_PROBE_DEVTREE)
1621 of_scan_bus(node, bus);
1623 if (mode == PCI_PROBE_NORMAL) {
1624 pci_bus_update_busn_res_end(bus, 255);
1625 hose->last_busno = pci_scan_child_bus(bus);
1626 pci_bus_update_busn_res_end(bus, hose->last_busno);
1629 /* Platform gets a chance to do some global fixups before
1630 * we proceed to resource allocation
1632 if (ppc_md.pcibios_fixup_phb)
1633 ppc_md.pcibios_fixup_phb(hose);
1635 /* Configure PCI Express settings */
1636 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1637 struct pci_bus *child;
1638 list_for_each_entry(child, &bus->children, node)
1639 pcie_bus_configure_settings(child);
1643 static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1645 int i, class = dev->class >> 8;
1646 /* When configured as agent, programing interface = 1 */
1647 int prog_if = dev->class & 0xf;
1649 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1650 class == PCI_CLASS_BRIDGE_OTHER) &&
1651 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1653 (dev->bus->parent == NULL)) {
1654 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1655 dev->resource[i].start = 0;
1656 dev->resource[i].end = 0;
1657 dev->resource[i].flags = 0;
1661 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1662 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1664 static void fixup_vga(struct pci_dev *pdev)
1668 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1669 if ((cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) || !vga_default_device())
1670 vga_set_default_device(pdev);
1673 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1674 PCI_CLASS_DISPLAY_VGA, 8, fixup_vga);