2 * Common pmac/prep/chrp pci routines. -- Cort
5 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/string.h>
9 #include <linux/init.h>
10 #include <linux/capability.h>
11 #include <linux/sched.h>
12 #include <linux/errno.h>
13 #include <linux/bootmem.h>
14 #include <linux/irq.h>
15 #include <linux/list.h>
17 #include <asm/processor.h>
20 #include <asm/sections.h>
21 #include <asm/pci-bridge.h>
22 #include <asm/byteorder.h>
23 #include <asm/uaccess.h>
24 #include <asm/machdep.h>
29 #define DBG(x...) printk(x)
34 unsigned long isa_io_base = 0;
35 unsigned long pci_dram_offset = 0;
36 int pcibios_assign_bus_offset = 1;
38 void pcibios_make_OF_bus_map(void);
40 static int pci_relocate_bridge_resource(struct pci_bus *bus, int i);
41 static int probe_resource(struct pci_bus *parent, struct resource *pr,
42 struct resource *res, struct resource **conflict);
43 static void update_bridge_base(struct pci_bus *bus, int i);
44 static void pcibios_fixup_resources(struct pci_dev* dev);
45 static void fixup_broken_pcnet32(struct pci_dev* dev);
46 static int reparent_resources(struct resource *parent, struct resource *res);
47 static void fixup_cpc710_pci64(struct pci_dev* dev);
49 static u8* pci_to_OF_bus_map;
52 /* By default, we don't re-assign bus numbers. We do this only on
55 int pci_assign_all_buses;
59 static int pci_bus_count;
62 fixup_hide_host_resource_fsl(struct pci_dev* dev)
64 int i, class = dev->class >> 8;
66 if ((class == PCI_CLASS_PROCESSOR_POWERPC) &&
67 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
68 (dev->bus->parent == NULL)) {
69 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
70 dev->resource[i].start = 0;
71 dev->resource[i].end = 0;
72 dev->resource[i].flags = 0;
76 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
77 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
80 fixup_broken_pcnet32(struct pci_dev* dev)
82 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
83 dev->vendor = PCI_VENDOR_ID_AMD;
84 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
87 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
90 fixup_cpc710_pci64(struct pci_dev* dev)
92 /* Hide the PCI64 BARs from the kernel as their content doesn't
93 * fit well in the resource management
95 dev->resource[0].start = dev->resource[0].end = 0;
96 dev->resource[0].flags = 0;
97 dev->resource[1].start = dev->resource[1].end = 0;
98 dev->resource[1].flags = 0;
100 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CPC710_PCI64, fixup_cpc710_pci64);
103 pcibios_fixup_resources(struct pci_dev *dev)
105 struct pci_controller* hose = (struct pci_controller *)dev->sysdata;
107 unsigned long offset;
110 printk(KERN_ERR "No hose for PCI dev %s!\n", pci_name(dev));
113 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
114 struct resource *res = dev->resource + i;
117 if (res->end == 0xffffffff) {
118 DBG("PCI:%s Resource %d [%016llx-%016llx] is unassigned\n",
119 pci_name(dev), i, (u64)res->start, (u64)res->end);
120 res->end -= res->start;
122 res->flags |= IORESOURCE_UNSET;
126 if (res->flags & IORESOURCE_MEM) {
127 offset = hose->pci_mem_offset;
128 } else if (res->flags & IORESOURCE_IO) {
129 offset = (unsigned long) hose->io_base_virt
133 res->start += offset;
135 DBG("Fixup res %d (%lx) of dev %s: %llx -> %llx\n",
136 i, res->flags, pci_name(dev),
137 (u64)res->start - offset, (u64)res->start);
141 /* Call machine specific resource fixup */
142 if (ppc_md.pcibios_fixup_resources)
143 ppc_md.pcibios_fixup_resources(dev);
145 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
147 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
148 struct resource *res)
150 unsigned long offset = 0;
151 struct pci_controller *hose = dev->sysdata;
153 if (hose && res->flags & IORESOURCE_IO)
154 offset = (unsigned long)hose->io_base_virt - isa_io_base;
155 else if (hose && res->flags & IORESOURCE_MEM)
156 offset = hose->pci_mem_offset;
157 region->start = res->start - offset;
158 region->end = res->end - offset;
160 EXPORT_SYMBOL(pcibios_resource_to_bus);
162 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
163 struct pci_bus_region *region)
165 unsigned long offset = 0;
166 struct pci_controller *hose = dev->sysdata;
168 if (hose && res->flags & IORESOURCE_IO)
169 offset = (unsigned long)hose->io_base_virt - isa_io_base;
170 else if (hose && res->flags & IORESOURCE_MEM)
171 offset = hose->pci_mem_offset;
172 res->start = region->start + offset;
173 res->end = region->end + offset;
175 EXPORT_SYMBOL(pcibios_bus_to_resource);
178 * We need to avoid collisions with `mirrored' VGA ports
179 * and other strange ISA hardware, so we always want the
180 * addresses to be allocated in the 0x000-0x0ff region
183 * Why? Because some silly external IO cards only decode
184 * the low 10 bits of the IO address. The 0x00-0xff region
185 * is reserved for motherboard devices that decode all 16
186 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
187 * but we want to try to avoid allocating at 0x2900-0x2bff
188 * which might have be mirrored at 0x0100-0x03ff..
190 void pcibios_align_resource(void *data, struct resource *res,
191 resource_size_t size, resource_size_t align)
193 struct pci_dev *dev = data;
195 if (res->flags & IORESOURCE_IO) {
196 resource_size_t start = res->start;
199 printk(KERN_ERR "PCI: I/O Region %s/%d too large"
200 " (%lld bytes)\n", pci_name(dev),
201 dev->resource - res, (unsigned long long)size);
205 start = (start + 0x3ff) & ~0x3ff;
210 EXPORT_SYMBOL(pcibios_align_resource);
213 * Handle resources of PCI devices. If the world were perfect, we could
214 * just allocate all the resource regions and do nothing more. It isn't.
215 * On the other hand, we cannot just re-allocate all devices, as it would
216 * require us to know lots of host bridge internals. So we attempt to
217 * keep as much of the original configuration as possible, but tweak it
218 * when it's found to be wrong.
220 * Known BIOS problems we have to work around:
221 * - I/O or memory regions not configured
222 * - regions configured, but not enabled in the command register
223 * - bogus I/O addresses above 64K used
224 * - expansion ROMs left enabled (this may sound harmless, but given
225 * the fact the PCI specs explicitly allow address decoders to be
226 * shared between expansion ROMs and other resource regions, it's
227 * at least dangerous)
230 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
231 * This gives us fixed barriers on where we can allocate.
232 * (2) Allocate resources for all enabled devices. If there is
233 * a collision, just mark the resource as unallocated. Also
234 * disable expansion ROMs during this step.
235 * (3) Try to allocate resources for disabled devices. If the
236 * resources were assigned correctly, everything goes well,
237 * if they weren't, they won't disturb allocation of other
239 * (4) Assign new addresses to resources which were either
240 * not configured at all or misconfigured. If explicitly
241 * requested by the user, configure expansion ROM address
246 pcibios_allocate_bus_resources(struct list_head *bus_list)
250 struct resource *res, *pr;
252 /* Depth-First Search on bus tree */
253 list_for_each_entry(bus, bus_list, node) {
254 for (i = 0; i < 4; ++i) {
255 if ((res = bus->resource[i]) == NULL || !res->flags
256 || res->start > res->end)
258 if (bus->parent == NULL)
259 pr = (res->flags & IORESOURCE_IO)?
260 &ioport_resource: &iomem_resource;
262 pr = pci_find_parent_resource(bus->self, res);
264 /* this happens when the generic PCI
265 * code (wrongly) decides that this
266 * bridge is transparent -- paulus
272 DBG("PCI: bridge rsrc %llx..%llx (%lx), parent %p\n",
273 (u64)res->start, (u64)res->end, res->flags, pr);
275 if (request_resource(pr, res) == 0)
278 * Must be a conflict with an existing entry.
279 * Move that entry (or entries) under the
280 * bridge resource and try again.
282 if (reparent_resources(pr, res) == 0)
285 printk(KERN_ERR "PCI: Cannot allocate resource region "
286 "%d of PCI bridge %d\n", i, bus->number);
287 if (pci_relocate_bridge_resource(bus, i))
288 bus->resource[i] = NULL;
290 pcibios_allocate_bus_resources(&bus->children);
295 * Reparent resource children of pr that conflict with res
296 * under res, and make res replace those children.
299 reparent_resources(struct resource *parent, struct resource *res)
301 struct resource *p, **pp;
302 struct resource **firstpp = NULL;
304 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
305 if (p->end < res->start)
307 if (res->end < p->start)
309 if (p->start < res->start || p->end > res->end)
310 return -1; /* not completely contained */
315 return -1; /* didn't find any conflicting entries? */
316 res->parent = parent;
317 res->child = *firstpp;
321 for (p = res->child; p != NULL; p = p->sibling) {
323 DBG(KERN_INFO "PCI: reparented %s [%llx..%llx] under %s\n",
324 p->name, (u64)p->start, (u64)p->end, res->name);
330 * A bridge has been allocated a range which is outside the range
331 * of its parent bridge, so it needs to be moved.
334 pci_relocate_bridge_resource(struct pci_bus *bus, int i)
336 struct resource *res, *pr, *conflict;
337 unsigned long try, size;
339 struct pci_bus *parent = bus->parent;
341 if (parent == NULL) {
342 /* shouldn't ever happen */
343 printk(KERN_ERR "PCI: can't move host bridge resource\n");
346 res = bus->resource[i];
350 for (j = 0; j < 4; j++) {
351 struct resource *r = parent->resource[j];
354 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
356 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) {
360 if (res->flags & IORESOURCE_PREFETCH)
365 size = res->end - res->start;
366 if (pr->start > pr->end || size > pr->end - pr->start)
370 res->start = try - size;
372 if (probe_resource(bus->parent, pr, res, &conflict) == 0)
374 if (conflict->start <= pr->start + size)
376 try = conflict->start - 1;
378 if (request_resource(pr, res)) {
379 DBG(KERN_ERR "PCI: huh? couldn't move to %llx..%llx\n",
380 (u64)res->start, (u64)res->end);
381 return -1; /* "can't happen" */
383 update_bridge_base(bus, i);
384 printk(KERN_INFO "PCI: bridge %d resource %d moved to %llx..%llx\n",
385 bus->number, i, (unsigned long long)res->start,
386 (unsigned long long)res->end);
391 probe_resource(struct pci_bus *parent, struct resource *pr,
392 struct resource *res, struct resource **conflict)
399 for (r = pr->child; r != NULL; r = r->sibling) {
400 if (r->end >= res->start && res->end >= r->start) {
405 list_for_each_entry(bus, &parent->children, node) {
406 for (i = 0; i < 4; ++i) {
407 if ((r = bus->resource[i]) == NULL)
409 if (!r->flags || r->start > r->end || r == res)
411 if (pci_find_parent_resource(bus->self, r) != pr)
413 if (r->end >= res->start && res->end >= r->start) {
419 list_for_each_entry(dev, &parent->devices, bus_list) {
420 for (i = 0; i < 6; ++i) {
421 r = &dev->resource[i];
422 if (!r->flags || (r->flags & IORESOURCE_UNSET))
424 if (pci_find_parent_resource(dev, r) != pr)
426 if (r->end >= res->start && res->end >= r->start) {
436 update_bridge_resource(struct pci_dev *dev, struct resource *res)
438 u8 io_base_lo, io_limit_lo;
439 u16 mem_base, mem_limit;
441 unsigned long start, end, off;
442 struct pci_controller *hose = dev->sysdata;
445 printk("update_bridge_base: no hose?\n");
448 pci_read_config_word(dev, PCI_COMMAND, &cmd);
449 pci_write_config_word(dev, PCI_COMMAND,
450 cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY));
451 if (res->flags & IORESOURCE_IO) {
452 off = (unsigned long) hose->io_base_virt - isa_io_base;
453 start = res->start - off;
454 end = res->end - off;
455 io_base_lo = (start >> 8) & PCI_IO_RANGE_MASK;
456 io_limit_lo = (end >> 8) & PCI_IO_RANGE_MASK;
458 io_base_lo |= PCI_IO_RANGE_TYPE_32;
460 io_base_lo |= PCI_IO_RANGE_TYPE_16;
461 pci_write_config_word(dev, PCI_IO_BASE_UPPER16,
463 pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16,
465 pci_write_config_byte(dev, PCI_IO_BASE, io_base_lo);
466 pci_write_config_byte(dev, PCI_IO_LIMIT, io_limit_lo);
468 } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
470 off = hose->pci_mem_offset;
471 mem_base = ((res->start - off) >> 16) & PCI_MEMORY_RANGE_MASK;
472 mem_limit = ((res->end - off) >> 16) & PCI_MEMORY_RANGE_MASK;
473 pci_write_config_word(dev, PCI_MEMORY_BASE, mem_base);
474 pci_write_config_word(dev, PCI_MEMORY_LIMIT, mem_limit);
476 } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
477 == (IORESOURCE_MEM | IORESOURCE_PREFETCH)) {
478 off = hose->pci_mem_offset;
479 mem_base = ((res->start - off) >> 16) & PCI_PREF_RANGE_MASK;
480 mem_limit = ((res->end - off) >> 16) & PCI_PREF_RANGE_MASK;
481 pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, mem_base);
482 pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, mem_limit);
485 DBG(KERN_ERR "PCI: ugh, bridge %s res has flags=%lx\n",
486 pci_name(dev), res->flags);
488 pci_write_config_word(dev, PCI_COMMAND, cmd);
492 update_bridge_base(struct pci_bus *bus, int i)
494 struct resource *res = bus->resource[i];
495 struct pci_dev *dev = bus->self;
496 update_bridge_resource(dev, res);
499 static inline void alloc_resource(struct pci_dev *dev, int idx)
501 struct resource *pr, *r = &dev->resource[idx];
503 DBG("PCI:%s: Resource %d: %016llx-%016llx (f=%lx)\n",
504 pci_name(dev), idx, (u64)r->start, (u64)r->end, r->flags);
505 pr = pci_find_parent_resource(dev, r);
506 if (!pr || request_resource(pr, r) < 0) {
507 printk(KERN_ERR "PCI: Cannot allocate resource region %d"
508 " of device %s\n", idx, pci_name(dev));
510 DBG("PCI: parent is %p: %016llx-%016llx (f=%lx)\n",
511 pr, (u64)pr->start, (u64)pr->end, pr->flags);
512 /* We'll assign a new address later */
513 r->flags |= IORESOURCE_UNSET;
520 pcibios_allocate_resources(int pass)
522 struct pci_dev *dev = NULL;
527 for_each_pci_dev(dev) {
528 pci_read_config_word(dev, PCI_COMMAND, &command);
529 for (idx = 0; idx < 6; idx++) {
530 r = &dev->resource[idx];
531 if (r->parent) /* Already allocated */
533 if (!r->flags || (r->flags & IORESOURCE_UNSET))
534 continue; /* Not assigned at all */
535 if (r->flags & IORESOURCE_IO)
536 disabled = !(command & PCI_COMMAND_IO);
538 disabled = !(command & PCI_COMMAND_MEMORY);
539 if (pass == disabled)
540 alloc_resource(dev, idx);
544 r = &dev->resource[PCI_ROM_RESOURCE];
545 if (r->flags & IORESOURCE_ROM_ENABLE) {
546 /* Turn the ROM off, leave the resource region, but keep it unregistered. */
548 DBG("PCI: Switching off ROM of %s\n", pci_name(dev));
549 r->flags &= ~IORESOURCE_ROM_ENABLE;
550 pci_read_config_dword(dev, dev->rom_base_reg, ®);
551 pci_write_config_dword(dev, dev->rom_base_reg,
552 reg & ~PCI_ROM_ADDRESS_ENABLE);
558 pcibios_assign_resources(void)
560 struct pci_dev *dev = NULL;
564 for_each_pci_dev(dev) {
565 int class = dev->class >> 8;
567 /* Don't touch classless devices and host bridges */
568 if (!class || class == PCI_CLASS_BRIDGE_HOST)
571 for (idx = 0; idx < 6; idx++) {
572 r = &dev->resource[idx];
575 * We shall assign a new address to this resource,
576 * either because the BIOS (sic) forgot to do so
577 * or because we have decided the old address was
578 * unusable for some reason.
580 if ((r->flags & IORESOURCE_UNSET) && r->end &&
581 (!ppc_md.pcibios_enable_device_hook ||
582 !ppc_md.pcibios_enable_device_hook(dev, 1))) {
585 r->flags &= ~IORESOURCE_UNSET;
586 rc = pci_assign_resource(dev, idx);
591 #if 0 /* don't assign ROMs */
592 r = &dev->resource[PCI_ROM_RESOURCE];
596 pci_assign_resource(dev, PCI_ROM_RESOURCE);
603 * Functions below are used on OpenFirmware machines.
606 make_one_node_map(struct device_node* node, u8 pci_bus)
608 const int *bus_range;
611 if (pci_bus >= pci_bus_count)
613 bus_range = of_get_property(node, "bus-range", &len);
614 if (bus_range == NULL || len < 2 * sizeof(int)) {
615 printk(KERN_WARNING "Can't get bus-range for %s, "
616 "assuming it starts at 0\n", node->full_name);
617 pci_to_OF_bus_map[pci_bus] = 0;
619 pci_to_OF_bus_map[pci_bus] = bus_range[0];
621 for (node=node->child; node != 0;node = node->sibling) {
623 const unsigned int *class_code, *reg;
625 class_code = of_get_property(node, "class-code", NULL);
626 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
627 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
629 reg = of_get_property(node, "reg", NULL);
632 dev = pci_get_bus_and_slot(pci_bus, ((reg[0] >> 8) & 0xff));
633 if (!dev || !dev->subordinate) {
637 make_one_node_map(node, dev->subordinate->number);
643 pcibios_make_OF_bus_map(void)
646 struct pci_controller *hose, *tmp;
647 struct property *map_prop;
648 struct device_node *dn;
650 pci_to_OF_bus_map = kmalloc(pci_bus_count, GFP_KERNEL);
651 if (!pci_to_OF_bus_map) {
652 printk(KERN_ERR "Can't allocate OF bus map !\n");
656 /* We fill the bus map with invalid values, that helps
659 for (i=0; i<pci_bus_count; i++)
660 pci_to_OF_bus_map[i] = 0xff;
662 /* For each hose, we begin searching bridges */
663 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
664 struct device_node* node = hose->dn;
668 make_one_node_map(node, hose->first_busno);
670 dn = of_find_node_by_path("/");
671 map_prop = of_find_property(dn, "pci-OF-bus-map", NULL);
673 BUG_ON(pci_bus_count > map_prop->length);
674 memcpy(map_prop->value, pci_to_OF_bus_map, pci_bus_count);
678 printk("PCI->OF bus map:\n");
679 for (i=0; i<pci_bus_count; i++) {
680 if (pci_to_OF_bus_map[i] == 0xff)
682 printk("%d -> %d\n", i, pci_to_OF_bus_map[i]);
687 typedef int (*pci_OF_scan_iterator)(struct device_node* node, void* data);
689 static struct device_node*
690 scan_OF_pci_childs(struct device_node* node, pci_OF_scan_iterator filter, void* data)
692 struct device_node* sub_node;
694 for (; node != 0;node = node->sibling) {
695 const unsigned int *class_code;
697 if (filter(node, data))
700 /* For PCI<->PCI bridges or CardBus bridges, we go down
701 * Note: some OFs create a parent node "multifunc-device" as
702 * a fake root for all functions of a multi-function device,
703 * we go down them as well.
705 class_code = of_get_property(node, "class-code", NULL);
706 if ((!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
707 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) &&
708 strcmp(node->name, "multifunc-device"))
710 sub_node = scan_OF_pci_childs(node->child, filter, data);
717 static struct device_node *scan_OF_for_pci_dev(struct device_node *parent,
720 struct device_node *np = NULL;
724 while ((np = of_get_next_child(parent, np)) != NULL) {
725 reg = of_get_property(np, "reg", &psize);
726 if (reg == NULL || psize < 4)
728 if (((reg[0] >> 8) & 0xff) == devfn)
735 static struct device_node *scan_OF_for_pci_bus(struct pci_bus *bus)
737 struct device_node *parent, *np;
739 /* Are we a root bus ? */
740 if (bus->self == NULL || bus->parent == NULL) {
741 struct pci_controller *hose = pci_bus_to_host(bus);
744 return of_node_get(hose->dn);
747 /* not a root bus, we need to get our parent */
748 parent = scan_OF_for_pci_bus(bus->parent);
752 /* now iterate for children for a match */
753 np = scan_OF_for_pci_dev(parent, bus->self->devfn);
760 * Scans the OF tree for a device node matching a PCI device
763 pci_busdev_to_OF_node(struct pci_bus *bus, int devfn)
765 struct device_node *parent, *np;
770 DBG("pci_busdev_to_OF_node(%d,0x%x)\n", bus->number, devfn);
771 parent = scan_OF_for_pci_bus(bus);
774 DBG(" parent is %s\n", parent ? parent->full_name : "<NULL>");
775 np = scan_OF_for_pci_dev(parent, devfn);
777 DBG(" result is %s\n", np ? np->full_name : "<NULL>");
779 /* XXX most callers don't release the returned node
780 * mostly because ppc64 doesn't increase the refcount,
781 * we need to fix that.
785 EXPORT_SYMBOL(pci_busdev_to_OF_node);
788 pci_device_to_OF_node(struct pci_dev *dev)
790 return pci_busdev_to_OF_node(dev->bus, dev->devfn);
792 EXPORT_SYMBOL(pci_device_to_OF_node);
795 find_OF_pci_device_filter(struct device_node* node, void* data)
797 return ((void *)node == data);
801 * Returns the PCI device matching a given OF node
804 pci_device_from_OF_node(struct device_node* node, u8* bus, u8* devfn)
806 const unsigned int *reg;
807 struct pci_controller* hose;
808 struct pci_dev* dev = NULL;
812 /* Make sure it's really a PCI device */
813 hose = pci_find_hose_for_OF_device(node);
814 if (!hose || !hose->dn)
816 if (!scan_OF_pci_childs(hose->dn->child,
817 find_OF_pci_device_filter, (void *)node))
819 reg = of_get_property(node, "reg", NULL);
822 *bus = (reg[0] >> 16) & 0xff;
823 *devfn = ((reg[0] >> 8) & 0xff);
825 /* Ok, here we need some tweak. If we have already renumbered
826 * all busses, we can't rely on the OF bus number any more.
827 * the pci_to_OF_bus_map is not enough as several PCI busses
828 * may match the same OF bus number.
830 if (!pci_to_OF_bus_map)
833 for_each_pci_dev(dev)
834 if (pci_to_OF_bus_map[dev->bus->number] == *bus &&
835 dev->devfn == *devfn) {
836 *bus = dev->bus->number;
843 EXPORT_SYMBOL(pci_device_from_OF_node);
846 pci_process_bridge_OF_ranges(struct pci_controller *hose,
847 struct device_node *dev, int primary)
849 static unsigned int static_lc_ranges[256] __initdata;
850 const unsigned int *dt_ranges;
851 unsigned int *lc_ranges, *ranges, *prev, size;
852 int rlen = 0, orig_rlen;
854 struct resource *res;
855 int np, na = of_n_addr_cells(dev);
858 /* First we try to merge ranges to fix a problem with some pmacs
859 * that can have more than 3 ranges, fortunately using contiguous
862 dt_ranges = of_get_property(dev, "ranges", &rlen);
865 /* Sanity check, though hopefully that never happens */
866 if (rlen > sizeof(static_lc_ranges)) {
867 printk(KERN_WARNING "OF ranges property too large !\n");
868 rlen = sizeof(static_lc_ranges);
870 lc_ranges = static_lc_ranges;
871 memcpy(lc_ranges, dt_ranges, rlen);
874 /* Let's work on a copy of the "ranges" property instead of damaging
875 * the device-tree image in memory
879 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
881 if (prev[0] == ranges[0] && prev[1] == ranges[1] &&
882 (prev[2] + prev[na+4]) == ranges[2] &&
883 (prev[na+2] + prev[na+4]) == ranges[na+2]) {
884 prev[na+4] += ranges[na+4];
895 * The ranges property is laid out as an array of elements,
896 * each of which comprises:
897 * cells 0 - 2: a PCI address
898 * cells 3 or 3+4: a CPU physical address
899 * (size depending on dev->n_addr_cells)
900 * cells 4+5 or 5+6: the size of the range
904 while (ranges && (rlen -= np * sizeof(unsigned int)) >= 0) {
907 switch ((ranges[0] >> 24) & 0x3) {
908 case 1: /* I/O space */
911 hose->io_base_phys = ranges[na+2];
912 /* limit I/O space to 16MB */
913 if (size > 0x01000000)
915 hose->io_base_virt = ioremap(ranges[na+2], size);
917 isa_io_base = (unsigned long) hose->io_base_virt;
918 res = &hose->io_resource;
919 res->flags = IORESOURCE_IO;
920 res->start = ranges[2];
921 DBG("PCI: IO 0x%llx -> 0x%llx\n",
922 (u64)res->start, (u64)res->start + size - 1);
924 case 2: /* memory space */
926 if (ranges[1] == 0 && ranges[2] == 0
927 && ranges[na+4] <= (16 << 20)) {
928 /* 1st 16MB, i.e. ISA memory area */
930 isa_mem_base = ranges[na+2];
933 while (memno < 3 && hose->mem_resources[memno].flags)
936 hose->pci_mem_offset = ranges[na+2] - ranges[2];
938 res = &hose->mem_resources[memno];
939 res->flags = IORESOURCE_MEM;
940 if(ranges[0] & 0x40000000)
941 res->flags |= IORESOURCE_PREFETCH;
942 res->start = ranges[na+2];
943 DBG("PCI: MEM[%d] 0x%llx -> 0x%llx\n", memno,
944 (u64)res->start, (u64)res->start + size - 1);
949 res->name = dev->full_name;
950 res->end = res->start + size - 1;
959 /* We create the "pci-OF-bus-map" property now so it appears in the
963 pci_create_OF_bus_map(void)
965 struct property* of_prop;
966 struct device_node *dn;
968 of_prop = (struct property*) alloc_bootmem(sizeof(struct property) + 256);
971 dn = of_find_node_by_path("/");
973 memset(of_prop, -1, sizeof(struct property) + 256);
974 of_prop->name = "pci-OF-bus-map";
975 of_prop->length = 256;
976 of_prop->value = &of_prop[1];
977 prom_add_property(dn, of_prop);
982 #else /* CONFIG_PPC_OF */
983 void pcibios_make_OF_bus_map(void)
986 #endif /* CONFIG_PPC_OF */
988 #ifdef CONFIG_PPC_PMAC
990 * This set of routines checks for PCI<->PCI bridges that have closed
991 * IO resources and have child devices. It tries to re-open an IO
994 * This is a _temporary_ fix to workaround a problem with Apple's OF
995 * closing IO windows on P2P bridges when the OF drivers of cards
996 * below this bridge don't claim any IO range (typically ATI or
999 * A more complete fix would be to use drivers/pci/setup-bus.c, which
1000 * involves a working pcibios_fixup_pbus_ranges(), some more care about
1001 * ordering when creating the host bus resources, and maybe a few more
1005 /* Initialize bridges with base/limit values we have collected */
1007 do_update_p2p_io_resource(struct pci_bus *bus, int enable_vga)
1009 struct pci_dev *bridge = bus->self;
1010 struct pci_controller* hose = (struct pci_controller *)bridge->sysdata;
1013 struct resource res;
1015 if (bus->resource[0] == NULL)
1017 res = *(bus->resource[0]);
1019 DBG("Remapping Bus %d, bridge: %s\n", bus->number, pci_name(bridge));
1020 res.start -= ((unsigned long) hose->io_base_virt - isa_io_base);
1021 res.end -= ((unsigned long) hose->io_base_virt - isa_io_base);
1022 DBG(" IO window: %016llx-%016llx\n", res.start, res.end);
1024 /* Set up the top and bottom of the PCI I/O segment for this bus. */
1025 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
1027 l |= (res.start >> 8) & 0x00f0;
1028 l |= res.end & 0xf000;
1029 pci_write_config_dword(bridge, PCI_IO_BASE, l);
1031 if ((l & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
1032 l = (res.start >> 16) | (res.end & 0xffff0000);
1033 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, l);
1036 pci_read_config_word(bridge, PCI_COMMAND, &w);
1037 w |= PCI_COMMAND_IO;
1038 pci_write_config_word(bridge, PCI_COMMAND, w);
1040 #if 0 /* Enabling this causes XFree 4.2.0 to hang during PCI probe */
1042 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, &w);
1043 w |= PCI_BRIDGE_CTL_VGA;
1044 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, w);
1049 /* This function is pretty basic and actually quite broken for the
1050 * general case, it's enough for us right now though. It's supposed
1051 * to tell us if we need to open an IO range at all or not and what
1055 check_for_io_childs(struct pci_bus *bus, struct resource* res, int *found_vga)
1057 struct pci_dev *dev;
1061 #define push_end(res, mask) do { \
1062 BUG_ON((mask+1) & mask); \
1063 res->end = (res->end + mask) | mask; \
1066 list_for_each_entry(dev, &bus->devices, bus_list) {
1067 u16 class = dev->class >> 8;
1069 if (class == PCI_CLASS_DISPLAY_VGA ||
1070 class == PCI_CLASS_NOT_DEFINED_VGA)
1072 if (class >> 8 == PCI_BASE_CLASS_BRIDGE && dev->subordinate)
1073 rc |= check_for_io_childs(dev->subordinate, res, found_vga);
1074 if (class == PCI_CLASS_BRIDGE_CARDBUS)
1075 push_end(res, 0xfff);
1077 for (i=0; i<PCI_NUM_RESOURCES; i++) {
1079 unsigned long r_size;
1081 if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI
1082 && i >= PCI_BRIDGE_RESOURCES)
1084 r = &dev->resource[i];
1085 r_size = r->end - r->start;
1088 if (r->flags & IORESOURCE_IO && (r_size) != 0) {
1090 push_end(res, r_size);
1098 /* Here we scan all P2P bridges of a given level that have a closed
1099 * IO window. Note that the test for the presence of a VGA card should
1100 * be improved to take into account already configured P2P bridges,
1101 * currently, we don't see them and might end up configuring 2 bridges
1102 * with VGA pass through enabled
1105 do_fixup_p2p_level(struct pci_bus *bus)
1111 for (parent_io=0; parent_io<4; parent_io++)
1112 if (bus->resource[parent_io]
1113 && bus->resource[parent_io]->flags & IORESOURCE_IO)
1118 list_for_each_entry(b, &bus->children, node) {
1119 struct pci_dev *d = b->self;
1120 struct pci_controller* hose = (struct pci_controller *)d->sysdata;
1121 struct resource *res = b->resource[0];
1122 struct resource tmp_res;
1126 memset(&tmp_res, 0, sizeof(tmp_res));
1127 tmp_res.start = bus->resource[parent_io]->start;
1129 /* We don't let low addresses go through that closed P2P bridge, well,
1130 * that may not be necessary but I feel safer that way
1132 if (tmp_res.start == 0)
1133 tmp_res.start = 0x1000;
1135 if (!list_empty(&b->devices) && res && res->flags == 0 &&
1136 res != bus->resource[parent_io] &&
1137 (d->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
1138 check_for_io_childs(b, &tmp_res, &found_vga)) {
1141 printk(KERN_INFO "Fixing up IO bus %s\n", b->name);
1145 printk(KERN_WARNING "Skipping VGA, already active"
1146 " on bus segment\n");
1151 pci_read_config_byte(d, PCI_IO_BASE, &io_base_lo);
1153 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32)
1154 max = ((unsigned long) hose->io_base_virt
1155 - isa_io_base) + 0xffffffff;
1157 max = ((unsigned long) hose->io_base_virt
1158 - isa_io_base) + 0xffff;
1161 res->flags = IORESOURCE_IO;
1162 res->name = b->name;
1164 /* Find a resource in the parent where we can allocate */
1165 for (i = 0 ; i < 4; i++) {
1166 struct resource *r = bus->resource[i];
1169 if ((r->flags & IORESOURCE_IO) == 0)
1171 DBG("Trying to allocate from %016llx, size %016llx from parent"
1172 " res %d: %016llx -> %016llx\n",
1173 res->start, res->end, i, r->start, r->end);
1175 if (allocate_resource(r, res, res->end + 1, res->start, max,
1176 res->end + 1, NULL, NULL) < 0) {
1180 do_update_p2p_io_resource(b, found_vga);
1184 do_fixup_p2p_level(b);
1189 pcibios_fixup_p2p_bridges(void)
1193 list_for_each_entry(b, &pci_root_buses, node)
1194 do_fixup_p2p_level(b);
1197 #endif /* CONFIG_PPC_PMAC */
1202 struct pci_controller *hose, *tmp;
1203 struct pci_bus *bus;
1206 printk(KERN_INFO "PCI: Probing PCI hardware\n");
1208 /* Scan all of the recorded PCI controllers. */
1209 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1210 if (pci_assign_all_buses)
1211 hose->first_busno = next_busno;
1212 hose->last_busno = 0xff;
1213 bus = pci_scan_bus_parented(hose->parent, hose->first_busno,
1216 pci_bus_add_devices(bus);
1217 hose->last_busno = bus->subordinate;
1218 if (pci_assign_all_buses || next_busno <= hose->last_busno)
1219 next_busno = hose->last_busno + pcibios_assign_bus_offset;
1221 pci_bus_count = next_busno;
1223 /* OpenFirmware based machines need a map of OF bus
1224 * numbers vs. kernel bus numbers since we may have to
1227 if (pci_assign_all_buses && have_of)
1228 pcibios_make_OF_bus_map();
1230 /* Call machine dependent fixup */
1231 if (ppc_md.pcibios_fixup)
1232 ppc_md.pcibios_fixup();
1234 /* Allocate and assign resources */
1235 pcibios_allocate_bus_resources(&pci_root_buses);
1236 pcibios_allocate_resources(0);
1237 pcibios_allocate_resources(1);
1238 #ifdef CONFIG_PPC_PMAC
1239 pcibios_fixup_p2p_bridges();
1240 #endif /* CONFIG_PPC_PMAC */
1241 pcibios_assign_resources();
1243 /* Call machine dependent post-init code */
1244 if (ppc_md.pcibios_after_init)
1245 ppc_md.pcibios_after_init();
1250 subsys_initcall(pcibios_init);
1252 void pcibios_fixup_bus(struct pci_bus *bus)
1254 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
1255 unsigned long io_offset;
1256 struct resource *res;
1257 struct pci_dev *dev;
1260 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
1261 if (bus->parent == NULL) {
1262 /* This is a host bridge - fill in its resources */
1265 bus->resource[0] = res = &hose->io_resource;
1268 printk(KERN_ERR "I/O resource not set for host"
1269 " bridge %d\n", hose->global_number);
1271 res->end = IO_SPACE_LIMIT;
1272 res->flags = IORESOURCE_IO;
1274 res->start += io_offset;
1275 res->end += io_offset;
1277 for (i = 0; i < 3; ++i) {
1278 res = &hose->mem_resources[i];
1282 printk(KERN_ERR "Memory resource not set for "
1283 "host bridge %d\n", hose->global_number);
1284 res->start = hose->pci_mem_offset;
1286 res->flags = IORESOURCE_MEM;
1288 bus->resource[i+1] = res;
1291 /* This is a subordinate bridge */
1292 pci_read_bridge_bases(bus);
1294 for (i = 0; i < 4; ++i) {
1295 if ((res = bus->resource[i]) == NULL)
1297 if (!res->flags || bus->self->transparent)
1299 if (io_offset && (res->flags & IORESOURCE_IO)) {
1300 res->start += io_offset;
1301 res->end += io_offset;
1302 } else if (hose->pci_mem_offset
1303 && (res->flags & IORESOURCE_MEM)) {
1304 res->start += hose->pci_mem_offset;
1305 res->end += hose->pci_mem_offset;
1310 /* Platform specific bus fixups */
1311 if (ppc_md.pcibios_fixup_bus)
1312 ppc_md.pcibios_fixup_bus(bus);
1314 /* Read default IRQs and fixup if necessary */
1315 list_for_each_entry(dev, &bus->devices, bus_list) {
1316 pci_read_irq_line(dev);
1317 if (ppc_md.pci_irq_fixup)
1318 ppc_md.pci_irq_fixup(dev);
1322 /* the next one is stolen from the alpha port... */
1324 pcibios_update_irq(struct pci_dev *dev, int irq)
1326 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
1327 /* XXX FIXME - update OF device tree node interrupt property */
1330 int pcibios_enable_device(struct pci_dev *dev, int mask)
1336 if (ppc_md.pcibios_enable_device_hook)
1337 if (ppc_md.pcibios_enable_device_hook(dev, 0))
1340 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1342 for (idx=0; idx<6; idx++) {
1343 r = &dev->resource[idx];
1344 if (r->flags & IORESOURCE_UNSET) {
1345 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
1348 if (r->flags & IORESOURCE_IO)
1349 cmd |= PCI_COMMAND_IO;
1350 if (r->flags & IORESOURCE_MEM)
1351 cmd |= PCI_COMMAND_MEMORY;
1353 if (cmd != old_cmd) {
1354 printk("PCI: Enabling device %s (%04x -> %04x)\n",
1355 pci_name(dev), old_cmd, cmd);
1356 pci_write_config_word(dev, PCI_COMMAND, cmd);
1361 static struct pci_controller*
1362 pci_bus_to_hose(int bus)
1364 struct pci_controller *hose, *tmp;
1366 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1367 if (bus >= hose->first_busno && bus <= hose->last_busno)
1372 /* Provide information on locations of various I/O regions in physical
1373 * memory. Do this on a per-card basis so that we choose the right
1375 * Note that the returned IO or memory base is a physical address
1378 long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1380 struct pci_controller* hose;
1381 long result = -EOPNOTSUPP;
1383 /* Argh ! Please forgive me for that hack, but that's the
1384 * simplest way to get existing XFree to not lockup on some
1385 * G5 machines... So when something asks for bus 0 io base
1386 * (bus 0 is HT root), we return the AGP one instead.
1388 #ifdef CONFIG_PPC_PMAC
1389 if (machine_is(powermac) && machine_is_compatible("MacRISC4"))
1392 #endif /* CONFIG_PPC_PMAC */
1394 hose = pci_bus_to_hose(bus);
1399 case IOBASE_BRIDGE_NUMBER:
1400 return (long)hose->first_busno;
1402 return (long)hose->pci_mem_offset;
1404 return (long)hose->io_base_phys;
1406 return (long)isa_io_base;
1407 case IOBASE_ISA_MEM:
1408 return (long)isa_mem_base;
1414 unsigned long pci_address_to_pio(phys_addr_t address)
1416 struct pci_controller *hose, *tmp;
1418 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1419 unsigned int size = hose->io_resource.end -
1420 hose->io_resource.start + 1;
1421 if (address >= hose->io_base_phys &&
1422 address < (hose->io_base_phys + size)) {
1423 unsigned long base =
1424 (unsigned long)hose->io_base_virt - _IO_BASE;
1425 return base + (address - hose->io_base_phys);
1428 return (unsigned int)-1;
1430 EXPORT_SYMBOL(pci_address_to_pio);
1433 * Null PCI config access functions, for the case when we can't
1436 #define NULL_PCI_OP(rw, size, type) \
1438 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1440 return PCIBIOS_DEVICE_NOT_FOUND; \
1444 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1447 return PCIBIOS_DEVICE_NOT_FOUND;
1451 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1454 return PCIBIOS_DEVICE_NOT_FOUND;
1457 static struct pci_ops null_pci_ops =
1459 .read = null_read_config,
1460 .write = null_write_config,
1464 * These functions are used early on before PCI scanning is done
1465 * and all of the pci_dev and pci_bus structures have been created.
1467 static struct pci_bus *
1468 fake_pci_bus(struct pci_controller *hose, int busnr)
1470 static struct pci_bus bus;
1473 hose = pci_bus_to_hose(busnr);
1475 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1479 bus.ops = hose? hose->ops: &null_pci_ops;
1483 #define EARLY_PCI_OP(rw, size, type) \
1484 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1485 int devfn, int offset, type value) \
1487 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1488 devfn, offset, value); \
1491 EARLY_PCI_OP(read, byte, u8 *)
1492 EARLY_PCI_OP(read, word, u16 *)
1493 EARLY_PCI_OP(read, dword, u32 *)
1494 EARLY_PCI_OP(write, byte, u8)
1495 EARLY_PCI_OP(write, word, u16)
1496 EARLY_PCI_OP(write, dword, u32)
1498 extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap);
1499 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1502 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);