2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
16 #include <linux/config.h>
17 #include <linux/kernel.h>
18 #include <linux/pci.h>
19 #include <linux/string.h>
20 #include <linux/init.h>
21 #include <linux/bootmem.h>
23 #include <linux/list.h>
24 #include <linux/syscalls.h>
26 #include <asm/processor.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/byteorder.h>
32 #include <asm/machdep.h>
33 #include <asm/ppc-pci.h>
37 #define DBG(fmt...) printk(fmt)
42 unsigned long pci_probe_only = 1;
43 int pci_assign_all_buses = 0;
46 * legal IO pages under MAX_ISA_PORT. This is to ensure we don't touch
47 * devices we don't have access to.
49 unsigned long io_page_mask;
51 EXPORT_SYMBOL(io_page_mask);
53 #ifdef CONFIG_PPC_MULTIPLATFORM
54 static void fixup_resource(struct resource *res, struct pci_dev *dev);
55 static void do_bus_setup(struct pci_bus *bus);
58 /* pci_io_base -- the base address from which io bars are offsets.
59 * This is the lowest I/O base address (so bar values are always positive),
60 * and it *must* be the start of ISA space if an ISA bus exists because
61 * ISA drivers use hard coded offsets. If no ISA bus exists a dummy
62 * page is mapped and isa_io_limit prevents access to it.
64 unsigned long isa_io_base; /* NULL if no ISA bus */
65 EXPORT_SYMBOL(isa_io_base);
66 unsigned long pci_io_base;
67 EXPORT_SYMBOL(pci_io_base);
69 void iSeries_pcibios_init(void);
73 struct dma_mapping_ops pci_dma_ops;
74 EXPORT_SYMBOL(pci_dma_ops);
76 int global_phb_number; /* Global phb counter */
78 /* Cached ISA bridge dev. */
79 struct pci_dev *ppc64_isabridge_dev = NULL;
81 static void fixup_broken_pcnet32(struct pci_dev* dev)
83 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
84 dev->vendor = PCI_VENDOR_ID_AMD;
85 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
88 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
90 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
93 unsigned long offset = 0;
94 struct pci_controller *hose = pci_bus_to_host(dev->bus);
99 if (res->flags & IORESOURCE_IO)
100 offset = (unsigned long)hose->io_base_virt - pci_io_base;
102 if (res->flags & IORESOURCE_MEM)
103 offset = hose->pci_mem_offset;
105 region->start = res->start - offset;
106 region->end = res->end - offset;
109 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
110 struct pci_bus_region *region)
112 unsigned long offset = 0;
113 struct pci_controller *hose = pci_bus_to_host(dev->bus);
118 if (res->flags & IORESOURCE_IO)
119 offset = (unsigned long)hose->io_base_virt - pci_io_base;
121 if (res->flags & IORESOURCE_MEM)
122 offset = hose->pci_mem_offset;
124 res->start = region->start + offset;
125 res->end = region->end + offset;
128 #ifdef CONFIG_HOTPLUG
129 EXPORT_SYMBOL(pcibios_resource_to_bus);
130 EXPORT_SYMBOL(pcibios_bus_to_resource);
134 * We need to avoid collisions with `mirrored' VGA ports
135 * and other strange ISA hardware, so we always want the
136 * addresses to be allocated in the 0x000-0x0ff region
139 * Why? Because some silly external IO cards only decode
140 * the low 10 bits of the IO address. The 0x00-0xff region
141 * is reserved for motherboard devices that decode all 16
142 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
143 * but we want to try to avoid allocating at 0x2900-0x2bff
144 * which might have be mirrored at 0x0100-0x03ff..
146 void pcibios_align_resource(void *data, struct resource *res,
147 unsigned long size, unsigned long align)
149 struct pci_dev *dev = data;
150 struct pci_controller *hose = pci_bus_to_host(dev->bus);
151 unsigned long start = res->start;
152 unsigned long alignto;
154 if (res->flags & IORESOURCE_IO) {
155 unsigned long offset = (unsigned long)hose->io_base_virt -
157 /* Make sure we start at our min on all hoses */
158 if (start - offset < PCIBIOS_MIN_IO)
159 start = PCIBIOS_MIN_IO + offset;
162 * Put everything into 0x00-0xff region modulo 0x400
165 start = (start + 0x3ff) & ~0x3ff;
167 } else if (res->flags & IORESOURCE_MEM) {
168 /* Make sure we start at our min on all hoses */
169 if (start - hose->pci_mem_offset < PCIBIOS_MIN_MEM)
170 start = PCIBIOS_MIN_MEM + hose->pci_mem_offset;
172 /* Align to multiple of size of minimum base. */
173 alignto = max(0x1000UL, align);
174 start = ALIGN(start, alignto);
180 static DEFINE_SPINLOCK(hose_spinlock);
183 * pci_controller(phb) initialized common variables.
185 static void __devinit pci_setup_pci_controller(struct pci_controller *hose)
187 memset(hose, 0, sizeof(struct pci_controller));
189 spin_lock(&hose_spinlock);
190 hose->global_number = global_phb_number++;
191 list_add_tail(&hose->list_node, &hose_list);
192 spin_unlock(&hose_spinlock);
195 static void add_linux_pci_domain(struct device_node *dev,
196 struct pci_controller *phb)
198 struct property *of_prop;
201 of_prop = (struct property *)
202 get_property(dev, "linux,pci-domain", &size);
205 WARN_ON(of_prop && size < sizeof(int));
206 if (of_prop && size < sizeof(int))
208 size = sizeof(struct property) + sizeof(int);
209 if (of_prop == NULL) {
211 of_prop = kmalloc(size, GFP_KERNEL);
213 of_prop = alloc_bootmem(size);
215 memset(of_prop, 0, sizeof(struct property));
216 of_prop->name = "linux,pci-domain";
217 of_prop->length = sizeof(int);
218 of_prop->value = (unsigned char *)&of_prop[1];
219 *((int *)of_prop->value) = phb->global_number;
220 prom_add_property(dev, of_prop);
223 struct pci_controller * pcibios_alloc_controller(struct device_node *dev)
225 struct pci_controller *phb;
228 phb = kmalloc(sizeof(struct pci_controller), GFP_KERNEL);
230 phb = alloc_bootmem(sizeof (struct pci_controller));
233 pci_setup_pci_controller(phb);
234 phb->arch_data = dev;
235 phb->is_dynamic = mem_init_done;
237 add_linux_pci_domain(dev, phb);
241 void pcibios_free_controller(struct pci_controller *phb)
243 if (phb->arch_data) {
244 struct device_node *np = phb->arch_data;
245 int *domain = (int *)get_property(np,
246 "linux,pci-domain", NULL);
254 void __devinit pcibios_claim_one_bus(struct pci_bus *b)
257 struct pci_bus *child_bus;
259 list_for_each_entry(dev, &b->devices, bus_list) {
262 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
263 struct resource *r = &dev->resource[i];
265 if (r->parent || !r->start || !r->flags)
267 pci_claim_resource(dev, i);
271 list_for_each_entry(child_bus, &b->children, node)
272 pcibios_claim_one_bus(child_bus);
274 #ifdef CONFIG_HOTPLUG
275 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
278 #ifndef CONFIG_PPC_ISERIES
279 static void __init pcibios_claim_of_setup(void)
283 list_for_each_entry(b, &pci_root_buses, node)
284 pcibios_claim_one_bus(b);
288 #ifdef CONFIG_PPC_MULTIPLATFORM
289 static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
294 prop = (u32 *) get_property(np, name, &len);
295 if (prop && len >= 4)
300 static unsigned int pci_parse_of_flags(u32 addr0)
302 unsigned int flags = 0;
304 if (addr0 & 0x02000000) {
305 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
306 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
307 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
308 if (addr0 & 0x40000000)
309 flags |= IORESOURCE_PREFETCH
310 | PCI_BASE_ADDRESS_MEM_PREFETCH;
311 } else if (addr0 & 0x01000000)
312 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
316 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
318 static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev)
322 struct resource *res;
326 addrs = (u32 *) get_property(node, "assigned-addresses", &proplen);
329 DBG(" parse addresses (%d bytes) @ %p\n", proplen, addrs);
330 for (; proplen >= 20; proplen -= 20, addrs += 5) {
331 flags = pci_parse_of_flags(addrs[0]);
334 base = GET_64BIT(addrs, 1);
335 size = GET_64BIT(addrs, 3);
339 DBG(" base: %llx, size: %llx, i: %x\n",
340 (unsigned long long)base, (unsigned long long)size, i);
342 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
343 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
344 } else if (i == dev->rom_base_reg) {
345 res = &dev->resource[PCI_ROM_RESOURCE];
346 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
348 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
352 res->end = base + size - 1;
354 res->name = pci_name(dev);
355 fixup_resource(res, dev);
359 struct pci_dev *of_create_pci_dev(struct device_node *node,
360 struct pci_bus *bus, int devfn)
365 dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL);
368 type = get_property(node, "device_type", NULL);
372 DBG(" create device, devfn: %x, type: %s\n", devfn, type);
374 memset(dev, 0, sizeof(struct pci_dev));
377 dev->dev.parent = bus->bridge;
378 dev->dev.bus = &pci_bus_type;
380 dev->multifunction = 0; /* maybe a lie? */
382 dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
383 dev->device = get_int_prop(node, "device-id", 0xffff);
384 dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
385 dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
387 dev->cfg_size = pci_cfg_space_size(dev);
389 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
390 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
391 dev->class = get_int_prop(node, "class-code", 0);
393 DBG(" class: 0x%x\n", dev->class);
395 dev->current_state = 4; /* unknown power state */
397 if (!strcmp(type, "pci")) {
398 /* a PCI-PCI bridge */
399 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
400 dev->rom_base_reg = PCI_ROM_ADDRESS1;
401 } else if (!strcmp(type, "cardbus")) {
402 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
404 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
405 dev->rom_base_reg = PCI_ROM_ADDRESS;
407 if (node->n_intrs > 0) {
408 dev->irq = node->intrs[0].line;
409 pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
414 pci_parse_of_addrs(node, dev);
416 DBG(" adding to system ...\n");
418 pci_device_add(dev, bus);
420 /* XXX pci_scan_msi_device(dev); */
424 EXPORT_SYMBOL(of_create_pci_dev);
426 void __devinit of_scan_bus(struct device_node *node,
429 struct device_node *child = NULL;
434 DBG("of_scan_bus(%s) bus no %d... \n", node->full_name, bus->number);
436 while ((child = of_get_next_child(node, child)) != NULL) {
437 DBG(" * %s\n", child->full_name);
438 reg = (u32 *) get_property(child, "reg", ®len);
439 if (reg == NULL || reglen < 20)
441 devfn = (reg[0] >> 8) & 0xff;
443 /* create a new pci_dev for this device */
444 dev = of_create_pci_dev(child, bus, devfn);
447 DBG("dev header type: %x\n", dev->hdr_type);
449 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
450 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
451 of_scan_pci_bridge(child, dev);
456 EXPORT_SYMBOL(of_scan_bus);
458 void __devinit of_scan_pci_bridge(struct device_node *node,
462 u32 *busrange, *ranges;
464 struct resource *res;
468 DBG("of_scan_pci_bridge(%s)\n", node->full_name);
470 /* parse bus-range property */
471 busrange = (u32 *) get_property(node, "bus-range", &len);
472 if (busrange == NULL || len != 8) {
473 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
477 ranges = (u32 *) get_property(node, "ranges", &len);
478 if (ranges == NULL) {
479 printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
484 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
486 printk(KERN_ERR "Failed to create pci bus for %s\n",
491 bus->primary = dev->bus->number;
492 bus->subordinate = busrange[1];
496 /* parse ranges property */
497 /* PCI #address-cells == 3 and #size-cells == 2 always */
498 res = &dev->resource[PCI_BRIDGE_RESOURCES];
499 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
501 bus->resource[i] = res;
505 for (; len >= 32; len -= 32, ranges += 8) {
506 flags = pci_parse_of_flags(ranges[0]);
507 size = GET_64BIT(ranges, 6);
508 if (flags == 0 || size == 0)
510 if (flags & IORESOURCE_IO) {
511 res = bus->resource[0];
513 printk(KERN_ERR "PCI: ignoring extra I/O range"
514 " for bridge %s\n", node->full_name);
518 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
519 printk(KERN_ERR "PCI: too many memory ranges"
520 " for bridge %s\n", node->full_name);
523 res = bus->resource[i];
526 res->start = GET_64BIT(ranges, 1);
527 res->end = res->start + size - 1;
529 fixup_resource(res, dev);
531 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
533 DBG(" bus name: %s\n", bus->name);
535 mode = PCI_PROBE_NORMAL;
536 if (ppc_md.pci_probe_mode)
537 mode = ppc_md.pci_probe_mode(bus);
538 DBG(" probe mode: %d\n", mode);
540 if (mode == PCI_PROBE_DEVTREE)
541 of_scan_bus(node, bus);
542 else if (mode == PCI_PROBE_NORMAL)
543 pci_scan_child_bus(bus);
545 EXPORT_SYMBOL(of_scan_pci_bridge);
546 #endif /* CONFIG_PPC_MULTIPLATFORM */
548 void __devinit scan_phb(struct pci_controller *hose)
551 struct device_node *node = hose->arch_data;
553 struct resource *res;
555 DBG("Scanning PHB %s\n", node ? node->full_name : "<NO NAME>");
557 bus = pci_create_bus(NULL, hose->first_busno, hose->ops, node);
559 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
560 hose->global_number);
563 bus->secondary = hose->first_busno;
566 bus->resource[0] = res = &hose->io_resource;
567 if (res->flags && request_resource(&ioport_resource, res))
568 printk(KERN_ERR "Failed to request PCI IO region "
569 "on PCI domain %04x\n", hose->global_number);
571 for (i = 0; i < 3; ++i) {
572 res = &hose->mem_resources[i];
573 bus->resource[i+1] = res;
574 if (res->flags && request_resource(&iomem_resource, res))
575 printk(KERN_ERR "Failed to request PCI memory region "
576 "on PCI domain %04x\n", hose->global_number);
579 mode = PCI_PROBE_NORMAL;
580 #ifdef CONFIG_PPC_MULTIPLATFORM
581 if (node && ppc_md.pci_probe_mode)
582 mode = ppc_md.pci_probe_mode(bus);
583 DBG(" probe mode: %d\n", mode);
584 if (mode == PCI_PROBE_DEVTREE) {
585 bus->subordinate = hose->last_busno;
586 of_scan_bus(node, bus);
588 #endif /* CONFIG_PPC_MULTIPLATFORM */
589 if (mode == PCI_PROBE_NORMAL)
590 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
591 pci_bus_add_devices(bus);
594 static int __init pcibios_init(void)
596 struct pci_controller *hose, *tmp;
598 /* For now, override phys_mem_access_prot. If we need it,
599 * later, we may move that initialization to each ppc_md
601 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
603 #ifdef CONFIG_PPC_ISERIES
604 iSeries_pcibios_init();
607 printk("PCI: Probing PCI hardware\n");
609 /* Scan all of the recorded PCI controllers. */
610 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
613 #ifndef CONFIG_PPC_ISERIES
615 pcibios_claim_of_setup();
617 /* FIXME: `else' will be removed when
618 pci_assign_unassigned_resources() is able to work
619 correctly with [partially] allocated PCI tree. */
620 pci_assign_unassigned_resources();
621 #endif /* !CONFIG_PPC_ISERIES */
623 /* Call machine dependent final fixup */
624 if (ppc_md.pcibios_fixup)
625 ppc_md.pcibios_fixup();
627 /* Cache the location of the ISA bridge (if we have one) */
628 ppc64_isabridge_dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
629 if (ppc64_isabridge_dev != NULL)
630 printk("ISA bridge at %s\n", pci_name(ppc64_isabridge_dev));
632 #ifdef CONFIG_PPC_MULTIPLATFORM
633 /* map in PCI I/O space */
637 printk("PCI: Probing PCI hardware done\n");
642 subsys_initcall(pcibios_init);
644 char __init *pcibios_setup(char *str)
649 int pcibios_enable_device(struct pci_dev *dev, int mask)
654 pci_read_config_word(dev, PCI_COMMAND, &cmd);
657 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
658 struct resource *res = &dev->resource[i];
660 /* Only set up the requested stuff */
661 if (!(mask & (1<<i)))
664 if (res->flags & IORESOURCE_IO)
665 cmd |= PCI_COMMAND_IO;
666 if (res->flags & IORESOURCE_MEM)
667 cmd |= PCI_COMMAND_MEMORY;
671 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
673 /* Enable the appropriate bits in the PCI command register. */
674 pci_write_config_word(dev, PCI_COMMAND, cmd);
680 * Return the domain number for this bus.
682 int pci_domain_nr(struct pci_bus *bus)
684 #ifdef CONFIG_PPC_ISERIES
687 struct pci_controller *hose = pci_bus_to_host(bus);
689 return hose->global_number;
693 EXPORT_SYMBOL(pci_domain_nr);
695 /* Decide whether to display the domain number in /proc */
696 int pci_proc_domain(struct pci_bus *bus)
698 #ifdef CONFIG_PPC_ISERIES
701 struct pci_controller *hose = pci_bus_to_host(bus);
707 * Platform support for /proc/bus/pci/X/Y mmap()s,
708 * modelled on the sparc64 implementation by Dave Miller.
713 * Adjust vm_pgoff of VMA such that it is the physical page offset
714 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
716 * Basically, the user finds the base address for his device which he wishes
717 * to mmap. They read the 32-bit value from the config space base register,
718 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
719 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
721 * Returns negative error code on failure, zero on success.
723 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
724 unsigned long *offset,
725 enum pci_mmap_state mmap_state)
727 struct pci_controller *hose = pci_bus_to_host(dev->bus);
728 unsigned long io_offset = 0;
732 return NULL; /* should never happen */
734 /* If memory, add on the PCI bridge address offset */
735 if (mmap_state == pci_mmap_mem) {
736 *offset += hose->pci_mem_offset;
737 res_bit = IORESOURCE_MEM;
739 io_offset = (unsigned long)hose->io_base_virt - pci_io_base;
740 *offset += io_offset;
741 res_bit = IORESOURCE_IO;
745 * Check that the offset requested corresponds to one of the
746 * resources of the device.
748 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
749 struct resource *rp = &dev->resource[i];
750 int flags = rp->flags;
752 /* treat ROM as memory (should be already) */
753 if (i == PCI_ROM_RESOURCE)
754 flags |= IORESOURCE_MEM;
756 /* Active and same type? */
757 if ((flags & res_bit) == 0)
760 /* In the range of this resource? */
761 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
764 /* found it! construct the final physical address */
765 if (mmap_state == pci_mmap_io)
766 *offset += hose->io_base_phys - io_offset;
774 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
777 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
779 enum pci_mmap_state mmap_state,
782 unsigned long prot = pgprot_val(protection);
784 /* Write combine is always 0 on non-memory space mappings. On
785 * memory space, if the user didn't pass 1, we check for a
786 * "prefetchable" resource. This is a bit hackish, but we use
787 * this to workaround the inability of /sysfs to provide a write
790 if (mmap_state != pci_mmap_mem)
792 else if (write_combine == 0) {
793 if (rp->flags & IORESOURCE_PREFETCH)
797 /* XXX would be nice to have a way to ask for write-through */
798 prot |= _PAGE_NO_CACHE;
800 prot &= ~_PAGE_GUARDED;
802 prot |= _PAGE_GUARDED;
804 printk("PCI map for %s:%lx, prot: %lx\n", pci_name(dev), rp->start,
807 return __pgprot(prot);
811 * This one is used by /dev/mem and fbdev who have no clue about the
812 * PCI device, it tries to find the PCI device first and calls the
815 pgprot_t pci_phys_mem_access_prot(struct file *file,
820 struct pci_dev *pdev = NULL;
821 struct resource *found = NULL;
822 unsigned long prot = pgprot_val(protection);
823 unsigned long offset = pfn << PAGE_SHIFT;
826 if (page_is_ram(pfn))
827 return __pgprot(prot);
829 prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
831 for_each_pci_dev(pdev) {
832 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
833 struct resource *rp = &pdev->resource[i];
834 int flags = rp->flags;
836 /* Active and same type? */
837 if ((flags & IORESOURCE_MEM) == 0)
839 /* In the range of this resource? */
840 if (offset < (rp->start & PAGE_MASK) ||
850 if (found->flags & IORESOURCE_PREFETCH)
851 prot &= ~_PAGE_GUARDED;
855 DBG("non-PCI map for %lx, prot: %lx\n", offset, prot);
857 return __pgprot(prot);
862 * Perform the actual remap of the pages for a PCI device mapping, as
863 * appropriate for this architecture. The region in the process to map
864 * is described by vm_start and vm_end members of VMA, the base physical
865 * address is found in vm_pgoff.
866 * The pci device structure is provided so that architectures may make mapping
867 * decisions on a per-device or per-bus basis.
869 * Returns a negative error code on failure, zero on success.
871 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
872 enum pci_mmap_state mmap_state, int write_combine)
874 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
878 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
882 vma->vm_pgoff = offset >> PAGE_SHIFT;
883 vma->vm_flags |= VM_SHM | VM_LOCKED | VM_IO;
884 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
886 mmap_state, write_combine);
888 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
889 vma->vm_end - vma->vm_start, vma->vm_page_prot);
894 #ifdef CONFIG_PPC_MULTIPLATFORM
895 static ssize_t pci_show_devspec(struct device *dev, struct device_attribute *attr, char *buf)
897 struct pci_dev *pdev;
898 struct device_node *np;
900 pdev = to_pci_dev (dev);
901 np = pci_device_to_OF_node(pdev);
902 if (np == NULL || np->full_name == NULL)
904 return sprintf(buf, "%s", np->full_name);
906 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
907 #endif /* CONFIG_PPC_MULTIPLATFORM */
909 void pcibios_add_platform_entries(struct pci_dev *pdev)
911 #ifdef CONFIG_PPC_MULTIPLATFORM
912 device_create_file(&pdev->dev, &dev_attr_devspec);
913 #endif /* CONFIG_PPC_MULTIPLATFORM */
916 #ifdef CONFIG_PPC_MULTIPLATFORM
918 #define ISA_SPACE_MASK 0x1
919 #define ISA_SPACE_IO 0x1
921 static void __devinit pci_process_ISA_OF_ranges(struct device_node *isa_node,
922 unsigned long phb_io_base_phys,
923 void __iomem * phb_io_base_virt)
925 /* Remove these asap */
939 struct isa_address isa_addr;
940 struct pci_address pci_addr;
944 struct isa_range *range;
945 unsigned long pci_addr;
946 unsigned int isa_addr;
950 range = (struct isa_range *) get_property(isa_node, "ranges", &rlen);
951 if (range == NULL || (rlen < sizeof(struct isa_range))) {
952 printk(KERN_ERR "no ISA ranges or unexpected isa range size,"
954 __ioremap_explicit(phb_io_base_phys,
955 (unsigned long)phb_io_base_virt,
956 0x10000, _PAGE_NO_CACHE | _PAGE_GUARDED);
960 /* From "ISA Binding to 1275"
961 * The ranges property is laid out as an array of elements,
962 * each of which comprises:
963 * cells 0 - 1: an ISA address
964 * cells 2 - 4: a PCI address
965 * (size depending on dev->n_addr_cells)
966 * cell 5: the size of the range
968 if ((range->isa_addr.a_hi && ISA_SPACE_MASK) == ISA_SPACE_IO) {
969 isa_addr = range->isa_addr.a_lo;
970 pci_addr = (unsigned long) range->pci_addr.a_mid << 32 |
971 range->pci_addr.a_lo;
973 /* Assume these are both zero */
974 if ((pci_addr != 0) || (isa_addr != 0)) {
975 printk(KERN_ERR "unexpected isa to pci mapping: %s\n",
980 size = PAGE_ALIGN(range->size);
982 __ioremap_explicit(phb_io_base_phys,
983 (unsigned long) phb_io_base_virt,
984 size, _PAGE_NO_CACHE | _PAGE_GUARDED);
988 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
989 struct device_node *dev, int prim)
991 unsigned int *ranges, pci_space;
995 struct resource *res;
996 int np, na = prom_n_addr_cells(dev);
997 unsigned long pci_addr, cpu_phys_addr;
1001 /* From "PCI Binding to 1275"
1002 * The ranges property is laid out as an array of elements,
1003 * each of which comprises:
1004 * cells 0 - 2: a PCI address
1005 * cells 3 or 3+4: a CPU physical address
1006 * (size depending on dev->n_addr_cells)
1007 * cells 4+5 or 5+6: the size of the range
1009 ranges = (unsigned int *) get_property(dev, "ranges", &rlen);
1012 hose->io_base_phys = 0;
1013 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
1015 pci_space = ranges[0];
1016 pci_addr = ((unsigned long)ranges[1] << 32) | ranges[2];
1018 cpu_phys_addr = ranges[3];
1020 cpu_phys_addr = (cpu_phys_addr << 32) | ranges[4];
1022 size = ((unsigned long)ranges[na+3] << 32) | ranges[na+4];
1027 /* Now consume following elements while they are contiguous */
1028 while (rlen >= np * sizeof(unsigned int)) {
1029 unsigned long addr, phys;
1031 if (ranges[0] != pci_space)
1033 addr = ((unsigned long)ranges[1] << 32) | ranges[2];
1036 phys = (phys << 32) | ranges[4];
1037 if (addr != pci_addr + size ||
1038 phys != cpu_phys_addr + size)
1041 size += ((unsigned long)ranges[na+3] << 32)
1044 rlen -= np * sizeof(unsigned int);
1047 switch ((pci_space >> 24) & 0x3) {
1048 case 1: /* I/O space */
1049 hose->io_base_phys = cpu_phys_addr;
1050 hose->pci_io_size = size;
1052 res = &hose->io_resource;
1053 res->flags = IORESOURCE_IO;
1054 res->start = pci_addr;
1055 DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose->global_number,
1056 res->start, res->start + size - 1);
1058 case 2: /* memory space */
1060 while (memno < 3 && hose->mem_resources[memno].flags)
1064 hose->pci_mem_offset = cpu_phys_addr - pci_addr;
1066 res = &hose->mem_resources[memno];
1067 res->flags = IORESOURCE_MEM;
1068 res->start = cpu_phys_addr;
1069 DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose->global_number,
1070 res->start, res->start + size - 1);
1075 res->name = dev->full_name;
1076 res->end = res->start + size - 1;
1078 res->sibling = NULL;
1084 void __init pci_setup_phb_io(struct pci_controller *hose, int primary)
1086 unsigned long size = hose->pci_io_size;
1087 unsigned long io_virt_offset;
1088 struct resource *res;
1089 struct device_node *isa_dn;
1091 hose->io_base_virt = reserve_phb_iospace(size);
1092 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1093 hose->global_number, hose->io_base_phys,
1094 (unsigned long) hose->io_base_virt);
1097 pci_io_base = (unsigned long)hose->io_base_virt;
1098 isa_dn = of_find_node_by_type(NULL, "isa");
1100 isa_io_base = pci_io_base;
1101 pci_process_ISA_OF_ranges(isa_dn, hose->io_base_phys,
1102 hose->io_base_virt);
1103 of_node_put(isa_dn);
1109 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
1110 res = &hose->io_resource;
1111 res->start += io_virt_offset;
1112 res->end += io_virt_offset;
1115 void __devinit pci_setup_phb_io_dynamic(struct pci_controller *hose,
1118 unsigned long size = hose->pci_io_size;
1119 unsigned long io_virt_offset;
1120 struct resource *res;
1122 hose->io_base_virt = __ioremap(hose->io_base_phys, size,
1123 _PAGE_NO_CACHE | _PAGE_GUARDED);
1124 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1125 hose->global_number, hose->io_base_phys,
1126 (unsigned long) hose->io_base_virt);
1129 pci_io_base = (unsigned long)hose->io_base_virt;
1131 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
1132 res = &hose->io_resource;
1133 res->start += io_virt_offset;
1134 res->end += io_virt_offset;
1138 static int get_bus_io_range(struct pci_bus *bus, unsigned long *start_phys,
1139 unsigned long *start_virt, unsigned long *size)
1141 struct pci_controller *hose = pci_bus_to_host(bus);
1142 struct pci_bus_region region;
1143 struct resource *res;
1146 res = bus->resource[0];
1147 pcibios_resource_to_bus(bus->self, ®ion, res);
1148 *start_phys = hose->io_base_phys + region.start;
1149 *start_virt = (unsigned long) hose->io_base_virt +
1151 if (region.end > region.start)
1152 *size = region.end - region.start + 1;
1154 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1155 __FUNCTION__, region.start, region.end);
1161 res = &hose->io_resource;
1162 *start_phys = hose->io_base_phys;
1163 *start_virt = (unsigned long) hose->io_base_virt;
1164 if (res->end > res->start)
1165 *size = res->end - res->start + 1;
1167 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1168 __FUNCTION__, res->start, res->end);
1176 int unmap_bus_range(struct pci_bus *bus)
1178 unsigned long start_phys;
1179 unsigned long start_virt;
1183 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
1187 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
1189 if (iounmap_explicit((void __iomem *) start_virt, size))
1194 EXPORT_SYMBOL(unmap_bus_range);
1196 int remap_bus_range(struct pci_bus *bus)
1198 unsigned long start_phys;
1199 unsigned long start_virt;
1203 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
1208 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
1210 if (start_phys == 0)
1212 printk("mapping IO %lx -> %lx, size: %lx\n", start_phys, start_virt, size);
1213 if (__ioremap_explicit(start_phys, start_virt, size,
1214 _PAGE_NO_CACHE | _PAGE_GUARDED))
1219 EXPORT_SYMBOL(remap_bus_range);
1221 void phbs_remap_io(void)
1223 struct pci_controller *hose, *tmp;
1225 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1226 remap_bus_range(hose->bus);
1229 static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
1231 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1232 unsigned long start, end, mask, offset;
1234 if (res->flags & IORESOURCE_IO) {
1235 offset = (unsigned long)hose->io_base_virt - pci_io_base;
1237 start = res->start += offset;
1238 end = res->end += offset;
1240 /* Need to allow IO access to pages that are in the
1242 if (start < MAX_ISA_PORT) {
1243 if (end > MAX_ISA_PORT)
1246 start >>= PAGE_SHIFT;
1249 /* get the range of pages for the map */
1250 mask = ((1 << (end+1)) - 1) ^ ((1 << start) - 1);
1251 io_page_mask |= mask;
1253 } else if (res->flags & IORESOURCE_MEM) {
1254 res->start += hose->pci_mem_offset;
1255 res->end += hose->pci_mem_offset;
1259 void __devinit pcibios_fixup_device_resources(struct pci_dev *dev,
1260 struct pci_bus *bus)
1262 /* Update device resources. */
1265 for (i = 0; i < PCI_NUM_RESOURCES; i++)
1266 if (dev->resource[i].flags)
1267 fixup_resource(&dev->resource[i], dev);
1269 EXPORT_SYMBOL(pcibios_fixup_device_resources);
1272 static void __devinit do_bus_setup(struct pci_bus *bus)
1274 struct pci_dev *dev;
1276 ppc_md.iommu_bus_setup(bus);
1278 list_for_each_entry(dev, &bus->devices, bus_list)
1279 ppc_md.iommu_dev_setup(dev);
1281 if (ppc_md.irq_bus_setup)
1282 ppc_md.irq_bus_setup(bus);
1285 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
1287 struct pci_dev *dev = bus->self;
1289 if (dev && pci_probe_only &&
1290 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1291 /* This is a subordinate bridge */
1293 pci_read_bridge_bases(bus);
1294 pcibios_fixup_device_resources(dev, bus);
1299 if (!pci_probe_only)
1302 list_for_each_entry(dev, &bus->devices, bus_list)
1303 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1304 pcibios_fixup_device_resources(dev, bus);
1306 EXPORT_SYMBOL(pcibios_fixup_bus);
1309 * Reads the interrupt pin to determine if interrupt is use by card.
1310 * If the interrupt is used, then gets the interrupt line from the
1311 * openfirmware and sets it in the pci_dev and pci_config line.
1313 int pci_read_irq_line(struct pci_dev *pci_dev)
1316 struct device_node *node;
1318 pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &intpin);
1322 node = pci_device_to_OF_node(pci_dev);
1326 if (node->n_intrs == 0)
1329 pci_dev->irq = node->intrs[0].line;
1331 pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, pci_dev->irq);
1335 EXPORT_SYMBOL(pci_read_irq_line);
1337 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1338 const struct resource *rsrc,
1339 u64 *start, u64 *end)
1341 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1342 unsigned long offset = 0;
1347 if (rsrc->flags & IORESOURCE_IO)
1348 offset = pci_io_base - (unsigned long)hose->io_base_virt +
1351 *start = rsrc->start + offset;
1352 *end = rsrc->end + offset;
1355 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
1360 struct pci_controller *hose, *tmp;
1361 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1362 if (hose->arch_data == node)
1364 node = node->parent;
1369 #endif /* CONFIG_PPC_MULTIPLATFORM */
1371 unsigned long pci_address_to_pio(phys_addr_t address)
1373 struct pci_controller *hose, *tmp;
1375 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1376 if (address >= hose->io_base_phys &&
1377 address < (hose->io_base_phys + hose->pci_io_size)) {
1378 unsigned long base =
1379 (unsigned long)hose->io_base_virt - pci_io_base;
1380 return base + (address - hose->io_base_phys);
1383 return (unsigned int)-1;
1385 EXPORT_SYMBOL_GPL(pci_address_to_pio);
1388 #define IOBASE_BRIDGE_NUMBER 0
1389 #define IOBASE_MEMORY 1
1391 #define IOBASE_ISA_IO 3
1392 #define IOBASE_ISA_MEM 4
1394 long sys_pciconfig_iobase(long which, unsigned long in_bus,
1395 unsigned long in_devfn)
1397 struct pci_controller* hose;
1398 struct list_head *ln;
1399 struct pci_bus *bus = NULL;
1400 struct device_node *hose_node;
1402 /* Argh ! Please forgive me for that hack, but that's the
1403 * simplest way to get existing XFree to not lockup on some
1404 * G5 machines... So when something asks for bus 0 io base
1405 * (bus 0 is HT root), we return the AGP one instead.
1407 if (machine_is_compatible("MacRISC4"))
1411 /* That syscall isn't quite compatible with PCI domains, but it's
1412 * used on pre-domains setup. We return the first match
1415 for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
1416 bus = pci_bus_b(ln);
1417 if (in_bus >= bus->number && in_bus < (bus->number + bus->subordinate))
1421 if (bus == NULL || bus->sysdata == NULL)
1424 hose_node = (struct device_node *)bus->sysdata;
1425 hose = PCI_DN(hose_node)->phb;
1428 case IOBASE_BRIDGE_NUMBER:
1429 return (long)hose->first_busno;
1431 return (long)hose->pci_mem_offset;
1433 return (long)hose->io_base_phys;
1435 return (long)isa_io_base;
1436 case IOBASE_ISA_MEM: