2 * Derived from "arch/i386/kernel/process.c"
3 * Copyright (C) 1995 Linus Torvalds
5 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
6 * Paul Mackerras (paulus@cs.anu.edu.au)
9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
17 #include <linux/errno.h>
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
21 #include <linux/smp.h>
22 #include <linux/stddef.h>
23 #include <linux/unistd.h>
24 #include <linux/ptrace.h>
25 #include <linux/slab.h>
26 #include <linux/user.h>
27 #include <linux/elf.h>
28 #include <linux/init.h>
29 #include <linux/prctl.h>
30 #include <linux/init_task.h>
31 #include <linux/export.h>
32 #include <linux/kallsyms.h>
33 #include <linux/mqueue.h>
34 #include <linux/hardirq.h>
35 #include <linux/utsname.h>
36 #include <linux/ftrace.h>
37 #include <linux/kernel_stat.h>
38 #include <linux/personality.h>
39 #include <linux/random.h>
40 #include <linux/hw_breakpoint.h>
42 #include <asm/pgtable.h>
43 #include <asm/uaccess.h>
45 #include <asm/processor.h>
48 #include <asm/machdep.h>
50 #include <asm/runlatch.h>
51 #include <asm/syscalls.h>
52 #include <asm/switch_to.h>
54 #include <asm/debug.h>
56 #include <asm/firmware.h>
58 #include <linux/kprobes.h>
59 #include <linux/kdebug.h>
61 /* Transactional Memory debug */
63 #define TM_DEBUG(x...) printk(KERN_INFO x)
65 #define TM_DEBUG(x...) do { } while(0)
68 extern unsigned long _get_SP(void);
71 struct task_struct *last_task_used_math = NULL;
72 struct task_struct *last_task_used_altivec = NULL;
73 struct task_struct *last_task_used_vsx = NULL;
74 struct task_struct *last_task_used_spe = NULL;
78 * Make sure the floating-point register state in the
79 * the thread_struct is up to date for task tsk.
81 void flush_fp_to_thread(struct task_struct *tsk)
83 if (tsk->thread.regs) {
85 * We need to disable preemption here because if we didn't,
86 * another process could get scheduled after the regs->msr
87 * test but before we have finished saving the FP registers
88 * to the thread_struct. That process could take over the
89 * FPU, and then when we get scheduled again we would store
90 * bogus values for the remaining FP registers.
93 if (tsk->thread.regs->msr & MSR_FP) {
96 * This should only ever be called for current or
97 * for a stopped child process. Since we save away
98 * the FP register state on context switch on SMP,
99 * there is something wrong if a stopped child appears
100 * to still have its FP state in the CPU registers.
102 BUG_ON(tsk != current);
109 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
111 void enable_kernel_fp(void)
113 WARN_ON(preemptible());
116 if (current->thread.regs && (current->thread.regs->msr & MSR_FP))
119 giveup_fpu(NULL); /* just enables FP for kernel */
121 giveup_fpu(last_task_used_math);
122 #endif /* CONFIG_SMP */
124 EXPORT_SYMBOL(enable_kernel_fp);
126 #ifdef CONFIG_ALTIVEC
127 void enable_kernel_altivec(void)
129 WARN_ON(preemptible());
132 if (current->thread.regs && (current->thread.regs->msr & MSR_VEC))
133 giveup_altivec(current);
135 giveup_altivec_notask();
137 giveup_altivec(last_task_used_altivec);
138 #endif /* CONFIG_SMP */
140 EXPORT_SYMBOL(enable_kernel_altivec);
143 * Make sure the VMX/Altivec register state in the
144 * the thread_struct is up to date for task tsk.
146 void flush_altivec_to_thread(struct task_struct *tsk)
148 if (tsk->thread.regs) {
150 if (tsk->thread.regs->msr & MSR_VEC) {
152 BUG_ON(tsk != current);
159 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
160 #endif /* CONFIG_ALTIVEC */
164 /* not currently used, but some crazy RAID module might want to later */
165 void enable_kernel_vsx(void)
167 WARN_ON(preemptible());
170 if (current->thread.regs && (current->thread.regs->msr & MSR_VSX))
173 giveup_vsx(NULL); /* just enable vsx for kernel - force */
175 giveup_vsx(last_task_used_vsx);
176 #endif /* CONFIG_SMP */
178 EXPORT_SYMBOL(enable_kernel_vsx);
181 void giveup_vsx(struct task_struct *tsk)
188 void flush_vsx_to_thread(struct task_struct *tsk)
190 if (tsk->thread.regs) {
192 if (tsk->thread.regs->msr & MSR_VSX) {
194 BUG_ON(tsk != current);
201 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
202 #endif /* CONFIG_VSX */
206 void enable_kernel_spe(void)
208 WARN_ON(preemptible());
211 if (current->thread.regs && (current->thread.regs->msr & MSR_SPE))
214 giveup_spe(NULL); /* just enable SPE for kernel - force */
216 giveup_spe(last_task_used_spe);
217 #endif /* __SMP __ */
219 EXPORT_SYMBOL(enable_kernel_spe);
221 void flush_spe_to_thread(struct task_struct *tsk)
223 if (tsk->thread.regs) {
225 if (tsk->thread.regs->msr & MSR_SPE) {
227 BUG_ON(tsk != current);
229 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
235 #endif /* CONFIG_SPE */
239 * If we are doing lazy switching of CPU state (FP, altivec or SPE),
240 * and the current task has some state, discard it.
242 void discard_lazy_cpu_state(void)
245 if (last_task_used_math == current)
246 last_task_used_math = NULL;
247 #ifdef CONFIG_ALTIVEC
248 if (last_task_used_altivec == current)
249 last_task_used_altivec = NULL;
250 #endif /* CONFIG_ALTIVEC */
252 if (last_task_used_vsx == current)
253 last_task_used_vsx = NULL;
254 #endif /* CONFIG_VSX */
256 if (last_task_used_spe == current)
257 last_task_used_spe = NULL;
261 #endif /* CONFIG_SMP */
263 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
264 void do_send_trap(struct pt_regs *regs, unsigned long address,
265 unsigned long error_code, int signal_code, int breakpt)
269 current->thread.trap_nr = signal_code;
270 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
271 11, SIGSEGV) == NOTIFY_STOP)
274 /* Deliver the signal to userspace */
275 info.si_signo = SIGTRAP;
276 info.si_errno = breakpt; /* breakpoint or watchpoint id */
277 info.si_code = signal_code;
278 info.si_addr = (void __user *)address;
279 force_sig_info(SIGTRAP, &info, current);
281 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
282 void do_break (struct pt_regs *regs, unsigned long address,
283 unsigned long error_code)
287 current->thread.trap_nr = TRAP_HWBKPT;
288 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
289 11, SIGSEGV) == NOTIFY_STOP)
292 if (debugger_break_match(regs))
295 /* Clear the breakpoint */
296 hw_breakpoint_disable();
298 /* Deliver the signal to userspace */
299 info.si_signo = SIGTRAP;
301 info.si_code = TRAP_HWBKPT;
302 info.si_addr = (void __user *)address;
303 force_sig_info(SIGTRAP, &info, current);
305 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
307 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
309 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
311 * Set the debug registers back to their default "safe" values.
313 static void set_debug_reg_defaults(struct thread_struct *thread)
315 thread->iac1 = thread->iac2 = 0;
316 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
317 thread->iac3 = thread->iac4 = 0;
319 thread->dac1 = thread->dac2 = 0;
320 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
321 thread->dvc1 = thread->dvc2 = 0;
326 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
328 thread->dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | \
329 DBCR1_IAC3US | DBCR1_IAC4US;
331 * Force Data Address Compare User/Supervisor bits to be User-only
332 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
334 thread->dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
340 static void prime_debug_regs(struct thread_struct *thread)
343 * We could have inherited MSR_DE from userspace, since
344 * it doesn't get cleared on exception entry. Make sure
345 * MSR_DE is clear before we enable any debug events.
347 mtmsr(mfmsr() & ~MSR_DE);
349 mtspr(SPRN_IAC1, thread->iac1);
350 mtspr(SPRN_IAC2, thread->iac2);
351 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
352 mtspr(SPRN_IAC3, thread->iac3);
353 mtspr(SPRN_IAC4, thread->iac4);
355 mtspr(SPRN_DAC1, thread->dac1);
356 mtspr(SPRN_DAC2, thread->dac2);
357 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
358 mtspr(SPRN_DVC1, thread->dvc1);
359 mtspr(SPRN_DVC2, thread->dvc2);
361 mtspr(SPRN_DBCR0, thread->dbcr0);
362 mtspr(SPRN_DBCR1, thread->dbcr1);
364 mtspr(SPRN_DBCR2, thread->dbcr2);
368 * Unless neither the old or new thread are making use of the
369 * debug registers, set the debug registers from the values
370 * stored in the new thread.
372 static void switch_booke_debug_regs(struct thread_struct *new_thread)
374 if ((current->thread.dbcr0 & DBCR0_IDM)
375 || (new_thread->dbcr0 & DBCR0_IDM))
376 prime_debug_regs(new_thread);
378 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
379 #ifndef CONFIG_HAVE_HW_BREAKPOINT
380 static void set_debug_reg_defaults(struct thread_struct *thread)
382 thread->hw_brk.address = 0;
383 thread->hw_brk.type = 0;
384 set_breakpoint(&thread->hw_brk);
386 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
387 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
389 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
390 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
392 mtspr(SPRN_DAC1, dabr);
393 #ifdef CONFIG_PPC_47x
398 #elif defined(CONFIG_PPC_BOOK3S)
399 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
401 mtspr(SPRN_DABR, dabr);
402 if (cpu_has_feature(CPU_FTR_DABRX))
403 mtspr(SPRN_DABRX, dabrx);
407 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
413 static inline int set_dabr(struct arch_hw_breakpoint *brk)
415 unsigned long dabr, dabrx;
417 dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
418 dabrx = ((brk->type >> 3) & 0x7);
421 return ppc_md.set_dabr(dabr, dabrx);
423 return __set_dabr(dabr, dabrx);
426 static inline int set_dawr(struct arch_hw_breakpoint *brk)
428 unsigned long dawr, dawrx, mrd;
432 dawrx = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \
433 << (63 - 58); //* read/write bits */
434 dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \
435 << (63 - 59); //* translate */
436 dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \
437 >> 3; //* PRIM bits */
438 /* dawr length is stored in field MDR bits 48:53. Matches range in
439 doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
441 brk->len is in bytes.
442 This aligns up to double word size, shifts and does the bias.
444 mrd = ((brk->len + 7) >> 3) - 1;
445 dawrx |= (mrd & 0x3f) << (63 - 53);
448 return ppc_md.set_dawr(dawr, dawrx);
449 mtspr(SPRN_DAWR, dawr);
450 mtspr(SPRN_DAWRX, dawrx);
454 int set_breakpoint(struct arch_hw_breakpoint *brk)
456 __get_cpu_var(current_brk) = *brk;
458 if (cpu_has_feature(CPU_FTR_DAWR))
459 return set_dawr(brk);
461 return set_dabr(brk);
465 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
468 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
469 struct arch_hw_breakpoint *b)
471 if (a->address != b->address)
473 if (a->type != b->type)
475 if (a->len != b->len)
479 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
480 static inline void tm_reclaim_task(struct task_struct *tsk)
482 /* We have to work out if we're switching from/to a task that's in the
483 * middle of a transaction.
485 * In switching we need to maintain a 2nd register state as
486 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the
487 * checkpointed (tbegin) state in ckpt_regs and saves the transactional
488 * (current) FPRs into oldtask->thread.transact_fpr[].
490 * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
492 struct thread_struct *thr = &tsk->thread;
497 if (!MSR_TM_ACTIVE(thr->regs->msr))
498 goto out_and_saveregs;
500 /* Stash the original thread MSR, as giveup_fpu et al will
501 * modify it. We hold onto it to see whether the task used
504 thr->tm_orig_msr = thr->regs->msr;
506 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
507 "ccr=%lx, msr=%lx, trap=%lx)\n",
508 tsk->pid, thr->regs->nip,
509 thr->regs->ccr, thr->regs->msr,
512 tm_reclaim(thr, thr->regs->msr, TM_CAUSE_RESCHED);
514 TM_DEBUG("--- tm_reclaim on pid %d complete\n",
518 /* Always save the regs here, even if a transaction's not active.
519 * This context-switches a thread's TM info SPRs. We do it here to
520 * be consistent with the restore path (in recheckpoint) which
521 * cannot happen later in _switch().
526 static inline void tm_recheckpoint_new_task(struct task_struct *new)
530 if (!cpu_has_feature(CPU_FTR_TM))
533 /* Recheckpoint the registers of the thread we're about to switch to.
535 * If the task was using FP, we non-lazily reload both the original and
536 * the speculative FP register states. This is because the kernel
537 * doesn't see if/when a TM rollback occurs, so if we take an FP
538 * unavoidable later, we are unable to determine which set of FP regs
539 * need to be restored.
541 if (!new->thread.regs)
544 /* The TM SPRs are restored here, so that TEXASR.FS can be set
545 * before the trecheckpoint and no explosion occurs.
547 tm_restore_sprs(&new->thread);
549 if (!MSR_TM_ACTIVE(new->thread.regs->msr))
551 msr = new->thread.tm_orig_msr;
552 /* Recheckpoint to restore original checkpointed register state. */
553 TM_DEBUG("*** tm_recheckpoint of pid %d "
554 "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
555 new->pid, new->thread.regs->msr, msr);
557 /* This loads the checkpointed FP/VEC state, if used */
558 tm_recheckpoint(&new->thread, msr);
560 /* This loads the speculative FP/VEC state, if used */
562 do_load_up_transact_fpu(&new->thread);
563 new->thread.regs->msr |=
564 (MSR_FP | new->thread.fpexc_mode);
566 #ifdef CONFIG_ALTIVEC
568 do_load_up_transact_altivec(&new->thread);
569 new->thread.regs->msr |= MSR_VEC;
572 /* We may as well turn on VSX too since all the state is restored now */
574 new->thread.regs->msr |= MSR_VSX;
576 TM_DEBUG("*** tm_recheckpoint of pid %d complete "
577 "(kernel msr 0x%lx)\n",
581 static inline void __switch_to_tm(struct task_struct *prev)
583 if (cpu_has_feature(CPU_FTR_TM)) {
585 tm_reclaim_task(prev);
589 #define tm_recheckpoint_new_task(new)
590 #define __switch_to_tm(prev)
591 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
593 struct task_struct *__switch_to(struct task_struct *prev,
594 struct task_struct *new)
596 struct thread_struct *new_thread, *old_thread;
598 struct task_struct *last;
599 #ifdef CONFIG_PPC_BOOK3S_64
600 struct ppc64_tlb_batch *batch;
603 /* Back up the TAR across context switches.
604 * Note that the TAR is not available for use in the kernel. (To
605 * provide this, the TAR should be backed up/restored on exception
606 * entry/exit instead, and be in pt_regs. FIXME, this should be in
607 * pt_regs anyway (for debug).)
608 * Save the TAR here before we do treclaim/trecheckpoint as these
609 * will change the TAR.
611 save_tar(&prev->thread);
613 __switch_to_tm(prev);
616 /* avoid complexity of lazy save/restore of fpu
617 * by just saving it every time we switch out if
618 * this task used the fpu during the last quantum.
620 * If it tries to use the fpu again, it'll trap and
621 * reload its fp regs. So we don't have to do a restore
622 * every switch, just a save.
625 if (prev->thread.regs && (prev->thread.regs->msr & MSR_FP))
627 #ifdef CONFIG_ALTIVEC
629 * If the previous thread used altivec in the last quantum
630 * (thus changing altivec regs) then save them.
631 * We used to check the VRSAVE register but not all apps
632 * set it, so we don't rely on it now (and in fact we need
633 * to save & restore VSCR even if VRSAVE == 0). -- paulus
635 * On SMP we always save/restore altivec regs just to avoid the
636 * complexity of changing processors.
639 if (prev->thread.regs && (prev->thread.regs->msr & MSR_VEC))
640 giveup_altivec(prev);
641 #endif /* CONFIG_ALTIVEC */
643 if (prev->thread.regs && (prev->thread.regs->msr & MSR_VSX))
644 /* VMX and FPU registers are already save here */
646 #endif /* CONFIG_VSX */
649 * If the previous thread used spe in the last quantum
650 * (thus changing spe regs) then save them.
652 * On SMP we always save/restore spe regs just to avoid the
653 * complexity of changing processors.
655 if ((prev->thread.regs && (prev->thread.regs->msr & MSR_SPE)))
657 #endif /* CONFIG_SPE */
659 #else /* CONFIG_SMP */
660 #ifdef CONFIG_ALTIVEC
661 /* Avoid the trap. On smp this this never happens since
662 * we don't set last_task_used_altivec -- Cort
664 if (new->thread.regs && last_task_used_altivec == new)
665 new->thread.regs->msr |= MSR_VEC;
666 #endif /* CONFIG_ALTIVEC */
668 if (new->thread.regs && last_task_used_vsx == new)
669 new->thread.regs->msr |= MSR_VSX;
670 #endif /* CONFIG_VSX */
672 /* Avoid the trap. On smp this this never happens since
673 * we don't set last_task_used_spe
675 if (new->thread.regs && last_task_used_spe == new)
676 new->thread.regs->msr |= MSR_SPE;
677 #endif /* CONFIG_SPE */
679 #endif /* CONFIG_SMP */
681 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
682 switch_booke_debug_regs(&new->thread);
685 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
688 #ifndef CONFIG_HAVE_HW_BREAKPOINT
689 if (unlikely(hw_brk_match(&__get_cpu_var(current_brk), &new->thread.hw_brk)))
690 set_breakpoint(&new->thread.hw_brk);
691 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
695 new_thread = &new->thread;
696 old_thread = ¤t->thread;
700 * Collect processor utilization data per process
702 if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
703 struct cpu_usage *cu = &__get_cpu_var(cpu_usage_array);
704 long unsigned start_tb, current_tb;
705 start_tb = old_thread->start_tb;
706 cu->current_tb = current_tb = mfspr(SPRN_PURR);
707 old_thread->accum_tb += (current_tb - start_tb);
708 new_thread->start_tb = current_tb;
710 #endif /* CONFIG_PPC64 */
712 #ifdef CONFIG_PPC_BOOK3S_64
713 batch = &__get_cpu_var(ppc64_tlb_batch);
715 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
717 __flush_tlb_pending(batch);
720 #endif /* CONFIG_PPC_BOOK3S_64 */
722 local_irq_save(flags);
725 * We can't take a PMU exception inside _switch() since there is a
726 * window where the kernel stack SLB and the kernel stack are out
727 * of sync. Hard disable here.
731 tm_recheckpoint_new_task(new);
733 last = _switch(old_thread, new_thread);
735 #ifdef CONFIG_PPC_BOOK3S_64
736 if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
737 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
738 batch = &__get_cpu_var(ppc64_tlb_batch);
741 #endif /* CONFIG_PPC_BOOK3S_64 */
743 local_irq_restore(flags);
748 static int instructions_to_print = 16;
750 static void show_instructions(struct pt_regs *regs)
753 unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
756 printk("Instruction dump:");
758 for (i = 0; i < instructions_to_print; i++) {
764 #if !defined(CONFIG_BOOKE)
765 /* If executing with the IMMU off, adjust pc rather
766 * than print XXXXXXXX.
768 if (!(regs->msr & MSR_IR))
769 pc = (unsigned long)phys_to_virt(pc);
772 /* We use __get_user here *only* to avoid an OOPS on a
773 * bad address because the pc *should* only be a
776 if (!__kernel_text_address(pc) ||
777 __get_user(instr, (unsigned int __user *)pc)) {
778 printk(KERN_CONT "XXXXXXXX ");
781 printk(KERN_CONT "<%08x> ", instr);
783 printk(KERN_CONT "%08x ", instr);
792 static struct regbit {
796 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
825 static void printbits(unsigned long val, struct regbit *bits)
827 const char *sep = "";
830 for (; bits->bit; ++bits)
831 if (val & bits->bit) {
832 printk("%s%s", sep, bits->name);
840 #define REGS_PER_LINE 4
841 #define LAST_VOLATILE 13
844 #define REGS_PER_LINE 8
845 #define LAST_VOLATILE 12
848 void show_regs(struct pt_regs * regs)
852 show_regs_print_info(KERN_DEFAULT);
854 printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
855 regs->nip, regs->link, regs->ctr);
856 printk("REGS: %p TRAP: %04lx %s (%s)\n",
857 regs, regs->trap, print_tainted(), init_utsname()->release);
858 printk("MSR: "REG" ", regs->msr);
859 printbits(regs->msr, msr_bits);
860 printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer);
862 printk("SOFTE: %ld\n", regs->softe);
865 if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
866 printk("CFAR: "REG"\n", regs->orig_gpr3);
867 if (trap == 0x300 || trap == 0x600)
868 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
869 printk("DEAR: "REG", ESR: "REG"\n", regs->dar, regs->dsisr);
871 printk("DAR: "REG", DSISR: %08lx\n", regs->dar, regs->dsisr);
874 for (i = 0; i < 32; i++) {
875 if ((i % REGS_PER_LINE) == 0)
876 printk("\nGPR%02d: ", i);
877 printk(REG " ", regs->gpr[i]);
878 if (i == LAST_VOLATILE && !FULL_REGS(regs))
882 #ifdef CONFIG_KALLSYMS
884 * Lookup NIP late so we have the best change of getting the
885 * above info out without failing
887 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
888 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
890 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
891 printk("PACATMSCRATCH [%llx]\n", get_paca()->tm_scratch);
893 show_stack(current, (unsigned long *) regs->gpr[1]);
894 if (!user_mode(regs))
895 show_instructions(regs);
898 void exit_thread(void)
900 discard_lazy_cpu_state();
903 void flush_thread(void)
905 discard_lazy_cpu_state();
907 #ifdef CONFIG_HAVE_HW_BREAKPOINT
908 flush_ptrace_hw_breakpoint(current);
909 #else /* CONFIG_HAVE_HW_BREAKPOINT */
910 set_debug_reg_defaults(¤t->thread);
911 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
915 release_thread(struct task_struct *t)
920 * this gets called so that we can store coprocessor state into memory and
921 * copy the current task into the new thread.
923 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
925 flush_fp_to_thread(src);
926 flush_altivec_to_thread(src);
927 flush_vsx_to_thread(src);
928 flush_spe_to_thread(src);
940 extern unsigned long dscr_default; /* defined in arch/powerpc/kernel/sysfs.c */
942 int copy_thread(unsigned long clone_flags, unsigned long usp,
943 unsigned long arg, struct task_struct *p)
945 struct pt_regs *childregs, *kregs;
946 extern void ret_from_fork(void);
947 extern void ret_from_kernel_thread(void);
949 unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
952 sp -= sizeof(struct pt_regs);
953 childregs = (struct pt_regs *) sp;
954 if (unlikely(p->flags & PF_KTHREAD)) {
955 struct thread_info *ti = (void *)task_stack_page(p);
956 memset(childregs, 0, sizeof(struct pt_regs));
957 childregs->gpr[1] = sp + sizeof(struct pt_regs);
958 childregs->gpr[14] = usp; /* function */
960 clear_tsk_thread_flag(p, TIF_32BIT);
961 childregs->softe = 1;
963 childregs->gpr[15] = arg;
964 p->thread.regs = NULL; /* no user register state */
965 ti->flags |= _TIF_RESTOREALL;
966 f = ret_from_kernel_thread;
968 struct pt_regs *regs = current_pt_regs();
969 CHECK_FULL_REGS(regs);
972 childregs->gpr[1] = usp;
973 p->thread.regs = childregs;
974 childregs->gpr[3] = 0; /* Result from fork() */
975 if (clone_flags & CLONE_SETTLS) {
977 if (!is_32bit_task())
978 childregs->gpr[13] = childregs->gpr[6];
981 childregs->gpr[2] = childregs->gpr[6];
986 sp -= STACK_FRAME_OVERHEAD;
989 * The way this works is that at some point in the future
990 * some task will call _switch to switch to the new task.
991 * That will pop off the stack frame created below and start
992 * the new task running at ret_from_fork. The new task will
993 * do some house keeping and then return from the fork or clone
994 * system call, using the stack frame created above.
996 ((unsigned long *)sp)[0] = 0;
997 sp -= sizeof(struct pt_regs);
998 kregs = (struct pt_regs *) sp;
999 sp -= STACK_FRAME_OVERHEAD;
1001 p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
1002 _ALIGN_UP(sizeof(struct thread_info), 16);
1004 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1005 p->thread.ptrace_bps[0] = NULL;
1008 #ifdef CONFIG_PPC_STD_MMU_64
1009 if (mmu_has_feature(MMU_FTR_SLB)) {
1010 unsigned long sp_vsid;
1011 unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1013 if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1014 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1015 << SLB_VSID_SHIFT_1T;
1017 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1019 sp_vsid |= SLB_VSID_KERNEL | llp;
1020 p->thread.ksp_vsid = sp_vsid;
1022 #endif /* CONFIG_PPC_STD_MMU_64 */
1024 if (cpu_has_feature(CPU_FTR_DSCR)) {
1025 p->thread.dscr_inherit = current->thread.dscr_inherit;
1026 p->thread.dscr = current->thread.dscr;
1028 if (cpu_has_feature(CPU_FTR_HAS_PPR))
1029 p->thread.ppr = INIT_PPR;
1032 * The PPC64 ABI makes use of a TOC to contain function
1033 * pointers. The function (ret_from_except) is actually a pointer
1034 * to the TOC entry. The first entry is a pointer to the actual
1038 kregs->nip = *((unsigned long *)f);
1040 kregs->nip = (unsigned long)f;
1046 * Set up a thread for executing a new program
1048 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1051 unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1055 * If we exec out of a kernel thread then thread.regs will not be
1058 if (!current->thread.regs) {
1059 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1060 current->thread.regs = regs - 1;
1063 memset(regs->gpr, 0, sizeof(regs->gpr));
1071 * We have just cleared all the nonvolatile GPRs, so make
1072 * FULL_REGS(regs) return true. This is necessary to allow
1073 * ptrace to examine the thread immediately after exec.
1080 regs->msr = MSR_USER;
1082 if (!is_32bit_task()) {
1083 unsigned long entry, toc;
1085 /* start is a relocated pointer to the function descriptor for
1086 * the elf _start routine. The first entry in the function
1087 * descriptor is the entry address of _start and the second
1088 * entry is the TOC value we need to use.
1090 __get_user(entry, (unsigned long __user *)start);
1091 __get_user(toc, (unsigned long __user *)start+1);
1093 /* Check whether the e_entry function descriptor entries
1094 * need to be relocated before we can use them.
1096 if (load_addr != 0) {
1102 regs->msr = MSR_USER64;
1106 regs->msr = MSR_USER32;
1109 discard_lazy_cpu_state();
1111 current->thread.used_vsr = 0;
1113 memset(current->thread.fpr, 0, sizeof(current->thread.fpr));
1114 current->thread.fpscr.val = 0;
1115 #ifdef CONFIG_ALTIVEC
1116 memset(current->thread.vr, 0, sizeof(current->thread.vr));
1117 memset(¤t->thread.vscr, 0, sizeof(current->thread.vscr));
1118 current->thread.vscr.u[3] = 0x00010000; /* Java mode disabled */
1119 current->thread.vrsave = 0;
1120 current->thread.used_vr = 0;
1121 #endif /* CONFIG_ALTIVEC */
1123 memset(current->thread.evr, 0, sizeof(current->thread.evr));
1124 current->thread.acc = 0;
1125 current->thread.spefscr = 0;
1126 current->thread.used_spe = 0;
1127 #endif /* CONFIG_SPE */
1128 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1129 if (cpu_has_feature(CPU_FTR_TM))
1130 regs->msr |= MSR_TM;
1131 current->thread.tm_tfhar = 0;
1132 current->thread.tm_texasr = 0;
1133 current->thread.tm_tfiar = 0;
1134 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1137 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1138 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1140 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1142 struct pt_regs *regs = tsk->thread.regs;
1144 /* This is a bit hairy. If we are an SPE enabled processor
1145 * (have embedded fp) we store the IEEE exception enable flags in
1146 * fpexc_mode. fpexc_mode is also used for setting FP exception
1147 * mode (asyn, precise, disabled) for 'Classic' FP. */
1148 if (val & PR_FP_EXC_SW_ENABLE) {
1150 if (cpu_has_feature(CPU_FTR_SPE)) {
1151 tsk->thread.fpexc_mode = val &
1152 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1162 /* on a CONFIG_SPE this does not hurt us. The bits that
1163 * __pack_fe01 use do not overlap with bits used for
1164 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits
1165 * on CONFIG_SPE implementations are reserved so writing to
1166 * them does not change anything */
1167 if (val > PR_FP_EXC_PRECISE)
1169 tsk->thread.fpexc_mode = __pack_fe01(val);
1170 if (regs != NULL && (regs->msr & MSR_FP) != 0)
1171 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1172 | tsk->thread.fpexc_mode;
1176 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1180 if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1182 if (cpu_has_feature(CPU_FTR_SPE))
1183 val = tsk->thread.fpexc_mode;
1190 val = __unpack_fe01(tsk->thread.fpexc_mode);
1191 return put_user(val, (unsigned int __user *) adr);
1194 int set_endian(struct task_struct *tsk, unsigned int val)
1196 struct pt_regs *regs = tsk->thread.regs;
1198 if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1199 (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1205 if (val == PR_ENDIAN_BIG)
1206 regs->msr &= ~MSR_LE;
1207 else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1208 regs->msr |= MSR_LE;
1215 int get_endian(struct task_struct *tsk, unsigned long adr)
1217 struct pt_regs *regs = tsk->thread.regs;
1220 if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1221 !cpu_has_feature(CPU_FTR_REAL_LE))
1227 if (regs->msr & MSR_LE) {
1228 if (cpu_has_feature(CPU_FTR_REAL_LE))
1229 val = PR_ENDIAN_LITTLE;
1231 val = PR_ENDIAN_PPC_LITTLE;
1233 val = PR_ENDIAN_BIG;
1235 return put_user(val, (unsigned int __user *)adr);
1238 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1240 tsk->thread.align_ctl = val;
1244 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1246 return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1249 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1250 unsigned long nbytes)
1252 unsigned long stack_page;
1253 unsigned long cpu = task_cpu(p);
1256 * Avoid crashing if the stack has overflowed and corrupted
1257 * task_cpu(p), which is in the thread_info struct.
1259 if (cpu < NR_CPUS && cpu_possible(cpu)) {
1260 stack_page = (unsigned long) hardirq_ctx[cpu];
1261 if (sp >= stack_page + sizeof(struct thread_struct)
1262 && sp <= stack_page + THREAD_SIZE - nbytes)
1265 stack_page = (unsigned long) softirq_ctx[cpu];
1266 if (sp >= stack_page + sizeof(struct thread_struct)
1267 && sp <= stack_page + THREAD_SIZE - nbytes)
1273 int validate_sp(unsigned long sp, struct task_struct *p,
1274 unsigned long nbytes)
1276 unsigned long stack_page = (unsigned long)task_stack_page(p);
1278 if (sp >= stack_page + sizeof(struct thread_struct)
1279 && sp <= stack_page + THREAD_SIZE - nbytes)
1282 return valid_irq_stack(sp, p, nbytes);
1285 EXPORT_SYMBOL(validate_sp);
1287 unsigned long get_wchan(struct task_struct *p)
1289 unsigned long ip, sp;
1292 if (!p || p == current || p->state == TASK_RUNNING)
1296 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1300 sp = *(unsigned long *)sp;
1301 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1304 ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
1305 if (!in_sched_functions(ip))
1308 } while (count++ < 16);
1312 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
1314 void show_stack(struct task_struct *tsk, unsigned long *stack)
1316 unsigned long sp, ip, lr, newsp;
1319 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1320 int curr_frame = current->curr_ret_stack;
1321 extern void return_to_handler(void);
1322 unsigned long rth = (unsigned long)return_to_handler;
1323 unsigned long mrth = -1;
1325 extern void mod_return_to_handler(void);
1326 rth = *(unsigned long *)rth;
1327 mrth = (unsigned long)mod_return_to_handler;
1328 mrth = *(unsigned long *)mrth;
1332 sp = (unsigned long) stack;
1337 asm("mr %0,1" : "=r" (sp));
1339 sp = tsk->thread.ksp;
1343 printk("Call Trace:\n");
1345 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
1348 stack = (unsigned long *) sp;
1350 ip = stack[STACK_FRAME_LR_SAVE];
1351 if (!firstframe || ip != lr) {
1352 printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
1353 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1354 if ((ip == rth || ip == mrth) && curr_frame >= 0) {
1356 (void *)current->ret_stack[curr_frame].ret);
1361 printk(" (unreliable)");
1367 * See if this is an exception frame.
1368 * We look for the "regshere" marker in the current frame.
1370 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
1371 && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
1372 struct pt_regs *regs = (struct pt_regs *)
1373 (sp + STACK_FRAME_OVERHEAD);
1375 printk("--- Exception: %lx at %pS\n LR = %pS\n",
1376 regs->trap, (void *)regs->nip, (void *)lr);
1381 } while (count++ < kstack_depth_to_print);
1385 /* Called with hard IRQs off */
1386 void notrace __ppc64_runlatch_on(void)
1388 struct thread_info *ti = current_thread_info();
1391 ctrl = mfspr(SPRN_CTRLF);
1392 ctrl |= CTRL_RUNLATCH;
1393 mtspr(SPRN_CTRLT, ctrl);
1395 ti->local_flags |= _TLF_RUNLATCH;
1398 /* Called with hard IRQs off */
1399 void notrace __ppc64_runlatch_off(void)
1401 struct thread_info *ti = current_thread_info();
1404 ti->local_flags &= ~_TLF_RUNLATCH;
1406 ctrl = mfspr(SPRN_CTRLF);
1407 ctrl &= ~CTRL_RUNLATCH;
1408 mtspr(SPRN_CTRLT, ctrl);
1410 #endif /* CONFIG_PPC64 */
1412 unsigned long arch_align_stack(unsigned long sp)
1414 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
1415 sp -= get_random_int() & ~PAGE_MASK;
1419 static inline unsigned long brk_rnd(void)
1421 unsigned long rnd = 0;
1423 /* 8MB for 32bit, 1GB for 64bit */
1424 if (is_32bit_task())
1425 rnd = (long)(get_random_int() % (1<<(23-PAGE_SHIFT)));
1427 rnd = (long)(get_random_int() % (1<<(30-PAGE_SHIFT)));
1429 return rnd << PAGE_SHIFT;
1432 unsigned long arch_randomize_brk(struct mm_struct *mm)
1434 unsigned long base = mm->brk;
1437 #ifdef CONFIG_PPC_STD_MMU_64
1439 * If we are using 1TB segments and we are allowed to randomise
1440 * the heap, we can put it above 1TB so it is backed by a 1TB
1441 * segment. Otherwise the heap will be in the bottom 1TB
1442 * which always uses 256MB segments and this may result in a
1443 * performance penalty.
1445 if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
1446 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
1449 ret = PAGE_ALIGN(base + brk_rnd());
1457 unsigned long randomize_et_dyn(unsigned long base)
1459 unsigned long ret = PAGE_ALIGN(base + brk_rnd());