3 * Common boot and setup code.
5 * Copyright (C) 2001 PPC64 Team, IBM Corp
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
15 #include <linux/export.h>
16 #include <linux/string.h>
17 #include <linux/sched.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/reboot.h>
21 #include <linux/delay.h>
22 #include <linux/initrd.h>
23 #include <linux/seq_file.h>
24 #include <linux/ioport.h>
25 #include <linux/console.h>
26 #include <linux/utsname.h>
27 #include <linux/tty.h>
28 #include <linux/root_dev.h>
29 #include <linux/notifier.h>
30 #include <linux/cpu.h>
31 #include <linux/unistd.h>
32 #include <linux/serial.h>
33 #include <linux/serial_8250.h>
34 #include <linux/bootmem.h>
35 #include <linux/pci.h>
36 #include <linux/lockdep.h>
37 #include <linux/memblock.h>
38 #include <linux/memory.h>
39 #include <linux/nmi.h>
42 #include <asm/kdump.h>
44 #include <asm/processor.h>
45 #include <asm/pgtable.h>
48 #include <asm/machdep.h>
51 #include <asm/cputable.h>
52 #include <asm/dt_cpu_ftrs.h>
53 #include <asm/sections.h>
54 #include <asm/btext.h>
55 #include <asm/nvram.h>
56 #include <asm/setup.h>
58 #include <asm/iommu.h>
59 #include <asm/serial.h>
60 #include <asm/cache.h>
63 #include <asm/firmware.h>
66 #include <asm/kexec.h>
67 #include <asm/code-patching.h>
68 #include <asm/livepatch.h>
70 #include <asm/cputhreads.h>
73 #define DBG(fmt...) udbg_printf(fmt)
78 int spinning_secondaries;
81 struct ppc64_caches ppc64_caches = {
91 EXPORT_SYMBOL_GPL(ppc64_caches);
93 #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP)
94 void __init setup_tlb_core_data(void)
98 BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0);
100 for_each_possible_cpu(cpu) {
101 int first = cpu_first_thread_sibling(cpu);
104 * If we boot via kdump on a non-primary thread,
105 * make sure we point at the thread that actually
108 if (cpu_first_thread_sibling(boot_cpuid) == first)
111 paca[cpu].tcd_ptr = &paca[first].tcd;
114 * If we have threads, we need either tlbsrx.
115 * or e6500 tablewalk mode, or else TLB handlers
116 * will be racy and could produce duplicate entries.
117 * Should we panic instead?
119 WARN_ONCE(smt_enabled_at_boot >= 2 &&
120 !mmu_has_feature(MMU_FTR_USE_TLBRSRV) &&
121 book3e_htw_mode != PPC_HTW_E6500,
122 "%s: unsupported MMU configuration\n", __func__);
129 static char *smt_enabled_cmdline;
131 /* Look for ibm,smt-enabled OF option */
132 void __init check_smt_enabled(void)
134 struct device_node *dn;
135 const char *smt_option;
137 /* Default to enabling all threads */
138 smt_enabled_at_boot = threads_per_core;
140 /* Allow the command line to overrule the OF option */
141 if (smt_enabled_cmdline) {
142 if (!strcmp(smt_enabled_cmdline, "on"))
143 smt_enabled_at_boot = threads_per_core;
144 else if (!strcmp(smt_enabled_cmdline, "off"))
145 smt_enabled_at_boot = 0;
150 rc = kstrtoint(smt_enabled_cmdline, 10, &smt);
152 smt_enabled_at_boot =
153 min(threads_per_core, smt);
156 dn = of_find_node_by_path("/options");
158 smt_option = of_get_property(dn, "ibm,smt-enabled",
162 if (!strcmp(smt_option, "on"))
163 smt_enabled_at_boot = threads_per_core;
164 else if (!strcmp(smt_option, "off"))
165 smt_enabled_at_boot = 0;
173 /* Look for smt-enabled= cmdline option */
174 static int __init early_smt_enabled(char *p)
176 smt_enabled_cmdline = p;
179 early_param("smt-enabled", early_smt_enabled);
181 #endif /* CONFIG_SMP */
183 /** Fix up paca fields required for the boot cpu */
184 static void __init fixup_boot_paca(void)
186 /* The boot cpu is started */
187 get_paca()->cpu_start = 1;
188 /* Allow percpu accesses to work until we setup percpu data */
189 get_paca()->data_offset = 0;
192 static void __init configure_exceptions(void)
195 * Setup the trampolines from the lowmem exception vectors
196 * to the kdump kernel when not using a relocatable kernel.
198 setup_kdump_trampoline();
200 /* Under a PAPR hypervisor, we need hypercalls */
201 if (firmware_has_feature(FW_FEATURE_SET_MODE)) {
202 /* Enable AIL if possible */
203 pseries_enable_reloc_on_exc();
206 * Tell the hypervisor that we want our exceptions to
207 * be taken in little endian mode.
209 * We don't call this for big endian as our calling convention
210 * makes us always enter in BE, and the call may fail under
211 * some circumstances with kdump.
213 #ifdef __LITTLE_ENDIAN__
214 pseries_little_endian_exceptions();
217 /* Set endian mode using OPAL */
218 if (firmware_has_feature(FW_FEATURE_OPAL))
219 opal_configure_cores();
221 /* AIL on native is done in cpu_ready_for_interrupts() */
225 static void cpu_ready_for_interrupts(void)
228 * Enable AIL if supported, and we are in hypervisor mode. This
229 * is called once for every processor.
231 * If we are not in hypervisor mode the job is done once for
232 * the whole partition in configure_exceptions().
234 if (cpu_has_feature(CPU_FTR_HVMODE) &&
235 cpu_has_feature(CPU_FTR_ARCH_207S)) {
236 unsigned long lpcr = mfspr(SPRN_LPCR);
237 mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);
240 /* Set IR and DR in PACA MSR */
241 get_paca()->kernel_msr = MSR_KERNEL;
245 * Early initialization entry point. This is called by head.S
246 * with MMU translation disabled. We rely on the "feature" of
247 * the CPU that ignores the top 2 bits of the address in real
248 * mode so we can access kernel globals normally provided we
249 * only toy with things in the RMO region. From here, we do
250 * some early parsing of the device-tree to setup out MEMBLOCK
251 * data structures, and allocate & initialize the hash table
252 * and segment tables so we can start running with translation
255 * It is this function which will call the probe() callback of
256 * the various platform types and copy the matching one to the
257 * global ppc_md structure. Your platform can eventually do
258 * some very early initializations from the probe() routine, but
259 * this is not recommended, be very careful as, for example, the
260 * device-tree is not accessible via normal means at this point.
263 void __init early_setup(unsigned long dt_ptr)
265 static __initdata struct paca_struct boot_paca;
267 /* -------- printk is _NOT_ safe to use here ! ------- */
269 /* Try new device tree based feature discovery ... */
270 if (!dt_cpu_ftrs_init(__va(dt_ptr)))
271 /* Otherwise use the old style CPU table */
272 identify_cpu(0, mfspr(SPRN_PVR));
274 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */
275 initialise_paca(&boot_paca, 0);
276 setup_paca(&boot_paca);
279 /* -------- printk is now safe to use ------- */
281 /* Enable early debugging if any specified (see udbg.h) */
284 DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr);
287 * Do early initialization using the flattened device
288 * tree, such as retrieving the physical memory map or
289 * calculating/retrieving the hash table size.
291 early_init_devtree(__va(dt_ptr));
293 /* Now we know the logical id of our boot cpu, setup the paca. */
294 setup_paca(&paca[boot_cpuid]);
298 * Configure exception handlers. This include setting up trampolines
299 * if needed, setting exception endian mode, etc...
301 configure_exceptions();
303 /* Apply all the dynamic patching */
304 apply_feature_fixups();
305 setup_feature_keys();
307 /* Initialize the hash table or TLB handling */
311 * At this point, we can let interrupts switch to virtual mode
312 * (the MMU has been setup), so adjust the MSR in the PACA to
313 * have IR and DR set and enable AIL if it exists
315 cpu_ready_for_interrupts();
317 DBG(" <- early_setup()\n");
319 #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
321 * This needs to be done *last* (after the above DBG() even)
323 * Right after we return from this function, we turn on the MMU
324 * which means the real-mode access trick that btext does will
325 * no longer work, it needs to switch to using a real MMU
326 * mapping. This call will ensure that it does
329 #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
333 void early_setup_secondary(void)
335 /* Mark interrupts disabled in PACA */
336 get_paca()->soft_enabled = 0;
338 /* Initialize the hash table or TLB handling */
339 early_init_mmu_secondary();
342 * At this point, we can let interrupts switch to virtual mode
343 * (the MMU has been setup), so adjust the MSR in the PACA to
344 * have IR and DR set.
346 cpu_ready_for_interrupts();
349 #endif /* CONFIG_SMP */
351 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)
352 static bool use_spinloop(void)
354 if (!IS_ENABLED(CONFIG_PPC_BOOK3E))
358 * When book3e boots from kexec, the ePAPR spin table does
361 return of_property_read_bool(of_chosen, "linux,booted-from-kexec");
364 void smp_release_cpus(void)
372 DBG(" -> smp_release_cpus()\n");
374 /* All secondary cpus are spinning on a common spinloop, release them
375 * all now so they can start to spin on their individual paca
376 * spinloops. For non SMP kernels, the secondary cpus never get out
377 * of the common spinloop.
380 ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop
382 *ptr = ppc_function_entry(generic_secondary_smp_init);
384 /* And wait a bit for them to catch up */
385 for (i = 0; i < 100000; i++) {
388 if (spinning_secondaries == 0)
392 DBG("spinning_secondaries = %d\n", spinning_secondaries);
394 DBG(" <- smp_release_cpus()\n");
396 #endif /* CONFIG_SMP || CONFIG_KEXEC_CORE */
399 * Initialize some remaining members of the ppc64_caches and systemcfg
401 * (at least until we get rid of them completely). This is mostly some
402 * cache informations about the CPU that will be used by cache flush
403 * routines and/or provided to userland
406 static void init_cache_info(struct ppc_cache_info *info, u32 size, u32 lsize,
411 info->line_size = lsize;
412 info->block_size = bsize;
413 info->log_block_size = __ilog2(bsize);
415 info->blocks_per_page = PAGE_SIZE / bsize;
417 info->blocks_per_page = 0;
420 info->assoc = 0xffff;
422 info->assoc = size / (sets * lsize);
425 static bool __init parse_cache_info(struct device_node *np,
427 struct ppc_cache_info *info)
429 static const char *ipropnames[] __initdata = {
432 "i-cache-block-size",
435 static const char *dpropnames[] __initdata = {
438 "d-cache-block-size",
441 const char **propnames = icache ? ipropnames : dpropnames;
442 const __be32 *sizep, *lsizep, *bsizep, *setsp;
443 u32 size, lsize, bsize, sets;
448 lsize = bsize = cur_cpu_spec->dcache_bsize;
449 sizep = of_get_property(np, propnames[0], NULL);
451 size = be32_to_cpu(*sizep);
452 setsp = of_get_property(np, propnames[1], NULL);
454 sets = be32_to_cpu(*setsp);
455 bsizep = of_get_property(np, propnames[2], NULL);
456 lsizep = of_get_property(np, propnames[3], NULL);
460 lsize = be32_to_cpu(*lsizep);
462 bsize = be32_to_cpu(*bsizep);
463 if (sizep == NULL || bsizep == NULL || lsizep == NULL)
467 * OF is weird .. it represents fully associative caches
468 * as "1 way" which doesn't make much sense and doesn't
469 * leave room for direct mapped. We'll assume that 0
470 * in OF means direct mapped for that reason.
477 init_cache_info(info, size, lsize, bsize, sets);
482 void __init initialize_cache_info(void)
484 struct device_node *cpu = NULL, *l2, *l3 = NULL;
487 DBG(" -> initialize_cache_info()\n");
490 * All shipping POWER8 machines have a firmware bug that
491 * puts incorrect information in the device-tree. This will
492 * be (hopefully) fixed for future chips but for now hard
493 * code the values if we are running on one of these
495 pvr = PVR_VER(mfspr(SPRN_PVR));
496 if (pvr == PVR_POWER8 || pvr == PVR_POWER8E ||
497 pvr == PVR_POWER8NVL) {
498 /* size lsize blk sets */
499 init_cache_info(&ppc64_caches.l1i, 0x8000, 128, 128, 32);
500 init_cache_info(&ppc64_caches.l1d, 0x10000, 128, 128, 64);
501 init_cache_info(&ppc64_caches.l2, 0x80000, 128, 0, 512);
502 init_cache_info(&ppc64_caches.l3, 0x800000, 128, 0, 8192);
504 cpu = of_find_node_by_type(NULL, "cpu");
507 * We're assuming *all* of the CPUs have the same
508 * d-cache and i-cache sizes... -Peter
511 if (!parse_cache_info(cpu, false, &ppc64_caches.l1d))
512 DBG("Argh, can't find dcache properties !\n");
514 if (!parse_cache_info(cpu, true, &ppc64_caches.l1i))
515 DBG("Argh, can't find icache properties !\n");
518 * Try to find the L2 and L3 if any. Assume they are
519 * unified and use the D-side properties.
521 l2 = of_find_next_cache_node(cpu);
524 parse_cache_info(l2, false, &ppc64_caches.l2);
525 l3 = of_find_next_cache_node(l2);
529 parse_cache_info(l3, false, &ppc64_caches.l3);
534 /* For use by binfmt_elf */
535 dcache_bsize = ppc64_caches.l1d.block_size;
536 icache_bsize = ppc64_caches.l1i.block_size;
538 cur_cpu_spec->dcache_bsize = dcache_bsize;
539 cur_cpu_spec->icache_bsize = icache_bsize;
541 DBG(" <- initialize_cache_info()\n");
544 /* This returns the limit below which memory accesses to the linear
545 * mapping are guarnateed not to cause a TLB or SLB miss. This is
546 * used to allocate interrupt or emergency stacks for which our
547 * exception entry path doesn't deal with being interrupted.
549 static __init u64 safe_stack_limit(void)
551 #ifdef CONFIG_PPC_BOOK3E
552 /* Freescale BookE bolts the entire linear mapping */
553 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E))
554 return linear_map_top;
555 /* Other BookE, we assume the first GB is bolted */
558 /* BookS, the first segment is bolted */
559 if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
560 return 1UL << SID_SHIFT_1T;
561 return 1UL << SID_SHIFT;
565 void __init irqstack_early_init(void)
567 u64 limit = safe_stack_limit();
571 * Interrupt stacks must be in the first segment since we
572 * cannot afford to take SLB misses on them.
574 for_each_possible_cpu(i) {
575 softirq_ctx[i] = (struct thread_info *)
576 __va(memblock_alloc_base(THREAD_SIZE,
577 THREAD_SIZE, limit));
578 hardirq_ctx[i] = (struct thread_info *)
579 __va(memblock_alloc_base(THREAD_SIZE,
580 THREAD_SIZE, limit));
584 #ifdef CONFIG_PPC_BOOK3E
585 void __init exc_lvl_early_init(void)
590 for_each_possible_cpu(i) {
591 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
592 critirq_ctx[i] = (struct thread_info *)__va(sp);
593 paca[i].crit_kstack = __va(sp + THREAD_SIZE);
595 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
596 dbgirq_ctx[i] = (struct thread_info *)__va(sp);
597 paca[i].dbg_kstack = __va(sp + THREAD_SIZE);
599 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
600 mcheckirq_ctx[i] = (struct thread_info *)__va(sp);
601 paca[i].mc_kstack = __va(sp + THREAD_SIZE);
604 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
605 patch_exception(0x040, exc_debug_debug_book3e);
610 * Stack space used when we detect a bad kernel stack pointer, and
611 * early in SMP boots before relocation is enabled. Exclusive emergency
612 * stack for machine checks.
614 void __init emergency_stack_init(void)
620 * Emergency stacks must be under 256MB, we cannot afford to take
621 * SLB misses on them. The ABI also requires them to be 128-byte
624 * Since we use these as temporary stacks during secondary CPU
625 * bringup, we need to get at them in real mode. This means they
626 * must also be within the RMO region.
628 limit = min(safe_stack_limit(), ppc64_rma_size);
630 for_each_possible_cpu(i) {
631 struct thread_info *ti;
632 ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit));
633 klp_init_thread_info(ti);
634 paca[i].emergency_sp = (void *)ti + THREAD_SIZE;
636 #ifdef CONFIG_PPC_BOOK3S_64
637 /* emergency stack for NMI exception handling. */
638 ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit));
639 klp_init_thread_info(ti);
640 paca[i].nmi_emergency_sp = (void *)ti + THREAD_SIZE;
642 /* emergency stack for machine check exception handling. */
643 ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit));
644 klp_init_thread_info(ti);
645 paca[i].mc_emergency_sp = (void *)ti + THREAD_SIZE;
651 #define PCPU_DYN_SIZE ()
653 static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align)
655 return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align,
656 __pa(MAX_DMA_ADDRESS));
659 static void __init pcpu_fc_free(void *ptr, size_t size)
661 free_bootmem(__pa(ptr), size);
664 static int pcpu_cpu_distance(unsigned int from, unsigned int to)
666 if (cpu_to_node(from) == cpu_to_node(to))
667 return LOCAL_DISTANCE;
669 return REMOTE_DISTANCE;
672 unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
673 EXPORT_SYMBOL(__per_cpu_offset);
675 void __init setup_per_cpu_areas(void)
677 const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE;
684 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need
685 * to group units. For larger mappings, use 1M atom which
686 * should be large enough to contain a number of units.
688 if (mmu_linear_psize == MMU_PAGE_4K)
689 atom_size = PAGE_SIZE;
693 rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance,
694 pcpu_fc_alloc, pcpu_fc_free);
696 panic("cannot initialize percpu area (err=%d)", rc);
698 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
699 for_each_possible_cpu(cpu) {
700 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
701 paca[cpu].data_offset = __per_cpu_offset[cpu];
706 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
707 unsigned long memory_block_size_bytes(void)
709 if (ppc_md.memory_block_size)
710 return ppc_md.memory_block_size();
712 return MIN_MEMORY_BLOCK_SIZE;
716 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
717 struct ppc_pci_io ppc_pci_io;
718 EXPORT_SYMBOL(ppc_pci_io);
721 #ifdef CONFIG_HARDLOCKUP_DETECTOR
722 u64 hw_nmi_get_sample_period(int watchdog_thresh)
724 return ppc_proc_freq * watchdog_thresh;
728 * The hardlockup detector breaks PMU event based branches and is likely
729 * to get false positives in KVM guests, so disable it by default.
731 static int __init disable_hardlockup_detector(void)
733 hardlockup_detector_disable();
737 early_initcall(disable_hardlockup_detector);