3 * Common boot and setup code.
5 * Copyright (C) 2001 PPC64 Team, IBM Corp
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
15 #include <linux/export.h>
16 #include <linux/string.h>
17 #include <linux/sched.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/reboot.h>
21 #include <linux/delay.h>
22 #include <linux/initrd.h>
23 #include <linux/seq_file.h>
24 #include <linux/ioport.h>
25 #include <linux/console.h>
26 #include <linux/utsname.h>
27 #include <linux/tty.h>
28 #include <linux/root_dev.h>
29 #include <linux/notifier.h>
30 #include <linux/cpu.h>
31 #include <linux/unistd.h>
32 #include <linux/serial.h>
33 #include <linux/serial_8250.h>
34 #include <linux/bootmem.h>
35 #include <linux/pci.h>
36 #include <linux/lockdep.h>
37 #include <linux/memblock.h>
38 #include <linux/hugetlb.h>
39 #include <linux/memory.h>
40 #include <linux/nmi.h>
43 #include <asm/kdump.h>
45 #include <asm/processor.h>
46 #include <asm/pgtable.h>
49 #include <asm/machdep.h>
52 #include <asm/cputable.h>
53 #include <asm/sections.h>
54 #include <asm/btext.h>
55 #include <asm/nvram.h>
56 #include <asm/setup.h>
58 #include <asm/iommu.h>
59 #include <asm/serial.h>
60 #include <asm/cache.h>
63 #include <asm/firmware.h>
66 #include <asm/kexec.h>
67 #include <asm/mmu_context.h>
68 #include <asm/code-patching.h>
69 #include <asm/kvm_ppc.h>
70 #include <asm/hugetlb.h>
71 #include <asm/livepatch.h>
75 #define DBG(fmt...) udbg_printf(fmt)
80 int spinning_secondaries;
83 /* Pick defaults since we might want to patch instructions
84 * before we've read this from the device tree.
86 struct ppc64_caches ppc64_caches = {
92 EXPORT_SYMBOL_GPL(ppc64_caches);
95 * These are used in binfmt_elf.c to put aux entries on the stack
96 * for each elf executable being started.
102 #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP)
103 static void setup_tlb_core_data(void)
107 BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0);
109 for_each_possible_cpu(cpu) {
110 int first = cpu_first_thread_sibling(cpu);
113 * If we boot via kdump on a non-primary thread,
114 * make sure we point at the thread that actually
117 if (cpu_first_thread_sibling(boot_cpuid) == first)
120 paca[cpu].tcd_ptr = &paca[first].tcd;
123 * If we have threads, we need either tlbsrx.
124 * or e6500 tablewalk mode, or else TLB handlers
125 * will be racy and could produce duplicate entries.
127 if (smt_enabled_at_boot >= 2 &&
128 !mmu_has_feature(MMU_FTR_USE_TLBRSRV) &&
129 book3e_htw_mode != PPC_HTW_E6500) {
130 /* Should we panic instead? */
131 WARN_ONCE("%s: unsupported MMU configuration -- expect problems\n",
137 static void setup_tlb_core_data(void)
144 static char *smt_enabled_cmdline;
146 /* Look for ibm,smt-enabled OF option */
147 static void check_smt_enabled(void)
149 struct device_node *dn;
150 const char *smt_option;
152 /* Default to enabling all threads */
153 smt_enabled_at_boot = threads_per_core;
155 /* Allow the command line to overrule the OF option */
156 if (smt_enabled_cmdline) {
157 if (!strcmp(smt_enabled_cmdline, "on"))
158 smt_enabled_at_boot = threads_per_core;
159 else if (!strcmp(smt_enabled_cmdline, "off"))
160 smt_enabled_at_boot = 0;
165 rc = kstrtoint(smt_enabled_cmdline, 10, &smt);
167 smt_enabled_at_boot =
168 min(threads_per_core, smt);
171 dn = of_find_node_by_path("/options");
173 smt_option = of_get_property(dn, "ibm,smt-enabled",
177 if (!strcmp(smt_option, "on"))
178 smt_enabled_at_boot = threads_per_core;
179 else if (!strcmp(smt_option, "off"))
180 smt_enabled_at_boot = 0;
188 /* Look for smt-enabled= cmdline option */
189 static int __init early_smt_enabled(char *p)
191 smt_enabled_cmdline = p;
194 early_param("smt-enabled", early_smt_enabled);
197 #define check_smt_enabled()
198 #endif /* CONFIG_SMP */
200 /** Fix up paca fields required for the boot cpu */
201 static void fixup_boot_paca(void)
203 /* The boot cpu is started */
204 get_paca()->cpu_start = 1;
205 /* Allow percpu accesses to work until we setup percpu data */
206 get_paca()->data_offset = 0;
209 static void configure_exceptions(void)
212 * Setup the trampolines from the lowmem exception vectors
213 * to the kdump kernel when not using a relocatable kernel.
215 setup_kdump_trampoline();
217 /* Under a PAPR hypervisor, we need hypercalls */
218 if (firmware_has_feature(FW_FEATURE_SET_MODE)) {
219 /* Enable AIL if possible */
220 pseries_enable_reloc_on_exc();
223 * Tell the hypervisor that we want our exceptions to
224 * be taken in little endian mode.
226 * We don't call this for big endian as our calling convention
227 * makes us always enter in BE, and the call may fail under
228 * some circumstances with kdump.
230 #ifdef __LITTLE_ENDIAN__
231 pseries_little_endian_exceptions();
234 /* Set endian mode using OPAL */
235 if (firmware_has_feature(FW_FEATURE_OPAL))
236 opal_configure_cores();
238 /* Enable AIL if supported, and we are in hypervisor mode */
239 if (cpu_has_feature(CPU_FTR_HVMODE) &&
240 cpu_has_feature(CPU_FTR_ARCH_207S)) {
241 unsigned long lpcr = mfspr(SPRN_LPCR);
242 mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);
247 static void cpu_ready_for_interrupts(void)
249 /* Set IR and DR in PACA MSR */
250 get_paca()->kernel_msr = MSR_KERNEL;
254 * Early initialization entry point. This is called by head.S
255 * with MMU translation disabled. We rely on the "feature" of
256 * the CPU that ignores the top 2 bits of the address in real
257 * mode so we can access kernel globals normally provided we
258 * only toy with things in the RMO region. From here, we do
259 * some early parsing of the device-tree to setup out MEMBLOCK
260 * data structures, and allocate & initialize the hash table
261 * and segment tables so we can start running with translation
264 * It is this function which will call the probe() callback of
265 * the various platform types and copy the matching one to the
266 * global ppc_md structure. Your platform can eventually do
267 * some very early initializations from the probe() routine, but
268 * this is not recommended, be very careful as, for example, the
269 * device-tree is not accessible via normal means at this point.
272 void __init early_setup(unsigned long dt_ptr)
274 static __initdata struct paca_struct boot_paca;
276 /* -------- printk is _NOT_ safe to use here ! ------- */
278 /* Identify CPU type */
279 identify_cpu(0, mfspr(SPRN_PVR));
281 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */
282 initialise_paca(&boot_paca, 0);
283 setup_paca(&boot_paca);
286 /* -------- printk is now safe to use ------- */
288 /* Enable early debugging if any specified (see udbg.h) */
291 DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr);
294 * Do early initialization using the flattened device
295 * tree, such as retrieving the physical memory map or
296 * calculating/retrieving the hash table size.
298 early_init_devtree(__va(dt_ptr));
300 /* Now we know the logical id of our boot cpu, setup the paca. */
301 setup_paca(&paca[boot_cpuid]);
304 /* Probe the machine type */
308 * Configure exception handlers. This include setting up trampolines
309 * if needed, setting exception endian mode, etc...
311 configure_exceptions();
313 /* Initialize the hash table or TLB handling */
316 /* Apply all the dynamic patching */
317 apply_feature_fixups();
320 * At this point, we can let interrupts switch to virtual mode
321 * (the MMU has been setup), so adjust the MSR in the PACA to
322 * have IR and DR set and enable AIL if it exists
324 cpu_ready_for_interrupts();
326 DBG(" <- early_setup()\n");
328 #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
330 * This needs to be done *last* (after the above DBG() even)
332 * Right after we return from this function, we turn on the MMU
333 * which means the real-mode access trick that btext does will
334 * no longer work, it needs to switch to using a real MMU
335 * mapping. This call will ensure that it does
338 #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
342 void early_setup_secondary(void)
344 /* Mark interrupts disabled in PACA */
345 get_paca()->soft_enabled = 0;
347 /* Initialize the hash table or TLB handling */
348 early_init_mmu_secondary();
351 * At this point, we can let interrupts switch to virtual mode
352 * (the MMU has been setup), so adjust the MSR in the PACA to
353 * have IR and DR set.
355 cpu_ready_for_interrupts();
358 #endif /* CONFIG_SMP */
360 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
361 static bool use_spinloop(void)
363 if (!IS_ENABLED(CONFIG_PPC_BOOK3E))
367 * When book3e boots from kexec, the ePAPR spin table does
370 return of_property_read_bool(of_chosen, "linux,booted-from-kexec");
373 void smp_release_cpus(void)
381 DBG(" -> smp_release_cpus()\n");
383 /* All secondary cpus are spinning on a common spinloop, release them
384 * all now so they can start to spin on their individual paca
385 * spinloops. For non SMP kernels, the secondary cpus never get out
386 * of the common spinloop.
389 ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop
391 *ptr = ppc_function_entry(generic_secondary_smp_init);
393 /* And wait a bit for them to catch up */
394 for (i = 0; i < 100000; i++) {
397 if (spinning_secondaries == 0)
401 DBG("spinning_secondaries = %d\n", spinning_secondaries);
403 DBG(" <- smp_release_cpus()\n");
405 #endif /* CONFIG_SMP || CONFIG_KEXEC */
408 * Initialize some remaining members of the ppc64_caches and systemcfg
410 * (at least until we get rid of them completely). This is mostly some
411 * cache informations about the CPU that will be used by cache flush
412 * routines and/or provided to userland
414 static void __init initialize_cache_info(void)
416 struct device_node *np;
417 unsigned long num_cpus = 0;
419 DBG(" -> initialize_cache_info()\n");
421 for_each_node_by_type(np, "cpu") {
425 * We're assuming *all* of the CPUs have the same
426 * d-cache and i-cache sizes... -Peter
429 const __be32 *sizep, *lsizep;
433 lsize = cur_cpu_spec->dcache_bsize;
434 sizep = of_get_property(np, "d-cache-size", NULL);
436 size = be32_to_cpu(*sizep);
437 lsizep = of_get_property(np, "d-cache-block-size",
439 /* fallback if block size missing */
441 lsizep = of_get_property(np,
445 lsize = be32_to_cpu(*lsizep);
446 if (sizep == NULL || lsizep == NULL)
447 DBG("Argh, can't find dcache properties ! "
448 "sizep: %p, lsizep: %p\n", sizep, lsizep);
450 ppc64_caches.dsize = size;
451 ppc64_caches.dline_size = lsize;
452 ppc64_caches.log_dline_size = __ilog2(lsize);
453 ppc64_caches.dlines_per_page = PAGE_SIZE / lsize;
456 lsize = cur_cpu_spec->icache_bsize;
457 sizep = of_get_property(np, "i-cache-size", NULL);
459 size = be32_to_cpu(*sizep);
460 lsizep = of_get_property(np, "i-cache-block-size",
463 lsizep = of_get_property(np,
467 lsize = be32_to_cpu(*lsizep);
468 if (sizep == NULL || lsizep == NULL)
469 DBG("Argh, can't find icache properties ! "
470 "sizep: %p, lsizep: %p\n", sizep, lsizep);
472 ppc64_caches.isize = size;
473 ppc64_caches.iline_size = lsize;
474 ppc64_caches.log_iline_size = __ilog2(lsize);
475 ppc64_caches.ilines_per_page = PAGE_SIZE / lsize;
479 DBG(" <- initialize_cache_info()\n");
484 * Do some initial setup of the system. The parameters are those which
485 * were passed in from the bootloader.
487 void __init setup_system(void)
489 DBG(" -> setup_system()\n");
492 * Unflatten the device-tree passed by prom_init or kexec
494 unflatten_device_tree();
497 * Fill the ppc64_caches & systemcfg structures with informations
498 * retrieved from the device-tree.
500 initialize_cache_info();
502 #ifdef CONFIG_PPC_RTAS
504 * Initialize RTAS if available
507 #endif /* CONFIG_PPC_RTAS */
510 * Check if we have an initrd provided via the device-tree
515 * Do some platform specific early initializations, that includes
516 * setting up the hash table pointers. It also sets up some interrupt-mapping
517 * related options that will be used by finish_device_tree()
519 if (ppc_md.init_early)
523 * We can discover serial ports now since the above did setup the
524 * hash table management for us, thus ioremap works. We do that early
525 * so that further code can be debugged
527 find_legacy_serial_ports();
530 * Register early console
532 register_early_udbg_console();
539 smp_setup_cpu_maps();
541 setup_tlb_core_data();
544 * Freescale Book3e parts spin in a loop provided by firmware,
545 * so smp_release_cpus() does nothing for them
547 #if defined(CONFIG_SMP)
548 /* Release secondary cpus out of their spinloops at 0x60 now that
549 * we can map physical -> logical CPU ids
554 pr_info("Starting Linux %s %s\n", init_utsname()->machine,
555 init_utsname()->version);
557 pr_info("-----------------------------------------------------\n");
558 pr_info("ppc64_pft_size = 0x%llx\n", ppc64_pft_size);
559 pr_info("phys_mem_size = 0x%llx\n", memblock_phys_mem_size());
561 if (ppc64_caches.dline_size != 0x80)
562 pr_info("dcache_line_size = 0x%x\n", ppc64_caches.dline_size);
563 if (ppc64_caches.iline_size != 0x80)
564 pr_info("icache_line_size = 0x%x\n", ppc64_caches.iline_size);
566 pr_info("cpu_features = 0x%016lx\n", cur_cpu_spec->cpu_features);
567 pr_info(" possible = 0x%016lx\n", CPU_FTRS_POSSIBLE);
568 pr_info(" always = 0x%016lx\n", CPU_FTRS_ALWAYS);
569 pr_info("cpu_user_features = 0x%08x 0x%08x\n", cur_cpu_spec->cpu_user_features,
570 cur_cpu_spec->cpu_user_features2);
571 pr_info("mmu_features = 0x%08x\n", cur_cpu_spec->mmu_features);
572 pr_info("firmware_features = 0x%016lx\n", powerpc_firmware_features);
574 #ifdef CONFIG_PPC_STD_MMU_64
576 pr_info("htab_address = 0x%p\n", htab_address);
578 pr_info("htab_hash_mask = 0x%lx\n", htab_hash_mask);
581 if (PHYSICAL_START > 0)
582 pr_info("physical_start = 0x%llx\n",
583 (unsigned long long)PHYSICAL_START);
584 pr_info("-----------------------------------------------------\n");
586 DBG(" <- setup_system()\n");
589 /* This returns the limit below which memory accesses to the linear
590 * mapping are guarnateed not to cause a TLB or SLB miss. This is
591 * used to allocate interrupt or emergency stacks for which our
592 * exception entry path doesn't deal with being interrupted.
594 static u64 safe_stack_limit(void)
596 #ifdef CONFIG_PPC_BOOK3E
597 /* Freescale BookE bolts the entire linear mapping */
598 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E))
599 return linear_map_top;
600 /* Other BookE, we assume the first GB is bolted */
603 /* BookS, the first segment is bolted */
604 if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
605 return 1UL << SID_SHIFT_1T;
606 return 1UL << SID_SHIFT;
610 static void __init irqstack_early_init(void)
612 u64 limit = safe_stack_limit();
616 * Interrupt stacks must be in the first segment since we
617 * cannot afford to take SLB misses on them.
619 for_each_possible_cpu(i) {
620 softirq_ctx[i] = (struct thread_info *)
621 __va(memblock_alloc_base(THREAD_SIZE,
622 THREAD_SIZE, limit));
623 hardirq_ctx[i] = (struct thread_info *)
624 __va(memblock_alloc_base(THREAD_SIZE,
625 THREAD_SIZE, limit));
629 #ifdef CONFIG_PPC_BOOK3E
630 static void __init exc_lvl_early_init(void)
635 for_each_possible_cpu(i) {
636 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
637 critirq_ctx[i] = (struct thread_info *)__va(sp);
638 paca[i].crit_kstack = __va(sp + THREAD_SIZE);
640 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
641 dbgirq_ctx[i] = (struct thread_info *)__va(sp);
642 paca[i].dbg_kstack = __va(sp + THREAD_SIZE);
644 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
645 mcheckirq_ctx[i] = (struct thread_info *)__va(sp);
646 paca[i].mc_kstack = __va(sp + THREAD_SIZE);
649 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
650 patch_exception(0x040, exc_debug_debug_book3e);
653 #define exc_lvl_early_init()
657 * Stack space used when we detect a bad kernel stack pointer, and
658 * early in SMP boots before relocation is enabled. Exclusive emergency
659 * stack for machine checks.
661 static void __init emergency_stack_init(void)
667 * Emergency stacks must be under 256MB, we cannot afford to take
668 * SLB misses on them. The ABI also requires them to be 128-byte
671 * Since we use these as temporary stacks during secondary CPU
672 * bringup, we need to get at them in real mode. This means they
673 * must also be within the RMO region.
675 limit = min(safe_stack_limit(), ppc64_rma_size);
677 for_each_possible_cpu(i) {
678 struct thread_info *ti;
679 ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit));
680 klp_init_thread_info(ti);
681 paca[i].emergency_sp = (void *)ti + THREAD_SIZE;
683 #ifdef CONFIG_PPC_BOOK3S_64
684 /* emergency stack for machine check exception handling. */
685 ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit));
686 klp_init_thread_info(ti);
687 paca[i].mc_emergency_sp = (void *)ti + THREAD_SIZE;
693 * Called into from start_kernel this initializes memblock, which is used
694 * to manage page allocation until mem_init is called.
696 void __init setup_arch(char **cmdline_p)
698 *cmdline_p = boot_command_line;
701 * Set cache line size based on type of cpu as a default.
702 * Systems with OF can look in the properties on the cpu node(s)
703 * for a possibly more accurate value.
705 dcache_bsize = ppc64_caches.dline_size;
706 icache_bsize = ppc64_caches.iline_size;
709 /* Reserve large chunks of memory for use by CMA for KVM */
713 * Reserve any gigantic pages requested on the command line.
714 * memblock needs to have been initialized by the time this is
715 * called since this will reserve memory.
717 reserve_hugetlb_gpages();
722 klp_init_thread_info(&init_thread_info);
724 init_mm.start_code = (unsigned long)_stext;
725 init_mm.end_code = (unsigned long) _etext;
726 init_mm.end_data = (unsigned long) _edata;
727 init_mm.brk = klimit;
728 #ifdef CONFIG_PPC_64K_PAGES
729 init_mm.context.pte_frag = NULL;
731 #ifdef CONFIG_SPAPR_TCE_IOMMU
732 mm_iommu_init(&init_mm.context);
734 irqstack_early_init();
735 exc_lvl_early_init();
736 emergency_stack_init();
740 #ifdef CONFIG_DUMMY_CONSOLE
741 conswitchp = &dummy_con;
743 if (ppc_md.setup_arch)
748 /* Initialize the MMU context management stuff */
751 /* Interrupt code needs to be 64K-aligned */
752 if ((unsigned long)_stext & 0xffff)
753 panic("Kernelbase not 64K-aligned (0x%lx)!\n",
754 (unsigned long)_stext);
758 #define PCPU_DYN_SIZE ()
760 static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align)
762 return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align,
763 __pa(MAX_DMA_ADDRESS));
766 static void __init pcpu_fc_free(void *ptr, size_t size)
768 free_bootmem(__pa(ptr), size);
771 static int pcpu_cpu_distance(unsigned int from, unsigned int to)
773 if (cpu_to_node(from) == cpu_to_node(to))
774 return LOCAL_DISTANCE;
776 return REMOTE_DISTANCE;
779 unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
780 EXPORT_SYMBOL(__per_cpu_offset);
782 void __init setup_per_cpu_areas(void)
784 const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE;
791 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need
792 * to group units. For larger mappings, use 1M atom which
793 * should be large enough to contain a number of units.
795 if (mmu_linear_psize == MMU_PAGE_4K)
796 atom_size = PAGE_SIZE;
800 rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance,
801 pcpu_fc_alloc, pcpu_fc_free);
803 panic("cannot initialize percpu area (err=%d)", rc);
805 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
806 for_each_possible_cpu(cpu) {
807 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
808 paca[cpu].data_offset = __per_cpu_offset[cpu];
813 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
814 unsigned long memory_block_size_bytes(void)
816 if (ppc_md.memory_block_size)
817 return ppc_md.memory_block_size();
819 return MIN_MEMORY_BLOCK_SIZE;
823 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
824 struct ppc_pci_io ppc_pci_io;
825 EXPORT_SYMBOL(ppc_pci_io);
828 #ifdef CONFIG_HARDLOCKUP_DETECTOR
829 u64 hw_nmi_get_sample_period(int watchdog_thresh)
831 return ppc_proc_freq * watchdog_thresh;
835 * The hardlockup detector breaks PMU event based branches and is likely
836 * to get false positives in KVM guests, so disable it by default.
838 static int __init disable_hardlockup_detector(void)
840 hardlockup_detector_disable();
844 early_initcall(disable_hardlockup_detector);