3 * Common boot and setup code.
5 * Copyright (C) 2001 PPC64 Team, IBM Corp
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
15 #include <linux/export.h>
16 #include <linux/string.h>
17 #include <linux/sched.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/reboot.h>
21 #include <linux/delay.h>
22 #include <linux/initrd.h>
23 #include <linux/seq_file.h>
24 #include <linux/ioport.h>
25 #include <linux/console.h>
26 #include <linux/utsname.h>
27 #include <linux/tty.h>
28 #include <linux/root_dev.h>
29 #include <linux/notifier.h>
30 #include <linux/cpu.h>
31 #include <linux/unistd.h>
32 #include <linux/serial.h>
33 #include <linux/serial_8250.h>
34 #include <linux/bootmem.h>
35 #include <linux/pci.h>
36 #include <linux/lockdep.h>
37 #include <linux/memblock.h>
38 #include <linux/hugetlb.h>
41 #include <asm/kdump.h>
43 #include <asm/processor.h>
44 #include <asm/pgtable.h>
47 #include <asm/machdep.h>
50 #include <asm/cputable.h>
51 #include <asm/sections.h>
52 #include <asm/btext.h>
53 #include <asm/nvram.h>
54 #include <asm/setup.h>
56 #include <asm/iommu.h>
57 #include <asm/serial.h>
58 #include <asm/cache.h>
61 #include <asm/firmware.h>
64 #include <asm/kexec.h>
65 #include <asm/mmu_context.h>
66 #include <asm/code-patching.h>
67 #include <asm/kvm_ppc.h>
68 #include <asm/hugetlb.h>
69 #include <asm/epapr_hcalls.h>
72 #define DBG(fmt...) udbg_printf(fmt)
77 int spinning_secondaries;
80 /* Pick defaults since we might want to patch instructions
81 * before we've read this from the device tree.
83 struct ppc64_caches ppc64_caches = {
89 EXPORT_SYMBOL_GPL(ppc64_caches);
92 * These are used in binfmt_elf.c to put aux entries on the stack
93 * for each elf executable being started.
99 #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP)
100 static void setup_tlb_core_data(void)
104 BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0);
106 for_each_possible_cpu(cpu) {
107 int first = cpu_first_thread_sibling(cpu);
109 paca[cpu].tcd_ptr = &paca[first].tcd;
112 * If we have threads, we need either tlbsrx.
113 * or e6500 tablewalk mode, or else TLB handlers
114 * will be racy and could produce duplicate entries.
116 if (smt_enabled_at_boot >= 2 &&
117 !mmu_has_feature(MMU_FTR_USE_TLBRSRV) &&
118 book3e_htw_mode != PPC_HTW_E6500) {
119 /* Should we panic instead? */
120 WARN_ONCE("%s: unsupported MMU configuration -- expect problems\n",
126 static void setup_tlb_core_data(void)
133 static char *smt_enabled_cmdline;
135 /* Look for ibm,smt-enabled OF option */
136 static void check_smt_enabled(void)
138 struct device_node *dn;
139 const char *smt_option;
141 /* Default to enabling all threads */
142 smt_enabled_at_boot = threads_per_core;
144 /* Allow the command line to overrule the OF option */
145 if (smt_enabled_cmdline) {
146 if (!strcmp(smt_enabled_cmdline, "on"))
147 smt_enabled_at_boot = threads_per_core;
148 else if (!strcmp(smt_enabled_cmdline, "off"))
149 smt_enabled_at_boot = 0;
154 rc = strict_strtol(smt_enabled_cmdline, 10, &smt);
156 smt_enabled_at_boot =
157 min(threads_per_core, (int)smt);
160 dn = of_find_node_by_path("/options");
162 smt_option = of_get_property(dn, "ibm,smt-enabled",
166 if (!strcmp(smt_option, "on"))
167 smt_enabled_at_boot = threads_per_core;
168 else if (!strcmp(smt_option, "off"))
169 smt_enabled_at_boot = 0;
177 /* Look for smt-enabled= cmdline option */
178 static int __init early_smt_enabled(char *p)
180 smt_enabled_cmdline = p;
183 early_param("smt-enabled", early_smt_enabled);
186 #define check_smt_enabled()
187 #endif /* CONFIG_SMP */
189 /** Fix up paca fields required for the boot cpu */
190 static void fixup_boot_paca(void)
192 /* The boot cpu is started */
193 get_paca()->cpu_start = 1;
194 /* Allow percpu accesses to work until we setup percpu data */
195 get_paca()->data_offset = 0;
198 static void cpu_ready_for_interrupts(void)
200 /* Set IR and DR in PACA MSR */
201 get_paca()->kernel_msr = MSR_KERNEL;
203 /* Enable AIL if supported */
204 if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
205 unsigned long lpcr = mfspr(SPRN_LPCR);
206 mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);
211 * Early initialization entry point. This is called by head.S
212 * with MMU translation disabled. We rely on the "feature" of
213 * the CPU that ignores the top 2 bits of the address in real
214 * mode so we can access kernel globals normally provided we
215 * only toy with things in the RMO region. From here, we do
216 * some early parsing of the device-tree to setup out MEMBLOCK
217 * data structures, and allocate & initialize the hash table
218 * and segment tables so we can start running with translation
221 * It is this function which will call the probe() callback of
222 * the various platform types and copy the matching one to the
223 * global ppc_md structure. Your platform can eventually do
224 * some very early initializations from the probe() routine, but
225 * this is not recommended, be very careful as, for example, the
226 * device-tree is not accessible via normal means at this point.
229 void __init early_setup(unsigned long dt_ptr)
231 static __initdata struct paca_struct boot_paca;
233 /* -------- printk is _NOT_ safe to use here ! ------- */
235 /* Identify CPU type */
236 identify_cpu(0, mfspr(SPRN_PVR));
238 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */
239 initialise_paca(&boot_paca, 0);
240 setup_paca(&boot_paca);
243 /* Initialize lockdep early or else spinlocks will blow */
246 /* -------- printk is now safe to use ------- */
248 /* Enable early debugging if any specified (see udbg.h) */
251 DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr);
254 * Do early initialization using the flattened device
255 * tree, such as retrieving the physical memory map or
256 * calculating/retrieving the hash table size.
258 early_init_devtree(__va(dt_ptr));
260 epapr_paravirt_early_init();
262 /* Now we know the logical id of our boot cpu, setup the paca. */
263 setup_paca(&paca[boot_cpuid]);
266 /* Probe the machine type */
269 setup_kdump_trampoline();
271 DBG("Found, Initializing memory management...\n");
273 /* Initialize the hash table or TLB handling */
277 * At this point, we can let interrupts switch to virtual mode
278 * (the MMU has been setup), so adjust the MSR in the PACA to
279 * have IR and DR set and enable AIL if it exists
281 cpu_ready_for_interrupts();
283 /* Reserve large chunks of memory for use by CMA for KVM */
287 * Reserve any gigantic pages requested on the command line.
288 * memblock needs to have been initialized by the time this is
289 * called since this will reserve memory.
291 reserve_hugetlb_gpages();
293 DBG(" <- early_setup()\n");
295 #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
297 * This needs to be done *last* (after the above DBG() even)
299 * Right after we return from this function, we turn on the MMU
300 * which means the real-mode access trick that btext does will
301 * no longer work, it needs to switch to using a real MMU
302 * mapping. This call will ensure that it does
305 #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
309 void early_setup_secondary(void)
311 /* Mark interrupts enabled in PACA */
312 get_paca()->soft_enabled = 0;
314 /* Initialize the hash table or TLB handling */
315 early_init_mmu_secondary();
318 * At this point, we can let interrupts switch to virtual mode
319 * (the MMU has been setup), so adjust the MSR in the PACA to
320 * have IR and DR set.
322 cpu_ready_for_interrupts();
325 #endif /* CONFIG_SMP */
327 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
328 void smp_release_cpus(void)
333 DBG(" -> smp_release_cpus()\n");
335 /* All secondary cpus are spinning on a common spinloop, release them
336 * all now so they can start to spin on their individual paca
337 * spinloops. For non SMP kernels, the secondary cpus never get out
338 * of the common spinloop.
341 ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop
343 *ptr = __pa(generic_secondary_smp_init);
345 /* And wait a bit for them to catch up */
346 for (i = 0; i < 100000; i++) {
349 if (spinning_secondaries == 0)
353 DBG("spinning_secondaries = %d\n", spinning_secondaries);
355 DBG(" <- smp_release_cpus()\n");
357 #endif /* CONFIG_SMP || CONFIG_KEXEC */
360 * Initialize some remaining members of the ppc64_caches and systemcfg
362 * (at least until we get rid of them completely). This is mostly some
363 * cache informations about the CPU that will be used by cache flush
364 * routines and/or provided to userland
366 static void __init initialize_cache_info(void)
368 struct device_node *np;
369 unsigned long num_cpus = 0;
371 DBG(" -> initialize_cache_info()\n");
373 for_each_node_by_type(np, "cpu") {
377 * We're assuming *all* of the CPUs have the same
378 * d-cache and i-cache sizes... -Peter
381 const __be32 *sizep, *lsizep;
385 lsize = cur_cpu_spec->dcache_bsize;
386 sizep = of_get_property(np, "d-cache-size", NULL);
388 size = be32_to_cpu(*sizep);
389 lsizep = of_get_property(np, "d-cache-block-size",
391 /* fallback if block size missing */
393 lsizep = of_get_property(np,
397 lsize = be32_to_cpu(*lsizep);
398 if (sizep == NULL || lsizep == NULL)
399 DBG("Argh, can't find dcache properties ! "
400 "sizep: %p, lsizep: %p\n", sizep, lsizep);
402 ppc64_caches.dsize = size;
403 ppc64_caches.dline_size = lsize;
404 ppc64_caches.log_dline_size = __ilog2(lsize);
405 ppc64_caches.dlines_per_page = PAGE_SIZE / lsize;
408 lsize = cur_cpu_spec->icache_bsize;
409 sizep = of_get_property(np, "i-cache-size", NULL);
411 size = be32_to_cpu(*sizep);
412 lsizep = of_get_property(np, "i-cache-block-size",
415 lsizep = of_get_property(np,
419 lsize = be32_to_cpu(*lsizep);
420 if (sizep == NULL || lsizep == NULL)
421 DBG("Argh, can't find icache properties ! "
422 "sizep: %p, lsizep: %p\n", sizep, lsizep);
424 ppc64_caches.isize = size;
425 ppc64_caches.iline_size = lsize;
426 ppc64_caches.log_iline_size = __ilog2(lsize);
427 ppc64_caches.ilines_per_page = PAGE_SIZE / lsize;
431 DBG(" <- initialize_cache_info()\n");
436 * Do some initial setup of the system. The parameters are those which
437 * were passed in from the bootloader.
439 void __init setup_system(void)
441 DBG(" -> setup_system()\n");
443 /* Apply the CPUs-specific and firmware specific fixups to kernel
444 * text (nop out sections not relevant to this CPU or this firmware)
446 do_feature_fixups(cur_cpu_spec->cpu_features,
447 &__start___ftr_fixup, &__stop___ftr_fixup);
448 do_feature_fixups(cur_cpu_spec->mmu_features,
449 &__start___mmu_ftr_fixup, &__stop___mmu_ftr_fixup);
450 do_feature_fixups(powerpc_firmware_features,
451 &__start___fw_ftr_fixup, &__stop___fw_ftr_fixup);
452 do_lwsync_fixups(cur_cpu_spec->cpu_features,
453 &__start___lwsync_fixup, &__stop___lwsync_fixup);
457 * Unflatten the device-tree passed by prom_init or kexec
459 unflatten_device_tree();
462 * Fill the ppc64_caches & systemcfg structures with informations
463 * retrieved from the device-tree.
465 initialize_cache_info();
467 #ifdef CONFIG_PPC_RTAS
469 * Initialize RTAS if available
472 #endif /* CONFIG_PPC_RTAS */
475 * Check if we have an initrd provided via the device-tree
480 * Do some platform specific early initializations, that includes
481 * setting up the hash table pointers. It also sets up some interrupt-mapping
482 * related options that will be used by finish_device_tree()
484 if (ppc_md.init_early)
488 * We can discover serial ports now since the above did setup the
489 * hash table management for us, thus ioremap works. We do that early
490 * so that further code can be debugged
492 find_legacy_serial_ports();
495 * Register early console
497 register_early_udbg_console();
504 smp_setup_cpu_maps();
506 setup_tlb_core_data();
509 /* Release secondary cpus out of their spinloops at 0x60 now that
510 * we can map physical -> logical CPU ids
515 printk("Starting Linux PPC64 %s\n", init_utsname()->version);
517 printk("-----------------------------------------------------\n");
518 printk("ppc64_pft_size = 0x%llx\n", ppc64_pft_size);
519 printk("physicalMemorySize = 0x%llx\n", memblock_phys_mem_size());
520 if (ppc64_caches.dline_size != 0x80)
521 printk("ppc64_caches.dcache_line_size = 0x%x\n",
522 ppc64_caches.dline_size);
523 if (ppc64_caches.iline_size != 0x80)
524 printk("ppc64_caches.icache_line_size = 0x%x\n",
525 ppc64_caches.iline_size);
526 #ifdef CONFIG_PPC_STD_MMU_64
528 printk("htab_address = 0x%p\n", htab_address);
529 printk("htab_hash_mask = 0x%lx\n", htab_hash_mask);
530 #endif /* CONFIG_PPC_STD_MMU_64 */
531 if (PHYSICAL_START > 0)
532 printk("physical_start = 0x%llx\n",
533 (unsigned long long)PHYSICAL_START);
534 printk("-----------------------------------------------------\n");
536 DBG(" <- setup_system()\n");
539 /* This returns the limit below which memory accesses to the linear
540 * mapping are guarnateed not to cause a TLB or SLB miss. This is
541 * used to allocate interrupt or emergency stacks for which our
542 * exception entry path doesn't deal with being interrupted.
544 static u64 safe_stack_limit(void)
546 #ifdef CONFIG_PPC_BOOK3E
547 /* Freescale BookE bolts the entire linear mapping */
548 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E))
549 return linear_map_top;
550 /* Other BookE, we assume the first GB is bolted */
553 /* BookS, the first segment is bolted */
554 if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
555 return 1UL << SID_SHIFT_1T;
556 return 1UL << SID_SHIFT;
560 static void __init irqstack_early_init(void)
562 u64 limit = safe_stack_limit();
566 * Interrupt stacks must be in the first segment since we
567 * cannot afford to take SLB misses on them.
569 for_each_possible_cpu(i) {
570 softirq_ctx[i] = (struct thread_info *)
571 __va(memblock_alloc_base(THREAD_SIZE,
572 THREAD_SIZE, limit));
573 hardirq_ctx[i] = (struct thread_info *)
574 __va(memblock_alloc_base(THREAD_SIZE,
575 THREAD_SIZE, limit));
579 #ifdef CONFIG_PPC_BOOK3E
580 static void __init exc_lvl_early_init(void)
585 for_each_possible_cpu(i) {
586 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
587 critirq_ctx[i] = (struct thread_info *)__va(sp);
588 paca[i].crit_kstack = __va(sp + THREAD_SIZE);
590 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
591 dbgirq_ctx[i] = (struct thread_info *)__va(sp);
592 paca[i].dbg_kstack = __va(sp + THREAD_SIZE);
594 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
595 mcheckirq_ctx[i] = (struct thread_info *)__va(sp);
596 paca[i].mc_kstack = __va(sp + THREAD_SIZE);
599 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
600 patch_exception(0x040, exc_debug_debug_book3e);
603 #define exc_lvl_early_init()
607 * Stack space used when we detect a bad kernel stack pointer, and
608 * early in SMP boots before relocation is enabled. Exclusive emergency
609 * stack for machine checks.
611 static void __init emergency_stack_init(void)
617 * Emergency stacks must be under 256MB, we cannot afford to take
618 * SLB misses on them. The ABI also requires them to be 128-byte
621 * Since we use these as temporary stacks during secondary CPU
622 * bringup, we need to get at them in real mode. This means they
623 * must also be within the RMO region.
625 limit = min(safe_stack_limit(), ppc64_rma_size);
627 for_each_possible_cpu(i) {
629 sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit);
631 paca[i].emergency_sp = __va(sp);
633 #ifdef CONFIG_PPC_BOOK3S_64
634 /* emergency stack for machine check exception handling. */
635 sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit);
637 paca[i].mc_emergency_sp = __va(sp);
643 * Called into from start_kernel this initializes bootmem, which is used
644 * to manage page allocation until mem_init is called.
646 void __init setup_arch(char **cmdline_p)
648 ppc64_boot_msg(0x12, "Setup Arch");
650 *cmdline_p = cmd_line;
653 * Set cache line size based on type of cpu as a default.
654 * Systems with OF can look in the properties on the cpu node(s)
655 * for a possibly more accurate value.
657 dcache_bsize = ppc64_caches.dline_size;
658 icache_bsize = ppc64_caches.iline_size;
663 init_mm.start_code = (unsigned long)_stext;
664 init_mm.end_code = (unsigned long) _etext;
665 init_mm.end_data = (unsigned long) _edata;
666 init_mm.brk = klimit;
667 #ifdef CONFIG_PPC_64K_PAGES
668 init_mm.context.pte_frag = NULL;
670 irqstack_early_init();
671 exc_lvl_early_init();
672 emergency_stack_init();
674 #ifdef CONFIG_PPC_STD_MMU_64
677 /* set up the bootmem stuff with available memory */
681 #ifdef CONFIG_DUMMY_CONSOLE
682 conswitchp = &dummy_con;
685 if (ppc_md.setup_arch)
690 /* Initialize the MMU context management stuff */
693 /* Interrupt code needs to be 64K-aligned */
694 if ((unsigned long)_stext & 0xffff)
695 panic("Kernelbase not 64K-aligned (0x%lx)!\n",
696 (unsigned long)_stext);
698 ppc64_boot_msg(0x15, "Setup Done");
702 /* ToDo: do something useful if ppc_md is not yet setup. */
703 #define PPC64_LINUX_FUNCTION 0x0f000000
704 #define PPC64_IPL_MESSAGE 0xc0000000
705 #define PPC64_TERM_MESSAGE 0xb0000000
707 static void ppc64_do_msg(unsigned int src, const char *msg)
709 if (ppc_md.progress) {
712 sprintf(buf, "%08X\n", src);
713 ppc_md.progress(buf, 0);
714 snprintf(buf, 128, "%s", msg);
715 ppc_md.progress(buf, 0);
719 /* Print a boot progress message. */
720 void ppc64_boot_msg(unsigned int src, const char *msg)
722 ppc64_do_msg(PPC64_LINUX_FUNCTION|PPC64_IPL_MESSAGE|src, msg);
723 printk("[boot]%04x %s\n", src, msg);
727 #define PCPU_DYN_SIZE ()
729 static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align)
731 return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align,
732 __pa(MAX_DMA_ADDRESS));
735 static void __init pcpu_fc_free(void *ptr, size_t size)
737 free_bootmem(__pa(ptr), size);
740 static int pcpu_cpu_distance(unsigned int from, unsigned int to)
742 if (cpu_to_node(from) == cpu_to_node(to))
743 return LOCAL_DISTANCE;
745 return REMOTE_DISTANCE;
748 unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
749 EXPORT_SYMBOL(__per_cpu_offset);
751 void __init setup_per_cpu_areas(void)
753 const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE;
760 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need
761 * to group units. For larger mappings, use 1M atom which
762 * should be large enough to contain a number of units.
764 if (mmu_linear_psize == MMU_PAGE_4K)
765 atom_size = PAGE_SIZE;
769 rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance,
770 pcpu_fc_alloc, pcpu_fc_free);
772 panic("cannot initialize percpu area (err=%d)", rc);
774 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
775 for_each_possible_cpu(cpu) {
776 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
777 paca[cpu].data_offset = __per_cpu_offset[cpu];
783 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
784 struct ppc_pci_io ppc_pci_io;
785 EXPORT_SYMBOL(ppc_pci_io);