3 * Common boot and setup code.
5 * Copyright (C) 2001 PPC64 Team, IBM Corp
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
15 #include <linux/export.h>
16 #include <linux/string.h>
17 #include <linux/sched.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/reboot.h>
21 #include <linux/delay.h>
22 #include <linux/initrd.h>
23 #include <linux/seq_file.h>
24 #include <linux/ioport.h>
25 #include <linux/console.h>
26 #include <linux/utsname.h>
27 #include <linux/tty.h>
28 #include <linux/root_dev.h>
29 #include <linux/notifier.h>
30 #include <linux/cpu.h>
31 #include <linux/unistd.h>
32 #include <linux/serial.h>
33 #include <linux/serial_8250.h>
34 #include <linux/bootmem.h>
35 #include <linux/pci.h>
36 #include <linux/lockdep.h>
37 #include <linux/memblock.h>
38 #include <linux/memory.h>
39 #include <linux/nmi.h>
42 #include <asm/kdump.h>
44 #include <asm/processor.h>
45 #include <asm/pgtable.h>
48 #include <asm/machdep.h>
51 #include <asm/cputable.h>
52 #include <asm/sections.h>
53 #include <asm/btext.h>
54 #include <asm/nvram.h>
55 #include <asm/setup.h>
57 #include <asm/iommu.h>
58 #include <asm/serial.h>
59 #include <asm/cache.h>
62 #include <asm/firmware.h>
65 #include <asm/kexec.h>
66 #include <asm/code-patching.h>
67 #include <asm/livepatch.h>
69 #include <asm/cputhreads.h>
72 #define DBG(fmt...) udbg_printf(fmt)
77 int spinning_secondaries;
80 struct ppc64_caches ppc64_caches = {
90 EXPORT_SYMBOL_GPL(ppc64_caches);
92 #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP)
93 void __init setup_tlb_core_data(void)
97 BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0);
99 for_each_possible_cpu(cpu) {
100 int first = cpu_first_thread_sibling(cpu);
103 * If we boot via kdump on a non-primary thread,
104 * make sure we point at the thread that actually
107 if (cpu_first_thread_sibling(boot_cpuid) == first)
110 paca[cpu].tcd_ptr = &paca[first].tcd;
113 * If we have threads, we need either tlbsrx.
114 * or e6500 tablewalk mode, or else TLB handlers
115 * will be racy and could produce duplicate entries.
116 * Should we panic instead?
118 WARN_ONCE(smt_enabled_at_boot >= 2 &&
119 !mmu_has_feature(MMU_FTR_USE_TLBRSRV) &&
120 book3e_htw_mode != PPC_HTW_E6500,
121 "%s: unsupported MMU configuration\n", __func__);
128 static char *smt_enabled_cmdline;
130 /* Look for ibm,smt-enabled OF option */
131 void __init check_smt_enabled(void)
133 struct device_node *dn;
134 const char *smt_option;
136 /* Default to enabling all threads */
137 smt_enabled_at_boot = threads_per_core;
139 /* Allow the command line to overrule the OF option */
140 if (smt_enabled_cmdline) {
141 if (!strcmp(smt_enabled_cmdline, "on"))
142 smt_enabled_at_boot = threads_per_core;
143 else if (!strcmp(smt_enabled_cmdline, "off"))
144 smt_enabled_at_boot = 0;
149 rc = kstrtoint(smt_enabled_cmdline, 10, &smt);
151 smt_enabled_at_boot =
152 min(threads_per_core, smt);
155 dn = of_find_node_by_path("/options");
157 smt_option = of_get_property(dn, "ibm,smt-enabled",
161 if (!strcmp(smt_option, "on"))
162 smt_enabled_at_boot = threads_per_core;
163 else if (!strcmp(smt_option, "off"))
164 smt_enabled_at_boot = 0;
172 /* Look for smt-enabled= cmdline option */
173 static int __init early_smt_enabled(char *p)
175 smt_enabled_cmdline = p;
178 early_param("smt-enabled", early_smt_enabled);
180 #endif /* CONFIG_SMP */
182 /** Fix up paca fields required for the boot cpu */
183 static void __init fixup_boot_paca(void)
185 /* The boot cpu is started */
186 get_paca()->cpu_start = 1;
187 /* Allow percpu accesses to work until we setup percpu data */
188 get_paca()->data_offset = 0;
191 static void __init configure_exceptions(void)
194 * Setup the trampolines from the lowmem exception vectors
195 * to the kdump kernel when not using a relocatable kernel.
197 setup_kdump_trampoline();
199 /* Under a PAPR hypervisor, we need hypercalls */
200 if (firmware_has_feature(FW_FEATURE_SET_MODE)) {
201 /* Enable AIL if possible */
202 pseries_enable_reloc_on_exc();
205 * Tell the hypervisor that we want our exceptions to
206 * be taken in little endian mode.
208 * We don't call this for big endian as our calling convention
209 * makes us always enter in BE, and the call may fail under
210 * some circumstances with kdump.
212 #ifdef __LITTLE_ENDIAN__
213 pseries_little_endian_exceptions();
216 /* Set endian mode using OPAL */
217 if (firmware_has_feature(FW_FEATURE_OPAL))
218 opal_configure_cores();
220 /* AIL on native is done in cpu_ready_for_interrupts() */
224 static void cpu_ready_for_interrupts(void)
227 * Enable AIL if supported, and we are in hypervisor mode. This
228 * is called once for every processor.
230 * If we are not in hypervisor mode the job is done once for
231 * the whole partition in configure_exceptions().
233 if (cpu_has_feature(CPU_FTR_HVMODE) &&
234 cpu_has_feature(CPU_FTR_ARCH_207S)) {
235 unsigned long lpcr = mfspr(SPRN_LPCR);
236 mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);
240 * Fixup HFSCR:TM based on CPU features. The bit is set by our
241 * early asm init because at that point we haven't updated our
242 * CPU features from firmware and device-tree. Here we have,
245 if (cpu_has_feature(CPU_FTR_HVMODE) && !cpu_has_feature(CPU_FTR_TM_COMP))
246 mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) & ~HFSCR_TM);
248 /* Set IR and DR in PACA MSR */
249 get_paca()->kernel_msr = MSR_KERNEL;
253 * Early initialization entry point. This is called by head.S
254 * with MMU translation disabled. We rely on the "feature" of
255 * the CPU that ignores the top 2 bits of the address in real
256 * mode so we can access kernel globals normally provided we
257 * only toy with things in the RMO region. From here, we do
258 * some early parsing of the device-tree to setup out MEMBLOCK
259 * data structures, and allocate & initialize the hash table
260 * and segment tables so we can start running with translation
263 * It is this function which will call the probe() callback of
264 * the various platform types and copy the matching one to the
265 * global ppc_md structure. Your platform can eventually do
266 * some very early initializations from the probe() routine, but
267 * this is not recommended, be very careful as, for example, the
268 * device-tree is not accessible via normal means at this point.
271 void __init early_setup(unsigned long dt_ptr)
273 static __initdata struct paca_struct boot_paca;
275 /* -------- printk is _NOT_ safe to use here ! ------- */
277 /* Identify CPU type */
278 identify_cpu(0, mfspr(SPRN_PVR));
280 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */
281 initialise_paca(&boot_paca, 0);
282 setup_paca(&boot_paca);
285 /* -------- printk is now safe to use ------- */
287 /* Enable early debugging if any specified (see udbg.h) */
290 DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr);
293 * Do early initialization using the flattened device
294 * tree, such as retrieving the physical memory map or
295 * calculating/retrieving the hash table size.
297 early_init_devtree(__va(dt_ptr));
299 /* Now we know the logical id of our boot cpu, setup the paca. */
300 setup_paca(&paca[boot_cpuid]);
304 * Configure exception handlers. This include setting up trampolines
305 * if needed, setting exception endian mode, etc...
307 configure_exceptions();
309 /* Apply all the dynamic patching */
310 apply_feature_fixups();
311 setup_feature_keys();
313 /* Initialize the hash table or TLB handling */
317 * At this point, we can let interrupts switch to virtual mode
318 * (the MMU has been setup), so adjust the MSR in the PACA to
319 * have IR and DR set and enable AIL if it exists
321 cpu_ready_for_interrupts();
323 DBG(" <- early_setup()\n");
325 #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
327 * This needs to be done *last* (after the above DBG() even)
329 * Right after we return from this function, we turn on the MMU
330 * which means the real-mode access trick that btext does will
331 * no longer work, it needs to switch to using a real MMU
332 * mapping. This call will ensure that it does
335 #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
339 void early_setup_secondary(void)
341 /* Mark interrupts disabled in PACA */
342 get_paca()->soft_enabled = 0;
344 /* Initialize the hash table or TLB handling */
345 early_init_mmu_secondary();
348 * At this point, we can let interrupts switch to virtual mode
349 * (the MMU has been setup), so adjust the MSR in the PACA to
350 * have IR and DR set.
352 cpu_ready_for_interrupts();
355 #endif /* CONFIG_SMP */
357 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)
358 static bool use_spinloop(void)
360 if (!IS_ENABLED(CONFIG_PPC_BOOK3E))
364 * When book3e boots from kexec, the ePAPR spin table does
367 return of_property_read_bool(of_chosen, "linux,booted-from-kexec");
370 void smp_release_cpus(void)
378 DBG(" -> smp_release_cpus()\n");
380 /* All secondary cpus are spinning on a common spinloop, release them
381 * all now so they can start to spin on their individual paca
382 * spinloops. For non SMP kernels, the secondary cpus never get out
383 * of the common spinloop.
386 ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop
388 *ptr = ppc_function_entry(generic_secondary_smp_init);
390 /* And wait a bit for them to catch up */
391 for (i = 0; i < 100000; i++) {
394 if (spinning_secondaries == 0)
398 DBG("spinning_secondaries = %d\n", spinning_secondaries);
400 DBG(" <- smp_release_cpus()\n");
402 #endif /* CONFIG_SMP || CONFIG_KEXEC_CORE */
405 * Initialize some remaining members of the ppc64_caches and systemcfg
407 * (at least until we get rid of them completely). This is mostly some
408 * cache informations about the CPU that will be used by cache flush
409 * routines and/or provided to userland
412 static void init_cache_info(struct ppc_cache_info *info, u32 size, u32 lsize,
417 info->line_size = lsize;
418 info->block_size = bsize;
419 info->log_block_size = __ilog2(bsize);
421 info->blocks_per_page = PAGE_SIZE / bsize;
423 info->blocks_per_page = 0;
426 info->assoc = 0xffff;
428 info->assoc = size / (sets * lsize);
431 static bool __init parse_cache_info(struct device_node *np,
433 struct ppc_cache_info *info)
435 static const char *ipropnames[] __initdata = {
438 "i-cache-block-size",
441 static const char *dpropnames[] __initdata = {
444 "d-cache-block-size",
447 const char **propnames = icache ? ipropnames : dpropnames;
448 const __be32 *sizep, *lsizep, *bsizep, *setsp;
449 u32 size, lsize, bsize, sets;
454 lsize = bsize = cur_cpu_spec->dcache_bsize;
455 sizep = of_get_property(np, propnames[0], NULL);
457 size = be32_to_cpu(*sizep);
458 setsp = of_get_property(np, propnames[1], NULL);
460 sets = be32_to_cpu(*setsp);
461 bsizep = of_get_property(np, propnames[2], NULL);
462 lsizep = of_get_property(np, propnames[3], NULL);
466 lsize = be32_to_cpu(*lsizep);
468 bsize = be32_to_cpu(*bsizep);
469 if (sizep == NULL || bsizep == NULL || lsizep == NULL)
473 * OF is weird .. it represents fully associative caches
474 * as "1 way" which doesn't make much sense and doesn't
475 * leave room for direct mapped. We'll assume that 0
476 * in OF means direct mapped for that reason.
483 init_cache_info(info, size, lsize, bsize, sets);
488 void __init initialize_cache_info(void)
490 struct device_node *cpu = NULL, *l2, *l3 = NULL;
493 DBG(" -> initialize_cache_info()\n");
496 * All shipping POWER8 machines have a firmware bug that
497 * puts incorrect information in the device-tree. This will
498 * be (hopefully) fixed for future chips but for now hard
499 * code the values if we are running on one of these
501 pvr = PVR_VER(mfspr(SPRN_PVR));
502 if (pvr == PVR_POWER8 || pvr == PVR_POWER8E ||
503 pvr == PVR_POWER8NVL) {
504 /* size lsize blk sets */
505 init_cache_info(&ppc64_caches.l1i, 0x8000, 128, 128, 32);
506 init_cache_info(&ppc64_caches.l1d, 0x10000, 128, 128, 64);
507 init_cache_info(&ppc64_caches.l2, 0x80000, 128, 0, 512);
508 init_cache_info(&ppc64_caches.l3, 0x800000, 128, 0, 8192);
510 cpu = of_find_node_by_type(NULL, "cpu");
513 * We're assuming *all* of the CPUs have the same
514 * d-cache and i-cache sizes... -Peter
517 if (!parse_cache_info(cpu, false, &ppc64_caches.l1d))
518 DBG("Argh, can't find dcache properties !\n");
520 if (!parse_cache_info(cpu, true, &ppc64_caches.l1i))
521 DBG("Argh, can't find icache properties !\n");
524 * Try to find the L2 and L3 if any. Assume they are
525 * unified and use the D-side properties.
527 l2 = of_find_next_cache_node(cpu);
530 parse_cache_info(l2, false, &ppc64_caches.l2);
531 l3 = of_find_next_cache_node(l2);
535 parse_cache_info(l3, false, &ppc64_caches.l3);
540 /* For use by binfmt_elf */
541 dcache_bsize = ppc64_caches.l1d.block_size;
542 icache_bsize = ppc64_caches.l1i.block_size;
544 DBG(" <- initialize_cache_info()\n");
547 /* This returns the limit below which memory accesses to the linear
548 * mapping are guarnateed not to cause a TLB or SLB miss. This is
549 * used to allocate interrupt or emergency stacks for which our
550 * exception entry path doesn't deal with being interrupted.
552 static __init u64 safe_stack_limit(void)
554 #ifdef CONFIG_PPC_BOOK3E
555 /* Freescale BookE bolts the entire linear mapping */
556 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E))
557 return linear_map_top;
558 /* Other BookE, we assume the first GB is bolted */
561 /* BookS, the first segment is bolted */
562 if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
563 return 1UL << SID_SHIFT_1T;
564 return 1UL << SID_SHIFT;
568 void __init irqstack_early_init(void)
570 u64 limit = safe_stack_limit();
574 * Interrupt stacks must be in the first segment since we
575 * cannot afford to take SLB misses on them.
577 for_each_possible_cpu(i) {
578 softirq_ctx[i] = (struct thread_info *)
579 __va(memblock_alloc_base(THREAD_SIZE,
580 THREAD_SIZE, limit));
581 hardirq_ctx[i] = (struct thread_info *)
582 __va(memblock_alloc_base(THREAD_SIZE,
583 THREAD_SIZE, limit));
587 #ifdef CONFIG_PPC_BOOK3E
588 void __init exc_lvl_early_init(void)
593 for_each_possible_cpu(i) {
594 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
595 critirq_ctx[i] = (struct thread_info *)__va(sp);
596 paca[i].crit_kstack = __va(sp + THREAD_SIZE);
598 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
599 dbgirq_ctx[i] = (struct thread_info *)__va(sp);
600 paca[i].dbg_kstack = __va(sp + THREAD_SIZE);
602 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
603 mcheckirq_ctx[i] = (struct thread_info *)__va(sp);
604 paca[i].mc_kstack = __va(sp + THREAD_SIZE);
607 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
608 patch_exception(0x040, exc_debug_debug_book3e);
613 * Stack space used when we detect a bad kernel stack pointer, and
614 * early in SMP boots before relocation is enabled. Exclusive emergency
615 * stack for machine checks.
617 void __init emergency_stack_init(void)
623 * Emergency stacks must be under 256MB, we cannot afford to take
624 * SLB misses on them. The ABI also requires them to be 128-byte
627 * Since we use these as temporary stacks during secondary CPU
628 * bringup, we need to get at them in real mode. This means they
629 * must also be within the RMO region.
631 limit = min(safe_stack_limit(), ppc64_rma_size);
633 for_each_possible_cpu(i) {
634 struct thread_info *ti;
635 ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit));
636 klp_init_thread_info(ti);
637 paca[i].emergency_sp = (void *)ti + THREAD_SIZE;
639 #ifdef CONFIG_PPC_BOOK3S_64
640 /* emergency stack for NMI exception handling. */
641 ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit));
642 klp_init_thread_info(ti);
643 paca[i].nmi_emergency_sp = (void *)ti + THREAD_SIZE;
645 /* emergency stack for machine check exception handling. */
646 ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit));
647 klp_init_thread_info(ti);
648 paca[i].mc_emergency_sp = (void *)ti + THREAD_SIZE;
654 #define PCPU_DYN_SIZE ()
656 static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align)
658 return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align,
659 __pa(MAX_DMA_ADDRESS));
662 static void __init pcpu_fc_free(void *ptr, size_t size)
664 free_bootmem(__pa(ptr), size);
667 static int pcpu_cpu_distance(unsigned int from, unsigned int to)
669 if (cpu_to_node(from) == cpu_to_node(to))
670 return LOCAL_DISTANCE;
672 return REMOTE_DISTANCE;
675 unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
676 EXPORT_SYMBOL(__per_cpu_offset);
678 void __init setup_per_cpu_areas(void)
680 const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE;
687 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need
688 * to group units. For larger mappings, use 1M atom which
689 * should be large enough to contain a number of units.
691 if (mmu_linear_psize == MMU_PAGE_4K)
692 atom_size = PAGE_SIZE;
696 rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance,
697 pcpu_fc_alloc, pcpu_fc_free);
699 panic("cannot initialize percpu area (err=%d)", rc);
701 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
702 for_each_possible_cpu(cpu) {
703 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
704 paca[cpu].data_offset = __per_cpu_offset[cpu];
709 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
710 unsigned long memory_block_size_bytes(void)
712 if (ppc_md.memory_block_size)
713 return ppc_md.memory_block_size();
715 return MIN_MEMORY_BLOCK_SIZE;
719 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
720 struct ppc_pci_io ppc_pci_io;
721 EXPORT_SYMBOL(ppc_pci_io);
724 #ifdef CONFIG_HARDLOCKUP_DETECTOR
725 u64 hw_nmi_get_sample_period(int watchdog_thresh)
727 return ppc_proc_freq * watchdog_thresh;
731 * The hardlockup detector breaks PMU event based branches and is likely
732 * to get false positives in KVM guests, so disable it by default.
734 static int __init disable_hardlockup_detector(void)
736 hardlockup_detector_disable();
740 early_initcall(disable_hardlockup_detector);