3 * Common boot and setup code.
5 * Copyright (C) 2001 PPC64 Team, IBM Corp
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
15 #include <linux/export.h>
16 #include <linux/string.h>
17 #include <linux/sched.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/reboot.h>
21 #include <linux/delay.h>
22 #include <linux/initrd.h>
23 #include <linux/seq_file.h>
24 #include <linux/ioport.h>
25 #include <linux/console.h>
26 #include <linux/utsname.h>
27 #include <linux/tty.h>
28 #include <linux/root_dev.h>
29 #include <linux/notifier.h>
30 #include <linux/cpu.h>
31 #include <linux/unistd.h>
32 #include <linux/serial.h>
33 #include <linux/serial_8250.h>
34 #include <linux/bootmem.h>
35 #include <linux/pci.h>
36 #include <linux/lockdep.h>
37 #include <linux/memblock.h>
38 #include <linux/memory.h>
39 #include <linux/nmi.h>
42 #include <asm/kdump.h>
44 #include <asm/processor.h>
45 #include <asm/pgtable.h>
48 #include <asm/machdep.h>
51 #include <asm/cputable.h>
52 #include <asm/dt_cpu_ftrs.h>
53 #include <asm/sections.h>
54 #include <asm/btext.h>
55 #include <asm/nvram.h>
56 #include <asm/setup.h>
58 #include <asm/iommu.h>
59 #include <asm/serial.h>
60 #include <asm/cache.h>
63 #include <asm/firmware.h>
66 #include <asm/kexec.h>
67 #include <asm/code-patching.h>
68 #include <asm/livepatch.h>
70 #include <asm/cputhreads.h>
73 #define DBG(fmt...) udbg_printf(fmt)
78 int spinning_secondaries;
81 struct ppc64_caches ppc64_caches = {
91 EXPORT_SYMBOL_GPL(ppc64_caches);
93 #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP)
94 void __init setup_tlb_core_data(void)
98 BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0);
100 for_each_possible_cpu(cpu) {
101 int first = cpu_first_thread_sibling(cpu);
104 * If we boot via kdump on a non-primary thread,
105 * make sure we point at the thread that actually
108 if (cpu_first_thread_sibling(boot_cpuid) == first)
111 paca[cpu].tcd_ptr = &paca[first].tcd;
114 * If we have threads, we need either tlbsrx.
115 * or e6500 tablewalk mode, or else TLB handlers
116 * will be racy and could produce duplicate entries.
117 * Should we panic instead?
119 WARN_ONCE(smt_enabled_at_boot >= 2 &&
120 !mmu_has_feature(MMU_FTR_USE_TLBRSRV) &&
121 book3e_htw_mode != PPC_HTW_E6500,
122 "%s: unsupported MMU configuration\n", __func__);
129 static char *smt_enabled_cmdline;
131 /* Look for ibm,smt-enabled OF option */
132 void __init check_smt_enabled(void)
134 struct device_node *dn;
135 const char *smt_option;
137 /* Default to enabling all threads */
138 smt_enabled_at_boot = threads_per_core;
140 /* Allow the command line to overrule the OF option */
141 if (smt_enabled_cmdline) {
142 if (!strcmp(smt_enabled_cmdline, "on"))
143 smt_enabled_at_boot = threads_per_core;
144 else if (!strcmp(smt_enabled_cmdline, "off"))
145 smt_enabled_at_boot = 0;
150 rc = kstrtoint(smt_enabled_cmdline, 10, &smt);
152 smt_enabled_at_boot =
153 min(threads_per_core, smt);
156 dn = of_find_node_by_path("/options");
158 smt_option = of_get_property(dn, "ibm,smt-enabled",
162 if (!strcmp(smt_option, "on"))
163 smt_enabled_at_boot = threads_per_core;
164 else if (!strcmp(smt_option, "off"))
165 smt_enabled_at_boot = 0;
173 /* Look for smt-enabled= cmdline option */
174 static int __init early_smt_enabled(char *p)
176 smt_enabled_cmdline = p;
179 early_param("smt-enabled", early_smt_enabled);
181 #endif /* CONFIG_SMP */
183 /** Fix up paca fields required for the boot cpu */
184 static void __init fixup_boot_paca(void)
186 /* The boot cpu is started */
187 get_paca()->cpu_start = 1;
188 /* Allow percpu accesses to work until we setup percpu data */
189 get_paca()->data_offset = 0;
192 static void __init configure_exceptions(void)
195 * Setup the trampolines from the lowmem exception vectors
196 * to the kdump kernel when not using a relocatable kernel.
198 setup_kdump_trampoline();
200 /* Under a PAPR hypervisor, we need hypercalls */
201 if (firmware_has_feature(FW_FEATURE_SET_MODE)) {
202 /* Enable AIL if possible */
203 pseries_enable_reloc_on_exc();
206 * Tell the hypervisor that we want our exceptions to
207 * be taken in little endian mode.
209 * We don't call this for big endian as our calling convention
210 * makes us always enter in BE, and the call may fail under
211 * some circumstances with kdump.
213 #ifdef __LITTLE_ENDIAN__
214 pseries_little_endian_exceptions();
217 /* Set endian mode using OPAL */
218 if (firmware_has_feature(FW_FEATURE_OPAL))
219 opal_configure_cores();
221 /* AIL on native is done in cpu_ready_for_interrupts() */
225 static void cpu_ready_for_interrupts(void)
228 * Enable AIL if supported, and we are in hypervisor mode. This
229 * is called once for every processor.
231 * If we are not in hypervisor mode the job is done once for
232 * the whole partition in configure_exceptions().
234 if (cpu_has_feature(CPU_FTR_HVMODE) &&
235 cpu_has_feature(CPU_FTR_ARCH_207S)) {
236 unsigned long lpcr = mfspr(SPRN_LPCR);
237 mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);
241 * Fixup HFSCR:TM based on CPU features. The bit is set by our
242 * early asm init because at that point we haven't updated our
243 * CPU features from firmware and device-tree. Here we have,
246 if (cpu_has_feature(CPU_FTR_HVMODE) && !cpu_has_feature(CPU_FTR_TM_COMP))
247 mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) & ~HFSCR_TM);
249 /* Set IR and DR in PACA MSR */
250 get_paca()->kernel_msr = MSR_KERNEL;
254 * Early initialization entry point. This is called by head.S
255 * with MMU translation disabled. We rely on the "feature" of
256 * the CPU that ignores the top 2 bits of the address in real
257 * mode so we can access kernel globals normally provided we
258 * only toy with things in the RMO region. From here, we do
259 * some early parsing of the device-tree to setup out MEMBLOCK
260 * data structures, and allocate & initialize the hash table
261 * and segment tables so we can start running with translation
264 * It is this function which will call the probe() callback of
265 * the various platform types and copy the matching one to the
266 * global ppc_md structure. Your platform can eventually do
267 * some very early initializations from the probe() routine, but
268 * this is not recommended, be very careful as, for example, the
269 * device-tree is not accessible via normal means at this point.
272 void __init early_setup(unsigned long dt_ptr)
274 static __initdata struct paca_struct boot_paca;
276 /* -------- printk is _NOT_ safe to use here ! ------- */
278 /* Try new device tree based feature discovery ... */
279 if (!dt_cpu_ftrs_init(__va(dt_ptr)))
280 /* Otherwise use the old style CPU table */
281 identify_cpu(0, mfspr(SPRN_PVR));
283 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */
284 initialise_paca(&boot_paca, 0);
285 setup_paca(&boot_paca);
288 /* -------- printk is now safe to use ------- */
290 /* Enable early debugging if any specified (see udbg.h) */
293 DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr);
296 * Do early initialization using the flattened device
297 * tree, such as retrieving the physical memory map or
298 * calculating/retrieving the hash table size.
300 early_init_devtree(__va(dt_ptr));
302 /* Now we know the logical id of our boot cpu, setup the paca. */
303 setup_paca(&paca[boot_cpuid]);
307 * Configure exception handlers. This include setting up trampolines
308 * if needed, setting exception endian mode, etc...
310 configure_exceptions();
312 /* Apply all the dynamic patching */
313 apply_feature_fixups();
314 setup_feature_keys();
316 /* Initialize the hash table or TLB handling */
320 * At this point, we can let interrupts switch to virtual mode
321 * (the MMU has been setup), so adjust the MSR in the PACA to
322 * have IR and DR set and enable AIL if it exists
324 cpu_ready_for_interrupts();
326 DBG(" <- early_setup()\n");
328 #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
330 * This needs to be done *last* (after the above DBG() even)
332 * Right after we return from this function, we turn on the MMU
333 * which means the real-mode access trick that btext does will
334 * no longer work, it needs to switch to using a real MMU
335 * mapping. This call will ensure that it does
338 #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
342 void early_setup_secondary(void)
344 /* Mark interrupts disabled in PACA */
345 get_paca()->soft_enabled = 0;
347 /* Initialize the hash table or TLB handling */
348 early_init_mmu_secondary();
351 * At this point, we can let interrupts switch to virtual mode
352 * (the MMU has been setup), so adjust the MSR in the PACA to
353 * have IR and DR set.
355 cpu_ready_for_interrupts();
358 #endif /* CONFIG_SMP */
360 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)
361 static bool use_spinloop(void)
363 if (!IS_ENABLED(CONFIG_PPC_BOOK3E))
367 * When book3e boots from kexec, the ePAPR spin table does
370 return of_property_read_bool(of_chosen, "linux,booted-from-kexec");
373 void smp_release_cpus(void)
381 DBG(" -> smp_release_cpus()\n");
383 /* All secondary cpus are spinning on a common spinloop, release them
384 * all now so they can start to spin on their individual paca
385 * spinloops. For non SMP kernels, the secondary cpus never get out
386 * of the common spinloop.
389 ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop
391 *ptr = ppc_function_entry(generic_secondary_smp_init);
393 /* And wait a bit for them to catch up */
394 for (i = 0; i < 100000; i++) {
397 if (spinning_secondaries == 0)
401 DBG("spinning_secondaries = %d\n", spinning_secondaries);
403 DBG(" <- smp_release_cpus()\n");
405 #endif /* CONFIG_SMP || CONFIG_KEXEC_CORE */
408 * Initialize some remaining members of the ppc64_caches and systemcfg
410 * (at least until we get rid of them completely). This is mostly some
411 * cache informations about the CPU that will be used by cache flush
412 * routines and/or provided to userland
415 static void init_cache_info(struct ppc_cache_info *info, u32 size, u32 lsize,
420 info->line_size = lsize;
421 info->block_size = bsize;
422 info->log_block_size = __ilog2(bsize);
424 info->blocks_per_page = PAGE_SIZE / bsize;
426 info->blocks_per_page = 0;
429 info->assoc = 0xffff;
431 info->assoc = size / (sets * lsize);
434 static bool __init parse_cache_info(struct device_node *np,
436 struct ppc_cache_info *info)
438 static const char *ipropnames[] __initdata = {
441 "i-cache-block-size",
444 static const char *dpropnames[] __initdata = {
447 "d-cache-block-size",
450 const char **propnames = icache ? ipropnames : dpropnames;
451 const __be32 *sizep, *lsizep, *bsizep, *setsp;
452 u32 size, lsize, bsize, sets;
457 lsize = bsize = cur_cpu_spec->dcache_bsize;
458 sizep = of_get_property(np, propnames[0], NULL);
460 size = be32_to_cpu(*sizep);
461 setsp = of_get_property(np, propnames[1], NULL);
463 sets = be32_to_cpu(*setsp);
464 bsizep = of_get_property(np, propnames[2], NULL);
465 lsizep = of_get_property(np, propnames[3], NULL);
469 lsize = be32_to_cpu(*lsizep);
471 bsize = be32_to_cpu(*bsizep);
472 if (sizep == NULL || bsizep == NULL || lsizep == NULL)
476 * OF is weird .. it represents fully associative caches
477 * as "1 way" which doesn't make much sense and doesn't
478 * leave room for direct mapped. We'll assume that 0
479 * in OF means direct mapped for that reason.
486 init_cache_info(info, size, lsize, bsize, sets);
491 void __init initialize_cache_info(void)
493 struct device_node *cpu = NULL, *l2, *l3 = NULL;
496 DBG(" -> initialize_cache_info()\n");
499 * All shipping POWER8 machines have a firmware bug that
500 * puts incorrect information in the device-tree. This will
501 * be (hopefully) fixed for future chips but for now hard
502 * code the values if we are running on one of these
504 pvr = PVR_VER(mfspr(SPRN_PVR));
505 if (pvr == PVR_POWER8 || pvr == PVR_POWER8E ||
506 pvr == PVR_POWER8NVL) {
507 /* size lsize blk sets */
508 init_cache_info(&ppc64_caches.l1i, 0x8000, 128, 128, 32);
509 init_cache_info(&ppc64_caches.l1d, 0x10000, 128, 128, 64);
510 init_cache_info(&ppc64_caches.l2, 0x80000, 128, 0, 512);
511 init_cache_info(&ppc64_caches.l3, 0x800000, 128, 0, 8192);
513 cpu = of_find_node_by_type(NULL, "cpu");
516 * We're assuming *all* of the CPUs have the same
517 * d-cache and i-cache sizes... -Peter
520 if (!parse_cache_info(cpu, false, &ppc64_caches.l1d))
521 DBG("Argh, can't find dcache properties !\n");
523 if (!parse_cache_info(cpu, true, &ppc64_caches.l1i))
524 DBG("Argh, can't find icache properties !\n");
527 * Try to find the L2 and L3 if any. Assume they are
528 * unified and use the D-side properties.
530 l2 = of_find_next_cache_node(cpu);
533 parse_cache_info(l2, false, &ppc64_caches.l2);
534 l3 = of_find_next_cache_node(l2);
538 parse_cache_info(l3, false, &ppc64_caches.l3);
543 /* For use by binfmt_elf */
544 dcache_bsize = ppc64_caches.l1d.block_size;
545 icache_bsize = ppc64_caches.l1i.block_size;
547 cur_cpu_spec->dcache_bsize = dcache_bsize;
548 cur_cpu_spec->icache_bsize = icache_bsize;
550 DBG(" <- initialize_cache_info()\n");
553 /* This returns the limit below which memory accesses to the linear
554 * mapping are guarnateed not to cause a TLB or SLB miss. This is
555 * used to allocate interrupt or emergency stacks for which our
556 * exception entry path doesn't deal with being interrupted.
558 static __init u64 safe_stack_limit(void)
560 #ifdef CONFIG_PPC_BOOK3E
561 /* Freescale BookE bolts the entire linear mapping */
562 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E))
563 return linear_map_top;
564 /* Other BookE, we assume the first GB is bolted */
567 /* BookS, the first segment is bolted */
568 if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
569 return 1UL << SID_SHIFT_1T;
570 return 1UL << SID_SHIFT;
574 void __init irqstack_early_init(void)
576 u64 limit = safe_stack_limit();
580 * Interrupt stacks must be in the first segment since we
581 * cannot afford to take SLB misses on them.
583 for_each_possible_cpu(i) {
584 softirq_ctx[i] = (struct thread_info *)
585 __va(memblock_alloc_base(THREAD_SIZE,
586 THREAD_SIZE, limit));
587 hardirq_ctx[i] = (struct thread_info *)
588 __va(memblock_alloc_base(THREAD_SIZE,
589 THREAD_SIZE, limit));
593 #ifdef CONFIG_PPC_BOOK3E
594 void __init exc_lvl_early_init(void)
599 for_each_possible_cpu(i) {
600 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
601 critirq_ctx[i] = (struct thread_info *)__va(sp);
602 paca[i].crit_kstack = __va(sp + THREAD_SIZE);
604 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
605 dbgirq_ctx[i] = (struct thread_info *)__va(sp);
606 paca[i].dbg_kstack = __va(sp + THREAD_SIZE);
608 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
609 mcheckirq_ctx[i] = (struct thread_info *)__va(sp);
610 paca[i].mc_kstack = __va(sp + THREAD_SIZE);
613 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
614 patch_exception(0x040, exc_debug_debug_book3e);
619 * Stack space used when we detect a bad kernel stack pointer, and
620 * early in SMP boots before relocation is enabled. Exclusive emergency
621 * stack for machine checks.
623 void __init emergency_stack_init(void)
629 * Emergency stacks must be under 256MB, we cannot afford to take
630 * SLB misses on them. The ABI also requires them to be 128-byte
633 * Since we use these as temporary stacks during secondary CPU
634 * bringup, we need to get at them in real mode. This means they
635 * must also be within the RMO region.
637 limit = min(safe_stack_limit(), ppc64_rma_size);
639 for_each_possible_cpu(i) {
640 struct thread_info *ti;
641 ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit));
642 klp_init_thread_info(ti);
643 paca[i].emergency_sp = (void *)ti + THREAD_SIZE;
645 #ifdef CONFIG_PPC_BOOK3S_64
646 /* emergency stack for NMI exception handling. */
647 ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit));
648 klp_init_thread_info(ti);
649 paca[i].nmi_emergency_sp = (void *)ti + THREAD_SIZE;
651 /* emergency stack for machine check exception handling. */
652 ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit));
653 klp_init_thread_info(ti);
654 paca[i].mc_emergency_sp = (void *)ti + THREAD_SIZE;
660 #define PCPU_DYN_SIZE ()
662 static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align)
664 return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align,
665 __pa(MAX_DMA_ADDRESS));
668 static void __init pcpu_fc_free(void *ptr, size_t size)
670 free_bootmem(__pa(ptr), size);
673 static int pcpu_cpu_distance(unsigned int from, unsigned int to)
675 if (cpu_to_node(from) == cpu_to_node(to))
676 return LOCAL_DISTANCE;
678 return REMOTE_DISTANCE;
681 unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
682 EXPORT_SYMBOL(__per_cpu_offset);
684 void __init setup_per_cpu_areas(void)
686 const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE;
693 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need
694 * to group units. For larger mappings, use 1M atom which
695 * should be large enough to contain a number of units.
697 if (mmu_linear_psize == MMU_PAGE_4K)
698 atom_size = PAGE_SIZE;
702 rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance,
703 pcpu_fc_alloc, pcpu_fc_free);
705 panic("cannot initialize percpu area (err=%d)", rc);
707 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
708 for_each_possible_cpu(cpu) {
709 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
710 paca[cpu].data_offset = __per_cpu_offset[cpu];
715 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
716 unsigned long memory_block_size_bytes(void)
718 if (ppc_md.memory_block_size)
719 return ppc_md.memory_block_size();
721 return MIN_MEMORY_BLOCK_SIZE;
725 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
726 struct ppc_pci_io ppc_pci_io;
727 EXPORT_SYMBOL(ppc_pci_io);
730 #ifdef CONFIG_HARDLOCKUP_DETECTOR
731 u64 hw_nmi_get_sample_period(int watchdog_thresh)
733 return ppc_proc_freq * watchdog_thresh;
737 * The hardlockup detector breaks PMU event based branches and is likely
738 * to get false positives in KVM guests, so disable it by default.
740 static int __init disable_hardlockup_detector(void)
742 hardlockup_detector_disable();
746 early_initcall(disable_hardlockup_detector);