1 #include <linux/device.h>
4 #include <linux/percpu.h>
5 #include <linux/init.h>
6 #include <linux/sched.h>
7 #include <linux/export.h>
8 #include <linux/nodemask.h>
9 #include <linux/cpumask.h>
10 #include <linux/notifier.h>
12 #include <asm/current.h>
13 #include <asm/processor.h>
14 #include <asm/cputable.h>
15 #include <asm/hvcall.h>
17 #include <asm/machdep.h>
21 #include "cacheinfo.h"
25 #include <asm/lppaca.h>
28 static DEFINE_PER_CPU(struct cpu, cpu_devices);
31 * SMT snooze delay stuff, 64-bit only for now
36 /* Time in microseconds we delay before sleeping in the idle loop */
37 DEFINE_PER_CPU(long, smt_snooze_delay) = { 100 };
39 static ssize_t store_smt_snooze_delay(struct device *dev,
40 struct device_attribute *attr,
44 struct cpu *cpu = container_of(dev, struct cpu, dev);
48 ret = sscanf(buf, "%ld", &snooze);
52 per_cpu(smt_snooze_delay, cpu->dev.id) = snooze;
53 update_smt_snooze_delay(snooze);
58 static ssize_t show_smt_snooze_delay(struct device *dev,
59 struct device_attribute *attr,
62 struct cpu *cpu = container_of(dev, struct cpu, dev);
64 return sprintf(buf, "%ld\n", per_cpu(smt_snooze_delay, cpu->dev.id));
67 static DEVICE_ATTR(smt_snooze_delay, 0644, show_smt_snooze_delay,
68 store_smt_snooze_delay);
70 static int __init setup_smt_snooze_delay(char *str)
75 if (!cpu_has_feature(CPU_FTR_SMT))
78 snooze = simple_strtol(str, NULL, 10);
79 for_each_possible_cpu(cpu)
80 per_cpu(smt_snooze_delay, cpu) = snooze;
84 __setup("smt-snooze-delay=", setup_smt_snooze_delay);
86 #endif /* CONFIG_PPC64 */
89 * Enabling PMCs will slow partition context switch times so we only do
90 * it the first time we write to the PMCs.
93 static DEFINE_PER_CPU(char, pmcs_enabled);
95 void ppc_enable_pmcs(void)
99 /* Only need to enable them once */
100 if (__get_cpu_var(pmcs_enabled))
103 __get_cpu_var(pmcs_enabled) = 1;
105 if (ppc_md.enable_pmcs)
106 ppc_md.enable_pmcs();
108 EXPORT_SYMBOL(ppc_enable_pmcs);
110 #define SYSFS_PMCSETUP(NAME, ADDRESS) \
111 static void read_##NAME(void *val) \
113 *(unsigned long *)val = mfspr(ADDRESS); \
115 static void write_##NAME(void *val) \
118 mtspr(ADDRESS, *(unsigned long *)val); \
120 static ssize_t show_##NAME(struct device *dev, \
121 struct device_attribute *attr, \
124 struct cpu *cpu = container_of(dev, struct cpu, dev); \
126 smp_call_function_single(cpu->dev.id, read_##NAME, &val, 1); \
127 return sprintf(buf, "%lx\n", val); \
129 static ssize_t __used \
130 store_##NAME(struct device *dev, struct device_attribute *attr, \
131 const char *buf, size_t count) \
133 struct cpu *cpu = container_of(dev, struct cpu, dev); \
135 int ret = sscanf(buf, "%lx", &val); \
138 smp_call_function_single(cpu->dev.id, write_##NAME, &val, 1); \
143 /* Let's define all possible registers, we'll only hook up the ones
144 * that are implemented on the current processor
147 #if defined(CONFIG_PPC64)
148 #define HAS_PPC_PMC_CLASSIC 1
149 #define HAS_PPC_PMC_IBM 1
150 #define HAS_PPC_PMC_PA6T 1
151 #elif defined(CONFIG_6xx)
152 #define HAS_PPC_PMC_CLASSIC 1
153 #define HAS_PPC_PMC_IBM 1
154 #define HAS_PPC_PMC_G4 1
158 #ifdef HAS_PPC_PMC_CLASSIC
159 SYSFS_PMCSETUP(mmcr0, SPRN_MMCR0);
160 SYSFS_PMCSETUP(mmcr1, SPRN_MMCR1);
161 SYSFS_PMCSETUP(pmc1, SPRN_PMC1);
162 SYSFS_PMCSETUP(pmc2, SPRN_PMC2);
163 SYSFS_PMCSETUP(pmc3, SPRN_PMC3);
164 SYSFS_PMCSETUP(pmc4, SPRN_PMC4);
165 SYSFS_PMCSETUP(pmc5, SPRN_PMC5);
166 SYSFS_PMCSETUP(pmc6, SPRN_PMC6);
168 #ifdef HAS_PPC_PMC_G4
169 SYSFS_PMCSETUP(mmcr2, SPRN_MMCR2);
173 SYSFS_PMCSETUP(pmc7, SPRN_PMC7);
174 SYSFS_PMCSETUP(pmc8, SPRN_PMC8);
176 SYSFS_PMCSETUP(mmcra, SPRN_MMCRA);
177 SYSFS_PMCSETUP(purr, SPRN_PURR);
178 SYSFS_PMCSETUP(spurr, SPRN_SPURR);
179 SYSFS_PMCSETUP(dscr, SPRN_DSCR);
180 SYSFS_PMCSETUP(pir, SPRN_PIR);
182 static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra);
183 static DEVICE_ATTR(spurr, 0600, show_spurr, NULL);
184 static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr);
185 static DEVICE_ATTR(purr, 0600, show_purr, store_purr);
186 static DEVICE_ATTR(pir, 0400, show_pir, NULL);
188 unsigned long dscr_default = 0;
189 EXPORT_SYMBOL(dscr_default);
191 static ssize_t show_dscr_default(struct device *dev,
192 struct device_attribute *attr, char *buf)
194 return sprintf(buf, "%lx\n", dscr_default);
197 static void update_dscr(void *dummy)
199 if (!current->thread.dscr_inherit)
200 mtspr(SPRN_DSCR, dscr_default);
203 static ssize_t __used store_dscr_default(struct device *dev,
204 struct device_attribute *attr, const char *buf,
210 ret = sscanf(buf, "%lx", &val);
215 on_each_cpu(update_dscr, NULL, 1);
220 static DEVICE_ATTR(dscr_default, 0600,
221 show_dscr_default, store_dscr_default);
223 static void sysfs_create_dscr_default(void)
226 if (cpu_has_feature(CPU_FTR_DSCR))
227 err = device_create_file(cpu_subsys.dev_root, &dev_attr_dscr_default);
229 #endif /* CONFIG_PPC64 */
231 #ifdef HAS_PPC_PMC_PA6T
232 SYSFS_PMCSETUP(pa6t_pmc0, SPRN_PA6T_PMC0);
233 SYSFS_PMCSETUP(pa6t_pmc1, SPRN_PA6T_PMC1);
234 SYSFS_PMCSETUP(pa6t_pmc2, SPRN_PA6T_PMC2);
235 SYSFS_PMCSETUP(pa6t_pmc3, SPRN_PA6T_PMC3);
236 SYSFS_PMCSETUP(pa6t_pmc4, SPRN_PA6T_PMC4);
237 SYSFS_PMCSETUP(pa6t_pmc5, SPRN_PA6T_PMC5);
238 #ifdef CONFIG_DEBUG_KERNEL
239 SYSFS_PMCSETUP(hid0, SPRN_HID0);
240 SYSFS_PMCSETUP(hid1, SPRN_HID1);
241 SYSFS_PMCSETUP(hid4, SPRN_HID4);
242 SYSFS_PMCSETUP(hid5, SPRN_HID5);
243 SYSFS_PMCSETUP(ima0, SPRN_PA6T_IMA0);
244 SYSFS_PMCSETUP(ima1, SPRN_PA6T_IMA1);
245 SYSFS_PMCSETUP(ima2, SPRN_PA6T_IMA2);
246 SYSFS_PMCSETUP(ima3, SPRN_PA6T_IMA3);
247 SYSFS_PMCSETUP(ima4, SPRN_PA6T_IMA4);
248 SYSFS_PMCSETUP(ima5, SPRN_PA6T_IMA5);
249 SYSFS_PMCSETUP(ima6, SPRN_PA6T_IMA6);
250 SYSFS_PMCSETUP(ima7, SPRN_PA6T_IMA7);
251 SYSFS_PMCSETUP(ima8, SPRN_PA6T_IMA8);
252 SYSFS_PMCSETUP(ima9, SPRN_PA6T_IMA9);
253 SYSFS_PMCSETUP(imaat, SPRN_PA6T_IMAAT);
254 SYSFS_PMCSETUP(btcr, SPRN_PA6T_BTCR);
255 SYSFS_PMCSETUP(pccr, SPRN_PA6T_PCCR);
256 SYSFS_PMCSETUP(rpccr, SPRN_PA6T_RPCCR);
257 SYSFS_PMCSETUP(der, SPRN_PA6T_DER);
258 SYSFS_PMCSETUP(mer, SPRN_PA6T_MER);
259 SYSFS_PMCSETUP(ber, SPRN_PA6T_BER);
260 SYSFS_PMCSETUP(ier, SPRN_PA6T_IER);
261 SYSFS_PMCSETUP(sier, SPRN_PA6T_SIER);
262 SYSFS_PMCSETUP(siar, SPRN_PA6T_SIAR);
263 SYSFS_PMCSETUP(tsr0, SPRN_PA6T_TSR0);
264 SYSFS_PMCSETUP(tsr1, SPRN_PA6T_TSR1);
265 SYSFS_PMCSETUP(tsr2, SPRN_PA6T_TSR2);
266 SYSFS_PMCSETUP(tsr3, SPRN_PA6T_TSR3);
267 #endif /* CONFIG_DEBUG_KERNEL */
268 #endif /* HAS_PPC_PMC_PA6T */
270 #ifdef HAS_PPC_PMC_IBM
271 static struct device_attribute ibm_common_attrs[] = {
272 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
273 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
275 #endif /* HAS_PPC_PMC_G4 */
277 #ifdef HAS_PPC_PMC_G4
278 static struct device_attribute g4_common_attrs[] = {
279 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
280 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
281 __ATTR(mmcr2, 0600, show_mmcr2, store_mmcr2),
283 #endif /* HAS_PPC_PMC_G4 */
285 static struct device_attribute classic_pmc_attrs[] = {
286 __ATTR(pmc1, 0600, show_pmc1, store_pmc1),
287 __ATTR(pmc2, 0600, show_pmc2, store_pmc2),
288 __ATTR(pmc3, 0600, show_pmc3, store_pmc3),
289 __ATTR(pmc4, 0600, show_pmc4, store_pmc4),
290 __ATTR(pmc5, 0600, show_pmc5, store_pmc5),
291 __ATTR(pmc6, 0600, show_pmc6, store_pmc6),
293 __ATTR(pmc7, 0600, show_pmc7, store_pmc7),
294 __ATTR(pmc8, 0600, show_pmc8, store_pmc8),
298 #ifdef HAS_PPC_PMC_PA6T
299 static struct device_attribute pa6t_attrs[] = {
300 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
301 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
302 __ATTR(pmc0, 0600, show_pa6t_pmc0, store_pa6t_pmc0),
303 __ATTR(pmc1, 0600, show_pa6t_pmc1, store_pa6t_pmc1),
304 __ATTR(pmc2, 0600, show_pa6t_pmc2, store_pa6t_pmc2),
305 __ATTR(pmc3, 0600, show_pa6t_pmc3, store_pa6t_pmc3),
306 __ATTR(pmc4, 0600, show_pa6t_pmc4, store_pa6t_pmc4),
307 __ATTR(pmc5, 0600, show_pa6t_pmc5, store_pa6t_pmc5),
308 #ifdef CONFIG_DEBUG_KERNEL
309 __ATTR(hid0, 0600, show_hid0, store_hid0),
310 __ATTR(hid1, 0600, show_hid1, store_hid1),
311 __ATTR(hid4, 0600, show_hid4, store_hid4),
312 __ATTR(hid5, 0600, show_hid5, store_hid5),
313 __ATTR(ima0, 0600, show_ima0, store_ima0),
314 __ATTR(ima1, 0600, show_ima1, store_ima1),
315 __ATTR(ima2, 0600, show_ima2, store_ima2),
316 __ATTR(ima3, 0600, show_ima3, store_ima3),
317 __ATTR(ima4, 0600, show_ima4, store_ima4),
318 __ATTR(ima5, 0600, show_ima5, store_ima5),
319 __ATTR(ima6, 0600, show_ima6, store_ima6),
320 __ATTR(ima7, 0600, show_ima7, store_ima7),
321 __ATTR(ima8, 0600, show_ima8, store_ima8),
322 __ATTR(ima9, 0600, show_ima9, store_ima9),
323 __ATTR(imaat, 0600, show_imaat, store_imaat),
324 __ATTR(btcr, 0600, show_btcr, store_btcr),
325 __ATTR(pccr, 0600, show_pccr, store_pccr),
326 __ATTR(rpccr, 0600, show_rpccr, store_rpccr),
327 __ATTR(der, 0600, show_der, store_der),
328 __ATTR(mer, 0600, show_mer, store_mer),
329 __ATTR(ber, 0600, show_ber, store_ber),
330 __ATTR(ier, 0600, show_ier, store_ier),
331 __ATTR(sier, 0600, show_sier, store_sier),
332 __ATTR(siar, 0600, show_siar, store_siar),
333 __ATTR(tsr0, 0600, show_tsr0, store_tsr0),
334 __ATTR(tsr1, 0600, show_tsr1, store_tsr1),
335 __ATTR(tsr2, 0600, show_tsr2, store_tsr2),
336 __ATTR(tsr3, 0600, show_tsr3, store_tsr3),
337 #endif /* CONFIG_DEBUG_KERNEL */
339 #endif /* HAS_PPC_PMC_PA6T */
340 #endif /* HAS_PPC_PMC_CLASSIC */
342 static void __cpuinit register_cpu_online(unsigned int cpu)
344 struct cpu *c = &per_cpu(cpu_devices, cpu);
345 struct device *s = &c->dev;
346 struct device_attribute *attrs, *pmc_attrs;
350 if (cpu_has_feature(CPU_FTR_SMT))
351 device_create_file(s, &dev_attr_smt_snooze_delay);
355 switch (cur_cpu_spec->pmc_type) {
356 #ifdef HAS_PPC_PMC_IBM
358 attrs = ibm_common_attrs;
359 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
360 pmc_attrs = classic_pmc_attrs;
362 #endif /* HAS_PPC_PMC_IBM */
363 #ifdef HAS_PPC_PMC_G4
365 attrs = g4_common_attrs;
366 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
367 pmc_attrs = classic_pmc_attrs;
369 #endif /* HAS_PPC_PMC_G4 */
370 #ifdef HAS_PPC_PMC_PA6T
372 /* PA Semi starts counting at PMC0 */
374 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
377 #endif /* HAS_PPC_PMC_PA6T */
384 for (i = 0; i < nattrs; i++)
385 device_create_file(s, &attrs[i]);
388 for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
389 device_create_file(s, &pmc_attrs[i]);
392 if (cpu_has_feature(CPU_FTR_MMCRA))
393 device_create_file(s, &dev_attr_mmcra);
395 if (cpu_has_feature(CPU_FTR_PURR))
396 device_create_file(s, &dev_attr_purr);
398 if (cpu_has_feature(CPU_FTR_SPURR))
399 device_create_file(s, &dev_attr_spurr);
401 if (cpu_has_feature(CPU_FTR_DSCR))
402 device_create_file(s, &dev_attr_dscr);
404 if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
405 device_create_file(s, &dev_attr_pir);
406 #endif /* CONFIG_PPC64 */
408 cacheinfo_cpu_online(cpu);
411 #ifdef CONFIG_HOTPLUG_CPU
412 static void unregister_cpu_online(unsigned int cpu)
414 struct cpu *c = &per_cpu(cpu_devices, cpu);
415 struct device *s = &c->dev;
416 struct device_attribute *attrs, *pmc_attrs;
419 BUG_ON(!c->hotpluggable);
422 if (cpu_has_feature(CPU_FTR_SMT))
423 device_remove_file(s, &dev_attr_smt_snooze_delay);
427 switch (cur_cpu_spec->pmc_type) {
428 #ifdef HAS_PPC_PMC_IBM
430 attrs = ibm_common_attrs;
431 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
432 pmc_attrs = classic_pmc_attrs;
434 #endif /* HAS_PPC_PMC_IBM */
435 #ifdef HAS_PPC_PMC_G4
437 attrs = g4_common_attrs;
438 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
439 pmc_attrs = classic_pmc_attrs;
441 #endif /* HAS_PPC_PMC_G4 */
442 #ifdef HAS_PPC_PMC_PA6T
444 /* PA Semi starts counting at PMC0 */
446 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
449 #endif /* HAS_PPC_PMC_PA6T */
456 for (i = 0; i < nattrs; i++)
457 device_remove_file(s, &attrs[i]);
460 for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
461 device_remove_file(s, &pmc_attrs[i]);
464 if (cpu_has_feature(CPU_FTR_MMCRA))
465 device_remove_file(s, &dev_attr_mmcra);
467 if (cpu_has_feature(CPU_FTR_PURR))
468 device_remove_file(s, &dev_attr_purr);
470 if (cpu_has_feature(CPU_FTR_SPURR))
471 device_remove_file(s, &dev_attr_spurr);
473 if (cpu_has_feature(CPU_FTR_DSCR))
474 device_remove_file(s, &dev_attr_dscr);
476 if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
477 device_remove_file(s, &dev_attr_pir);
478 #endif /* CONFIG_PPC64 */
480 cacheinfo_cpu_offline(cpu);
483 #ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
484 ssize_t arch_cpu_probe(const char *buf, size_t count)
486 if (ppc_md.cpu_probe)
487 return ppc_md.cpu_probe(buf, count);
492 ssize_t arch_cpu_release(const char *buf, size_t count)
494 if (ppc_md.cpu_release)
495 return ppc_md.cpu_release(buf, count);
499 #endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */
501 #endif /* CONFIG_HOTPLUG_CPU */
503 static int __cpuinit sysfs_cpu_notify(struct notifier_block *self,
504 unsigned long action, void *hcpu)
506 unsigned int cpu = (unsigned int)(long)hcpu;
510 case CPU_ONLINE_FROZEN:
511 register_cpu_online(cpu);
513 #ifdef CONFIG_HOTPLUG_CPU
515 case CPU_DEAD_FROZEN:
516 unregister_cpu_online(cpu);
523 static struct notifier_block __cpuinitdata sysfs_cpu_nb = {
524 .notifier_call = sysfs_cpu_notify,
527 static DEFINE_MUTEX(cpu_mutex);
529 int cpu_add_dev_attr(struct device_attribute *attr)
533 mutex_lock(&cpu_mutex);
535 for_each_possible_cpu(cpu) {
536 device_create_file(get_cpu_device(cpu), attr);
539 mutex_unlock(&cpu_mutex);
542 EXPORT_SYMBOL_GPL(cpu_add_dev_attr);
544 int cpu_add_dev_attr_group(struct attribute_group *attrs)
550 mutex_lock(&cpu_mutex);
552 for_each_possible_cpu(cpu) {
553 dev = get_cpu_device(cpu);
554 ret = sysfs_create_group(&dev->kobj, attrs);
558 mutex_unlock(&cpu_mutex);
561 EXPORT_SYMBOL_GPL(cpu_add_dev_attr_group);
564 void cpu_remove_dev_attr(struct device_attribute *attr)
568 mutex_lock(&cpu_mutex);
570 for_each_possible_cpu(cpu) {
571 device_remove_file(get_cpu_device(cpu), attr);
574 mutex_unlock(&cpu_mutex);
576 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr);
578 void cpu_remove_dev_attr_group(struct attribute_group *attrs)
583 mutex_lock(&cpu_mutex);
585 for_each_possible_cpu(cpu) {
586 dev = get_cpu_device(cpu);
587 sysfs_remove_group(&dev->kobj, attrs);
590 mutex_unlock(&cpu_mutex);
592 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr_group);
598 static void register_nodes(void)
602 for (i = 0; i < MAX_NUMNODES; i++)
603 register_one_node(i);
606 int sysfs_add_device_to_node(struct device *dev, int nid)
608 struct node *node = &node_devices[nid];
609 return sysfs_create_link(&node->dev.kobj, &dev->kobj,
610 kobject_name(&dev->kobj));
612 EXPORT_SYMBOL_GPL(sysfs_add_device_to_node);
614 void sysfs_remove_device_from_node(struct device *dev, int nid)
616 struct node *node = &node_devices[nid];
617 sysfs_remove_link(&node->dev.kobj, kobject_name(&dev->kobj));
619 EXPORT_SYMBOL_GPL(sysfs_remove_device_from_node);
622 static void register_nodes(void)
629 /* Only valid if CPU is present. */
630 static ssize_t show_physical_id(struct device *dev,
631 struct device_attribute *attr, char *buf)
633 struct cpu *cpu = container_of(dev, struct cpu, dev);
635 return sprintf(buf, "%d\n", get_hard_smp_processor_id(cpu->dev.id));
637 static DEVICE_ATTR(physical_id, 0444, show_physical_id, NULL);
639 static int __init topology_init(void)
644 register_cpu_notifier(&sysfs_cpu_nb);
646 for_each_possible_cpu(cpu) {
647 struct cpu *c = &per_cpu(cpu_devices, cpu);
650 * For now, we just see if the system supports making
651 * the RTAS calls for CPU hotplug. But, there may be a
652 * more comprehensive way to do this for an individual
653 * CPU. For instance, the boot cpu might never be valid
659 if (cpu_online(cpu) || c->hotpluggable) {
660 register_cpu(c, cpu);
662 device_create_file(&c->dev, &dev_attr_physical_id);
666 register_cpu_online(cpu);
669 sysfs_create_dscr_default();
670 #endif /* CONFIG_PPC64 */
674 subsys_initcall(topology_init);