2 * Transactional memory support routines to reclaim and recheckpoint
3 * transactional process state.
5 * Copyright 2012 Matt Evans & Michael Neuling, IBM Corporation.
8 #include <asm/asm-offsets.h>
9 #include <asm/ppc_asm.h>
10 #include <asm/ppc-opcode.h>
11 #include <asm/ptrace.h>
16 /* See fpu.S, this is borrowed from there */
17 #define __SAVE_32FPRS_VSRS(n,c,base) \
20 END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
21 SAVE_32FPRS(n,base); \
23 2: SAVE_32VSRS(n,c,base); \
25 #define __REST_32FPRS_VSRS(n,c,base) \
28 END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
29 REST_32FPRS(n,base); \
31 2: REST_32VSRS(n,c,base); \
34 #define __SAVE_32FPRS_VSRS(n,c,base) SAVE_32FPRS(n, base)
35 #define __REST_32FPRS_VSRS(n,c,base) REST_32FPRS(n, base)
37 #define SAVE_32FPRS_VSRS(n,c,base) \
38 __SAVE_32FPRS_VSRS(n,__REG_##c,__REG_##base)
39 #define REST_32FPRS_VSRS(n,c,base) \
40 __REST_32FPRS_VSRS(n,__REG_##c,__REG_##base)
42 /* Stack frame offsets for local variables. */
43 #define TM_FRAME_L0 TM_FRAME_SIZE-16
44 #define TM_FRAME_L1 TM_FRAME_SIZE-8
45 #define STACK_PARAM(x) (48+((x)*8))
48 /* In order to access the TM SPRs, TM must be enabled. So, do so: */
61 std r0, THREAD_TM_TFHAR(r3)
63 std r0, THREAD_TM_TEXASR(r3)
65 std r0, THREAD_TM_TFIAR(r3)
68 _GLOBAL(tm_restore_sprs)
69 ld r0, THREAD_TM_TFHAR(r3)
71 ld r0, THREAD_TM_TEXASR(r3)
73 ld r0, THREAD_TM_TFIAR(r3)
77 /* Passed an 8-bit failure cause as first argument. */
84 .tc dscr_default[TC],dscr_default
88 /* void tm_reclaim(struct thread_struct *thread,
89 * unsigned long orig_msr,
92 * - Performs a full reclaim. This destroys outstanding
93 * transactions and updates thread->regs.tm_ckpt_* with the
94 * original checkpointed state. Note that thread->regs is
96 * - FP regs are written back to thread->transact_fpr before
97 * reclaiming. These are the transactional (current) versions.
99 * Purpose is to both abort transactions of, and preserve the state of,
100 * a transactions at a context switch. We preserve/restore both sets of process
101 * state to restore them when the thread's scheduled again. We continue in
102 * userland as though nothing happened, but when the transaction is resumed
103 * they will abort back to the checkpointed state we save out here.
105 * Call with IRQs off, stacks get all out of sync for some periods in here!
113 stdu r1, -TM_FRAME_SIZE(r1)
115 /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. */
117 std r3, STACK_PARAM(0)(r1)
120 /* We need to setup MSR for VSX register save instructions. Here we
121 * also clear the MSR RI since when we do the treclaim, we won't have a
122 * valid kernel pointer for a while. We clear RI here as it avoids
123 * adding another mtmsr closer to the treclaim. This makes the region
124 * maked as non-recoverable wider than it needs to be but it saves on
125 * inserting another mtmsrd later.
131 ori r16, r16, MSR_EE /* IRQs hard off */
133 oris r15, r15, MSR_VEC@h
136 oris r15,r15, MSR_VSX@h
137 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
140 std r14, TM_FRAME_L0(r1)
142 /* Stash the stack pointer away for use after reclaim */
145 /* ******************** FPR/VR/VSRs ************
146 * Before reclaiming, capture the current/transactional FPR/VR
147 * versions /if used/.
149 * (If VSX used, FP and VMX are implied. Or, we don't need to look
150 * at MSR.VSX as copying FP regs if .FP, vector regs if .VMX covers it.)
152 * We're passed the thread's MSR as parameter 2.
154 * We enabled VEC/FP/VSX in the msr above, so we can execute these
157 andis. r0, r4, MSR_VEC@h
160 addi r7, r3, THREAD_TRANSACT_VRSTATE
161 SAVE_32VRS(0, r6, r7) /* r6 scratch, r7 transact vr state */
166 mfspr r0, SPRN_VRSAVE
167 std r0, THREAD_TRANSACT_VRSAVE(r3)
172 addi r7, r3, THREAD_TRANSACT_FPSTATE
173 SAVE_32FPRS_VSRS(0, R6, R7) /* r6 scratch, r7 transact fp state */
176 stfd fr0,FPSTATE_FPSCR(r7)
179 /* Do sanity check on MSR to make sure we are suspended */
180 li r7, (MSR_TS_S)@higher
184 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
186 /* The moment we treclaim, ALL of our GPRs will switch
187 * to user register state. (FPRs, CCR etc. also!)
188 * Use an sprg and a tm_scratch in the PACA to shuffle.
190 TRECLAIM(R5) /* Cause in r5 */
192 /* ******************** GPRs ******************** */
193 /* Stash the checkpointed r13 away in the scratch SPR and get the real
199 /* Stash the checkpointed r1 away in paca tm_scratch and get the real
202 std r1, PACATMSCRATCH(r13)
205 /* Store the PPR in r11 and reset to decent value */
206 std r11, GPR11(r1) /* Temporary stash */
210 /* Now get some more GPRS free */
211 std r7, GPR7(r1) /* Temporary stash */
212 std r12, GPR12(r1) /* '' '' '' */
213 ld r12, STACK_PARAM(0)(r1) /* Param 0, thread_struct * */
215 std r11, THREAD_TM_PPR(r12) /* Store PPR and free r11 */
217 addi r7, r12, PT_CKPT_REGS /* Thread's ckpt_regs */
219 /* Make r7 look like an exception frame so that we
220 * can use the neat GPRx(n) macros. r7 is NOT a pt_regs ptr!
222 subi r7, r7, STACK_FRAME_OVERHEAD
224 /* Sync the userland GPRs 2-12, 14-31 to thread->regs: */
225 SAVE_GPR(0, r7) /* user r0 */
226 SAVE_GPR(2, r7) /* user r2 */
227 SAVE_4GPRS(3, r7) /* user r3-r6 */
228 SAVE_GPR(8, r7) /* user r8 */
229 SAVE_GPR(9, r7) /* user r9 */
230 SAVE_GPR(10, r7) /* user r10 */
231 ld r3, PACATMSCRATCH(r13) /* user r1 */
232 ld r4, GPR7(r1) /* user r7 */
233 ld r5, GPR11(r1) /* user r11 */
234 ld r6, GPR12(r1) /* user r12 */
235 GET_SCRATCH0(8) /* user r13 */
242 SAVE_NVGPRS(r7) /* user r14-r31 */
244 /* ******************** NIP ******************** */
246 std r3, _NIP(r7) /* Returns to failhandler */
247 /* The checkpointed NIP is ignored when rescheduling/rechkpting,
248 * but is used in signal return to 'wind back' to the abort handler.
251 /* ******************** CR,LR,CCR,MSR ********** */
263 /* ******************** TAR, DSCR ********** */
267 std r3, THREAD_TM_TAR(r12)
268 std r4, THREAD_TM_DSCR(r12)
270 /* MSR and flags: We don't change CRs, and we don't need to alter
274 /* TM regs, incl TEXASR -- these live in thread_struct. Note they've
275 * been updated by the treclaim, to explain to userland the failure
278 mfspr r0, SPRN_TEXASR
281 std r0, THREAD_TM_TEXASR(r12)
282 std r3, THREAD_TM_TFHAR(r12)
283 std r4, THREAD_TM_TFIAR(r12)
285 /* AMR is checkpointed too, but is unsupported by Linux. */
287 /* Restore original MSR/IRQ state & clear TM mode */
288 ld r14, TM_FRAME_L0(r1) /* Orig MSR */
290 rldimi r14, r15, MSR_TS_LG, (63-MSR_TS_LG)-1
295 addi r1, r1, TM_FRAME_SIZE
302 /* Load system default DSCR */
303 ld r4, DSCR_DEFAULT@toc(r2)
310 /* void tm_recheckpoint(struct thread_struct *thread,
311 * unsigned long orig_msr)
312 * - Restore the checkpointed register state saved by tm_reclaim
313 * when we switch_to a process.
315 * Call with IRQs off, stacks get all out of sync for
316 * some periods in here!
318 _GLOBAL(__tm_recheckpoint)
324 stdu r1, -TM_FRAME_SIZE(r1)
326 /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD].
327 * This is used for backing up the NVGPRs:
331 /* Load complete register state from ts_ckpt* registers */
333 addi r7, r3, PT_CKPT_REGS /* Thread's ckpt_regs */
335 /* Make r7 look like an exception frame so that we
336 * can use the neat GPRx(n) macros. r7 is now NOT a pt_regs ptr!
338 subi r7, r7, STACK_FRAME_OVERHEAD
343 /* R4 = original MSR to indicate whether thread used FP/Vector etc. */
345 /* Enable FP/vec in MSR if necessary! */
349 beq restore_gprs /* if neither, skip both */
353 oris r5, r5, MSR_VSX@h
354 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
356 or r5, r6, r5 /* Set MSR.FP+.VSX/.VEC */
359 #ifdef CONFIG_ALTIVEC
360 /* FP and VEC registers: These are recheckpointed from thread.fpr[]
361 * and thread.vr[] respectively. The thread.transact_fpr[] version
362 * is more modern, and will be loaded subsequently by any FPUnavailable
365 andis. r0, r4, MSR_VEC@h
368 addi r8, r3, THREAD_VRSTATE
372 REST_32VRS(0, r5, r8) /* r5 scratch, r8 ptr */
374 ld r5, THREAD_VRSAVE(r3)
375 mtspr SPRN_VRSAVE, r5
381 addi r8, r3, THREAD_FPSTATE
382 lfd fr0, FPSTATE_FPSCR(r8)
384 REST_32FPRS_VSRS(0, R4, R8)
387 mtmsr r6 /* FP/Vec off again! */
391 /* ******************** CR,LR,CCR,MSR ********** */
400 /* ******************** TAR ******************** */
401 ld r4, THREAD_TM_TAR(r3)
404 /* Load up the PPR and DSCR in GPRs only at this stage */
405 ld r5, THREAD_TM_DSCR(r3)
406 ld r6, THREAD_TM_PPR(r3)
408 /* Clear the MSR RI since we are about to change R1. EE is already off
413 REST_GPR(0, r7) /* GPR0 */
414 REST_2GPRS(2, r7) /* GPR2-3 */
415 REST_GPR(4, r7) /* GPR4 */
416 REST_4GPRS(8, r7) /* GPR8-11 */
417 REST_2GPRS(12, r7) /* GPR12-13 */
419 REST_NVGPRS(r7) /* GPR14-31 */
421 /* Load up PPR and DSCR here so we don't run with user values for long
426 /* Do final sanity check on TEXASR to make sure FS is set. Do this
427 * here before we load up the userspace r1 so any bugs we hit will get
429 mfspr r5, SPRN_TEXASR
434 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
436 /* Do final sanity check on MSR to make sure we are not transactional
440 li r5, (MSR_TS_MASK)@higher
444 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
450 REST_GPR(1, r7) /* GPR1 */
451 REST_GPR(5, r7) /* GPR5-7 */
455 /* Commit register state as checkpointed state: */
460 /* Our transactional state has now changed.
462 * Now just get out of here. Transactional (current) state will be
463 * updated once restore is called on the return path in the _switch-ed
470 /* R1 is restored, so we are recoverable again. EE is still off */
476 addi r1, r1, TM_FRAME_SIZE
483 /* Load system default DSCR */
484 ld r4, DSCR_DEFAULT@toc(r2)
490 /* ****************************************************************** */