1 #include <asm/processor.h>
2 #include <asm/ppc_asm.h>
4 #include <asm/asm-offsets.h>
5 #include <asm/cputable.h>
6 #include <asm/thread_info.h>
8 #include <asm/ptrace.h>
10 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
11 /* void do_load_up_transact_altivec(struct thread_struct *thread)
13 * This is similar to load_up_altivec but for the transactional version of the
14 * vector regs. It doesn't mess with the task MSR or valid flags.
15 * Furthermore, VEC laziness is not supported with TM currently.
17 _GLOBAL(do_load_up_transact_altivec)
24 stw r4,THREAD_USED_VR(r3)
26 li r10,THREAD_TRANSACT_VRSTATE+VRSTATE_VSCR
29 addi r10,r3,THREAD_TRANSACT_VRSTATE
36 * Load state from memory into VMX registers including VSCR.
37 * Assumes the caller has enabled VMX in the MSR.
39 _GLOBAL(load_vr_state)
47 * Store VMX state into memory, including VSCR.
48 * Assumes the caller has enabled VMX in the MSR.
50 _GLOBAL(store_vr_state)
58 * Disable VMX for the task which had it previously,
59 * and save its vector registers in its thread_struct.
60 * Enables the VMX for use in the kernel on return.
61 * On SMP we know the VMX is free, since we give it up every
62 * switch (ie, no lazy save of the vector registers).
64 * Note that on 32-bit this can only use registers that will be
65 * restored by fast_exception_return, i.e. r3 - r6, r10 and r11.
67 _GLOBAL(load_up_altivec)
68 mfmsr r5 /* grab the current MSR */
70 MTMSRD(r5) /* enable use of AltiVec now */
74 * While userspace in general ignores VRSAVE, glibc uses it as a boolean
75 * to optimise userspace context save/restore. Whenever we take an
76 * altivec unavailable exception we must set VRSAVE to something non
77 * zero. Set it to all 1s. See also the programming note in the ISA.
85 /* enable use of VMX after return */
87 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
90 ld r4,PACACURRENT(r13)
91 addi r5,r4,THREAD /* Get THREAD */
92 oris r12,r12,MSR_VEC@h
95 /* Don't care if r4 overflows, this is desired behaviour */
96 lbz r4,THREAD_LOAD_VEC(r5)
98 stb r4,THREAD_LOAD_VEC(r5)
99 addi r6,r5,THREAD_VRSTATE
102 stw r4,THREAD_USED_VR(r5)
106 /* restore registers and return */
111 * Save the vector registers to its thread_struct
113 _GLOBAL(save_altivec)
114 addi r3,r3,THREAD /* want THREAD of task */
115 PPC_LL r7,THREAD_VRSAVEAREA(r3)
116 PPC_LL r5,PT_REGS(r3)
119 addi r7,r3,THREAD_VRSTATE
120 2: SAVE_32VRS(0,r4,r7)
129 #error This asm code isn't ready for 32-bit kernels
133 * load_up_vsx(unused, unused, tsk)
134 * Disable VSX for the task which had it previously,
135 * and save its vector registers in its thread_struct.
136 * Reuse the fp and vsx saves, but first check to see if they have
137 * been saved already.
140 /* Load FP and VSX registers if they haven't been done yet */
142 beql+ load_up_fpu /* skip if already loaded */
143 andis. r5,r12,MSR_VEC@h
144 beql+ load_up_altivec /* skip if already loaded */
146 ld r4,PACACURRENT(r13)
147 addi r4,r4,THREAD /* Get THREAD */
149 stw r6,THREAD_USED_VSR(r4) /* ... also set thread used vsr */
150 /* enable use of VSX after return */
151 oris r12,r12,MSR_VSX@h
153 b fast_exception_return
155 #endif /* CONFIG_VSX */
159 * The routines below are in assembler so we can closely control the
160 * usage of floating-point registers. These routines must be called
161 * with preempt disabled.
168 .long 0x3f800000 /* 1.0 in single-precision FP */
170 .long 0x3f000000 /* 0.5 in single-precision FP */
172 #define LDCONST(fr, name) \
181 .tc FD_3ff00000_0[TC],0x3ff0000000000000 /* 1.0 */
183 .tc FD_3fe00000_0[TC],0x3fe0000000000000 /* 0.5 */
185 #define LDCONST(fr, name) \
191 * Internal routine to enable floating point and set FPSCR to 0.
192 * Don't call it from C; it doesn't use the normal calling convention.
224 * Vector add, floating point.
241 * Vector subtract, floating point.
258 * Vector multiply and add, floating point.
270 fmadds fr0,fr0,fr2,fr1
278 * Vector negative multiply and subtract, floating point.
290 fnmsubs fr0,fr0,fr2,fr1
298 * Vector reciprocal estimate. We just compute 1.0/x.
299 * r3 -> destination, r4 -> source.
316 * Vector reciprocal square-root estimate, floating point.
317 * We use the frsqrte instruction for the initial estimate followed
318 * by 2 iterations of Newton-Raphson to get sufficient accuracy.
319 * r3 -> destination, r4 -> source.
334 frsqrte fr1,fr0 /* r = frsqrte(s) */
335 fmuls fr3,fr1,fr0 /* r * s */
336 fmuls fr2,fr1,fr5 /* r * 0.5 */
337 fnmsubs fr3,fr1,fr3,fr4 /* 1 - s * r * r */
338 fmadds fr1,fr2,fr3,fr1 /* r = r + 0.5 * r * (1 - s * r * r) */
339 fmuls fr3,fr1,fr0 /* r * s */
340 fmuls fr2,fr1,fr5 /* r * 0.5 */
341 fnmsubs fr3,fr1,fr3,fr4 /* 1 - s * r * r */
342 fmadds fr1,fr2,fr3,fr1 /* r = r + 0.5 * r * (1 - s * r * r) */