2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
15 * Copyright IBM Corp. 2007
17 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
20 #include <linux/types.h>
21 #include <linux/string.h>
22 #include <linux/kvm.h>
23 #include <linux/kvm_host.h>
24 #include <linux/highmem.h>
25 #include <asm/mmu-44x.h>
26 #include <asm/kvm_ppc.h>
27 #include <asm/kvm_44x.h>
31 #define PPC44x_TLB_USER_PERM_MASK (PPC44x_TLB_UX|PPC44x_TLB_UR|PPC44x_TLB_UW)
32 #define PPC44x_TLB_SUPER_PERM_MASK (PPC44x_TLB_SX|PPC44x_TLB_SR|PPC44x_TLB_SW)
34 static unsigned int kvmppc_tlb_44x_pos;
37 void kvmppc_dump_tlbs(struct kvm_vcpu *vcpu)
39 struct kvmppc_44x_tlbe *tlbe;
42 printk("vcpu %d TLB dump:\n", vcpu->vcpu_id);
43 printk("| %2s | %3s | %8s | %8s | %8s |\n",
44 "nr", "tid", "word0", "word1", "word2");
46 for (i = 0; i < PPC44x_TLB_SIZE; i++) {
47 tlbe = &vcpu_44x->guest_tlb[i];
48 if (tlbe->word0 & PPC44x_TLB_VALID)
49 printk(" G%2d | %02X | %08X | %08X | %08X |\n",
50 i, tlbe->tid, tlbe->word0, tlbe->word1,
54 for (i = 0; i < PPC44x_TLB_SIZE; i++) {
55 tlbe = &vcpu_44x->shadow_tlb[i];
56 if (tlbe->word0 & PPC44x_TLB_VALID)
57 printk(" S%2d | %02X | %08X | %08X | %08X |\n",
58 i, tlbe->tid, tlbe->word0, tlbe->word1,
64 static u32 kvmppc_44x_tlb_shadow_attrib(u32 attrib, int usermode)
66 /* Mask off reserved bits. */
67 attrib &= PPC44x_TLB_PERM_MASK|PPC44x_TLB_ATTR_MASK;
70 /* Guest is in supervisor mode, so we need to translate guest
71 * supervisor permissions into user permissions. */
72 attrib &= ~PPC44x_TLB_USER_PERM_MASK;
73 attrib |= (attrib & PPC44x_TLB_SUPER_PERM_MASK) << 3;
76 /* Make sure host can always access this memory. */
77 attrib |= PPC44x_TLB_SX|PPC44x_TLB_SR|PPC44x_TLB_SW;
82 /* Search the guest TLB for a matching entry. */
83 int kvmppc_44x_tlb_index(struct kvm_vcpu *vcpu, gva_t eaddr, unsigned int pid,
86 struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);
89 /* XXX Replace loop with fancy data structures. */
90 for (i = 0; i < PPC44x_TLB_SIZE; i++) {
91 struct kvmppc_44x_tlbe *tlbe = &vcpu_44x->guest_tlb[i];
94 if (eaddr < get_tlb_eaddr(tlbe))
97 if (eaddr > get_tlb_end(tlbe))
100 tid = get_tlb_tid(tlbe);
101 if (tid && (tid != pid))
104 if (!get_tlb_v(tlbe))
107 if (get_tlb_ts(tlbe) != as)
116 struct kvmppc_44x_tlbe *kvmppc_44x_itlb_search(struct kvm_vcpu *vcpu,
119 struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);
120 unsigned int as = !!(vcpu->arch.msr & MSR_IS);
123 index = kvmppc_44x_tlb_index(vcpu, eaddr, vcpu->arch.pid, as);
126 return &vcpu_44x->guest_tlb[index];
129 struct kvmppc_44x_tlbe *kvmppc_44x_dtlb_search(struct kvm_vcpu *vcpu,
132 struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);
133 unsigned int as = !!(vcpu->arch.msr & MSR_DS);
136 index = kvmppc_44x_tlb_index(vcpu, eaddr, vcpu->arch.pid, as);
139 return &vcpu_44x->guest_tlb[index];
142 static int kvmppc_44x_tlbe_is_writable(struct kvmppc_44x_tlbe *tlbe)
144 return tlbe->word2 & (PPC44x_TLB_SW|PPC44x_TLB_UW);
147 static void kvmppc_44x_shadow_release(struct kvm_vcpu *vcpu,
150 struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);
151 struct kvmppc_44x_tlbe *stlbe = &vcpu_44x->shadow_tlb[index];
152 struct page *page = vcpu_44x->shadow_pages[index];
154 if (get_tlb_v(stlbe)) {
155 if (kvmppc_44x_tlbe_is_writable(stlbe))
156 kvm_release_page_dirty(page);
158 kvm_release_page_clean(page);
162 void kvmppc_core_destroy_mmu(struct kvm_vcpu *vcpu)
166 for (i = 0; i <= tlb_44x_hwater; i++)
167 kvmppc_44x_shadow_release(vcpu, i);
170 void kvmppc_tlbe_set_modified(struct kvm_vcpu *vcpu, unsigned int i)
172 struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);
174 vcpu_44x->shadow_tlb_mod[i] = 1;
177 /* Caller must ensure that the specified guest TLB entry is safe to insert into
179 void kvmppc_mmu_map(struct kvm_vcpu *vcpu, u64 gvaddr, gfn_t gfn, u64 asid,
182 struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);
183 struct page *new_page;
184 struct kvmppc_44x_tlbe *stlbe;
188 /* Future optimization: don't overwrite the TLB entry containing the
189 * current PC (or stack?). */
190 victim = kvmppc_tlb_44x_pos++;
191 if (kvmppc_tlb_44x_pos > tlb_44x_hwater)
192 kvmppc_tlb_44x_pos = 0;
193 stlbe = &vcpu_44x->shadow_tlb[victim];
195 /* Get reference to new page. */
196 new_page = gfn_to_page(vcpu->kvm, gfn);
197 if (is_error_page(new_page)) {
198 printk(KERN_ERR "Couldn't get guest page for gfn %lx!\n", gfn);
199 kvm_release_page_clean(new_page);
202 hpaddr = page_to_phys(new_page);
204 /* Drop reference to old page. */
205 kvmppc_44x_shadow_release(vcpu, victim);
207 vcpu_44x->shadow_pages[victim] = new_page;
209 /* XXX Make sure (va, size) doesn't overlap any other
210 * entries. 440x6 user manual says the result would be
213 /* XXX what about AS? */
215 stlbe->tid = !(asid & 0xff);
217 /* Force TS=1 for all guest mappings. */
218 /* For now we hardcode 4KB mappings, but it will be important to
219 * use host large pages in the future. */
220 stlbe->word0 = (gvaddr & PAGE_MASK) | PPC44x_TLB_VALID | PPC44x_TLB_TS
222 stlbe->word1 = (hpaddr & 0xfffffc00) | ((hpaddr >> 32) & 0xf);
223 stlbe->word2 = kvmppc_44x_tlb_shadow_attrib(flags,
224 vcpu->arch.msr & MSR_PR);
225 kvmppc_tlbe_set_modified(vcpu, victim);
227 KVMTRACE_5D(STLB_WRITE, vcpu, victim,
228 stlbe->tid, stlbe->word0, stlbe->word1, stlbe->word2,
232 static void kvmppc_mmu_invalidate(struct kvm_vcpu *vcpu, gva_t eaddr,
233 gva_t eend, u32 asid)
235 struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);
236 unsigned int pid = !(asid & 0xff);
239 /* XXX Replace loop with fancy data structures. */
240 for (i = 0; i <= tlb_44x_hwater; i++) {
241 struct kvmppc_44x_tlbe *stlbe = &vcpu_44x->shadow_tlb[i];
244 if (!get_tlb_v(stlbe))
247 if (eend < get_tlb_eaddr(stlbe))
250 if (eaddr > get_tlb_end(stlbe))
253 tid = get_tlb_tid(stlbe);
254 if (tid && (tid != pid))
257 kvmppc_44x_shadow_release(vcpu, i);
259 kvmppc_tlbe_set_modified(vcpu, i);
260 KVMTRACE_5D(STLB_INVAL, vcpu, i,
261 stlbe->tid, stlbe->word0, stlbe->word1,
262 stlbe->word2, handler);
266 /* Invalidate all mappings on the privilege switch after PID has been changed.
267 * The guest always runs with PID=1, so we must clear the entire TLB when
268 * switching address spaces. */
269 void kvmppc_mmu_priv_switch(struct kvm_vcpu *vcpu, int usermode)
271 struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);
274 if (vcpu->arch.swap_pid) {
275 /* XXX Replace loop with fancy data structures. */
276 for (i = 0; i <= tlb_44x_hwater; i++) {
277 struct kvmppc_44x_tlbe *stlbe = &vcpu_44x->shadow_tlb[i];
279 /* Future optimization: clear only userspace mappings. */
280 kvmppc_44x_shadow_release(vcpu, i);
282 kvmppc_tlbe_set_modified(vcpu, i);
283 KVMTRACE_5D(STLB_INVAL, vcpu, i,
284 stlbe->tid, stlbe->word0, stlbe->word1,
285 stlbe->word2, handler);
287 vcpu->arch.swap_pid = 0;
290 vcpu->arch.shadow_pid = !usermode;
293 static int tlbe_is_host_safe(const struct kvm_vcpu *vcpu,
294 const struct kvmppc_44x_tlbe *tlbe)
298 if (!get_tlb_v(tlbe))
301 /* Does it match current guest AS? */
302 /* XXX what about IS != DS? */
303 if (get_tlb_ts(tlbe) != !!(vcpu->arch.msr & MSR_IS))
306 gpa = get_tlb_raddr(tlbe);
307 if (!gfn_to_memslot(vcpu->kvm, gpa >> PAGE_SHIFT))
308 /* Mapping is not for RAM. */
314 int kvmppc_44x_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws)
316 struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);
321 struct kvmppc_44x_tlbe *tlbe;
324 index = vcpu->arch.gpr[ra];
325 if (index > PPC44x_TLB_SIZE) {
326 printk("%s: index %d\n", __func__, index);
327 kvmppc_dump_vcpu(vcpu);
331 tlbe = &vcpu_44x->guest_tlb[index];
333 /* Invalidate shadow mappings for the about-to-be-clobbered TLBE. */
334 if (tlbe->word0 & PPC44x_TLB_VALID) {
335 eaddr = get_tlb_eaddr(tlbe);
336 asid = (tlbe->word0 & PPC44x_TLB_TS) | tlbe->tid;
337 kvmppc_mmu_invalidate(vcpu, eaddr, get_tlb_end(tlbe), asid);
341 case PPC44x_TLB_PAGEID:
342 tlbe->tid = vcpu->arch.mmucr & 0xff;
343 tlbe->word0 = vcpu->arch.gpr[rs];
346 case PPC44x_TLB_XLAT:
347 tlbe->word1 = vcpu->arch.gpr[rs];
350 case PPC44x_TLB_ATTRIB:
351 tlbe->word2 = vcpu->arch.gpr[rs];
358 if (tlbe_is_host_safe(vcpu, tlbe)) {
359 eaddr = get_tlb_eaddr(tlbe);
360 raddr = get_tlb_raddr(tlbe);
361 asid = (tlbe->word0 & PPC44x_TLB_TS) | tlbe->tid;
362 flags = tlbe->word2 & 0xffff;
364 /* Create a 4KB mapping on the host. If the guest wanted a
365 * large page, only the first 4KB is mapped here and the rest
366 * are mapped on the fly. */
367 kvmppc_mmu_map(vcpu, eaddr, raddr >> PAGE_SHIFT, asid, flags);
370 KVMTRACE_5D(GTLB_WRITE, vcpu, index,
371 tlbe->tid, tlbe->word0, tlbe->word1, tlbe->word2,
377 int kvmppc_44x_emul_tlbsx(struct kvm_vcpu *vcpu, u8 rt, u8 ra, u8 rb, u8 rc)
381 unsigned int as = get_mmucr_sts(vcpu);
382 unsigned int pid = get_mmucr_stid(vcpu);
384 ea = vcpu->arch.gpr[rb];
386 ea += vcpu->arch.gpr[ra];
388 index = kvmppc_44x_tlb_index(vcpu, ea, pid, as);
391 vcpu->arch.cr &= ~0x20000000;
393 vcpu->arch.cr |= 0x20000000;
395 vcpu->arch.gpr[rt] = index;